From patchwork Sat Apr 11 08:02:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Pandey X-Patchwork-Id: 202189 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53461C2BA2B for ; Sat, 11 Apr 2020 08:04:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 229BD2078E for ; Sat, 11 Apr 2020 08:04:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="S5blbag5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726140AbgDKIED (ORCPT ); Sat, 11 Apr 2020 04:04:03 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:54469 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726047AbgDKIEC (ORCPT ); Sat, 11 Apr 2020 04:04:02 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1586592242; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=KXy1loHb2FhxhHhKQrd5okL0GUCoCdYflO1LTaz/12I=; b=S5blbag5tpnd0vEndOqBuSgNzD5QTI63+pp18sL5epso4N5F6kMKXetRqwgwHULdNR06r/ta UArH/bGe3oY828Ap2pSR3UgBEq9UCEfhHr4EaJ+9gyalRSL5KX9Tp4sdP/T+YKDdQgzoUn+D rDtq8+E+5odRGFae3Ms0RxXRbVM= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e9179e9.7f727dc2f0a0-smtp-out-n03; Sat, 11 Apr 2020 08:03:53 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 0DCADC433F2; Sat, 11 Apr 2020 08:03:53 +0000 (UTC) Received: from c-ajitp-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ajitp) by smtp.codeaurora.org (Postfix) with ESMTPSA id 857D6C433CB; Sat, 11 Apr 2020 08:03:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 857D6C433CB Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=ajitp@codeaurora.org From: Ajit Pandey To: alsa-devel@alsa-project.org, broonie@kernel.org, devicetree@vger.kernel.org, plai@codeaurora.org, bgoswami@codeaurora.org, srinivas.kandagatla@linaro.org Cc: linux-kernel@vger.kernel.org, tiwai@suse.com, Ajit Pandey Subject: [PATCH 02/11] ASoC: qcom: lpass: Add struct lpass_dai to store dai clocks pointer Date: Sat, 11 Apr 2020 13:32:42 +0530 Message-Id: <1586592171-31644-3-git-send-email-ajitp@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1586592171-31644-1-git-send-email-ajitp@codeaurora.org> References: <1586592171-31644-1-git-send-email-ajitp@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org lpass_dai will store clocks related to respective dai's and it will be initialized during probe based on variant clock names. Signed-off-by: Ajit Pandey --- sound/soc/qcom/lpass-cpu.c | 89 ++++++++++++++++++++++++++-------------------- sound/soc/qcom/lpass.h | 18 +++++----- 2 files changed, 61 insertions(+), 46 deletions(-) diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c index dbce7e9..492f27b 100644 --- a/sound/soc/qcom/lpass-cpu.c +++ b/sound/soc/qcom/lpass-cpu.c @@ -23,13 +23,15 @@ static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id, unsigned int freq, int dir) { struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); - int ret; - - ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq); - if (ret) - dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n", - freq, ret); + struct lpass_dai *dai_data = drvdata->dai_priv[dai->driver->id]; + int ret = 0; + if (dai_data->osr_clk != NULL) { + ret = clk_set_rate(dai_data->osr_clk, freq); + if (ret) + dev_err(dai->dev, "error setting mi2s osrclk to %u:%d\n", + freq, ret); + } return ret; } @@ -37,18 +39,22 @@ static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); + struct lpass_dai *dai_data = drvdata->dai_priv[dai->driver->id]; int ret; - ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]); - if (ret) { - dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret); - return ret; + if (dai_data->osr_clk != NULL) { + ret = clk_prepare_enable(dai_data->osr_clk); + if (ret) { + dev_err(dai->dev, + "error in enabling mi2s osr clk: %d\n", ret); + return ret; + } } - ret = clk_prepare_enable(drvdata->mi2s_bit_clk[dai->driver->id]); + ret = clk_prepare_enable(dai_data->bit_clk); if (ret) { dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret); - clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); + clk_disable_unprepare(dai_data->osr_clk); return ret; } @@ -59,16 +65,18 @@ static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); + struct lpass_dai *dai_data = drvdata->dai_priv[dai->driver->id]; - clk_disable_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]); + clk_disable_unprepare(dai_data->bit_clk); - clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); + clk_disable_unprepare(dai_data->osr_clk); } static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); + struct lpass_dai *dai_data = drvdata->dai_priv[dai->driver->id]; snd_pcm_format_t format = params_format(params); unsigned int channels = params_channels(params); unsigned int rate = params_rate(params); @@ -163,8 +171,7 @@ static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, return ret; } - ret = clk_set_rate(drvdata->mi2s_bit_clk[dai->driver->id], - rate * bitwidth * 2); + ret = clk_set_rate(dai_data->bit_clk, rate * bitwidth * 2); if (ret) { dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n", rate * bitwidth * 2, ret); @@ -413,6 +420,25 @@ static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg) .cache_type = REGCACHE_FLAT, }; +static int lpass_init_dai_clocks(struct device *dev, + struct lpass_data *drvdata) +{ + struct lpass_dai *dai; + struct lpass_variant *v = drvdata->variant; + int i; + + for (i = 0; i < v->num_dai; i++) { + + dai = drvdata->dai_priv[i]; + + dai->osr_clk = devm_clk_get_optional(dev, + v->dai_osr_clk_names[i]); + dai->bit_clk = devm_clk_get(dev, v->dai_bit_clk_names[i]); + } + + return 0; +} + int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) { struct lpass_data *drvdata; @@ -421,7 +447,7 @@ int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) struct lpass_variant *variant; struct device *dev = &pdev->dev; const struct of_device_id *match; - int ret, i, dai_id; + int ret, i; dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0); if (dsp_of_node) { @@ -467,28 +493,15 @@ int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) variant->init(pdev); for (i = 0; i < variant->num_dai; i++) { - dai_id = variant->dai_driver[i].id; - drvdata->mi2s_osr_clk[dai_id] = devm_clk_get(&pdev->dev, - variant->dai_osr_clk_names[i]); - if (IS_ERR(drvdata->mi2s_osr_clk[dai_id])) { - dev_warn(&pdev->dev, - "%s() error getting optional %s: %ld\n", - __func__, - variant->dai_osr_clk_names[i], - PTR_ERR(drvdata->mi2s_osr_clk[dai_id])); - - drvdata->mi2s_osr_clk[dai_id] = NULL; - } + drvdata->dai_priv[i] = devm_kzalloc(dev, + sizeof(struct lpass_dai), + GFP_KERNEL); + } - drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(&pdev->dev, - variant->dai_bit_clk_names[i]); - if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) { - dev_err(&pdev->dev, - "error getting %s: %ld\n", - variant->dai_bit_clk_names[i], - PTR_ERR(drvdata->mi2s_bit_clk[dai_id])); - return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]); - } + ret = lpass_init_dai_clocks(dev, drvdata); + if (ret) { + dev_err(&pdev->dev, "error intializing dai clock: %d\n", ret); + return ret; } drvdata->ahbix_clk = devm_clk_get(&pdev->dev, "ahbix-clk"); diff --git a/sound/soc/qcom/lpass.h b/sound/soc/qcom/lpass.h index 17113d3..b729686 100644 --- a/sound/soc/qcom/lpass.h +++ b/sound/soc/qcom/lpass.h @@ -13,9 +13,14 @@ #include #include -#define LPASS_AHBIX_CLOCK_FREQUENCY 131072000 -#define LPASS_MAX_MI2S_PORTS (8) -#define LPASS_MAX_DMA_CHANNELS (8) +#define LPASS_AHBIX_CLOCK_FREQUENCY 131072000 +#define LPASS_MAX_MI2S_PORTS (8) +#define LPASS_MAX_DMA_CHANNELS (8) + +struct lpass_dai { + struct clk *osr_clk; + struct clk *bit_clk; +}; /* Both the CPU DAI and platform drivers will access this data */ struct lpass_data { @@ -23,11 +28,8 @@ struct lpass_data { /* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */ struct clk *ahbix_clk; - /* MI2S system clock */ - struct clk *mi2s_osr_clk[LPASS_MAX_MI2S_PORTS]; - - /* MI2S bit clock (derived from system clock by a divider */ - struct clk *mi2s_bit_clk[LPASS_MAX_MI2S_PORTS]; + /* MI2S dai specific configuration */ + struct lpass_dai *dai_priv[LPASS_MAX_MI2S_PORTS]; /* low-power audio interface (LPAIF) registers */ void __iomem *lpaif; From patchwork Sat Apr 11 08:02:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Pandey X-Patchwork-Id: 202188 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 020B7C2BBC7 for ; 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Sat, 11 Apr 2020 08:04:03 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 4ABB8C44788; Sat, 11 Apr 2020 08:04:02 +0000 (UTC) Received: from c-ajitp-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ajitp) by smtp.codeaurora.org (Postfix) with ESMTPSA id 8C4B2C433F2; Sat, 11 Apr 2020 08:03:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8C4B2C433F2 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=ajitp@codeaurora.org From: Ajit Pandey To: alsa-devel@alsa-project.org, broonie@kernel.org, devicetree@vger.kernel.org, plai@codeaurora.org, bgoswami@codeaurora.org, srinivas.kandagatla@linaro.org Cc: linux-kernel@vger.kernel.org, tiwai@suse.com, Ajit Pandey Subject: [PATCH 03/11] ASoC: qcom: Add common array to initialize soc based core clocks Date: Sat, 11 Apr 2020 13:32:43 +0530 Message-Id: <1586592171-31644-4-git-send-email-ajitp@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1586592171-31644-1-git-send-email-ajitp@codeaurora.org> References: <1586592171-31644-1-git-send-email-ajitp@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org lpass variants have their own soc specific clocks that needs to be enable for MI2S audio support. Added a common variable in drvdata to initialize such clocks using bulk clk api. Such clock names is still defined in variants specific data and needs to fetched during init. Signed-off-by: Ajit Pandey --- sound/soc/qcom/lpass-apq8016.c | 39 ++++++++++++++++++--------------------- sound/soc/qcom/lpass.h | 10 +++++++--- 2 files changed, 25 insertions(+), 24 deletions(-) diff --git a/sound/soc/qcom/lpass-apq8016.c b/sound/soc/qcom/lpass-apq8016.c index 6575da5..cef4661 100644 --- a/sound/soc/qcom/lpass-apq8016.c +++ b/sound/soc/qcom/lpass-apq8016.c @@ -161,33 +161,26 @@ static int apq8016_lpass_free_dma_channel(struct lpass_data *drvdata, int chan) static int apq8016_lpass_init(struct platform_device *pdev) { struct lpass_data *drvdata = platform_get_drvdata(pdev); + struct lpass_variant *variant = drvdata->variant; struct device *dev = &pdev->dev; - int ret; + int ret, i; - drvdata->pcnoc_mport_clk = devm_clk_get(dev, "pcnoc-mport-clk"); - if (IS_ERR(drvdata->pcnoc_mport_clk)) { - dev_err(&pdev->dev, "error getting pcnoc-mport-clk: %ld\n", - PTR_ERR(drvdata->pcnoc_mport_clk)); - return PTR_ERR(drvdata->pcnoc_mport_clk); - } + drvdata->clks = devm_kcalloc(dev, variant->num_clks, + sizeof(*drvdata->clks), GFP_KERNEL); + drvdata->num_clks = variant->num_clks; + + for (i = 0; i < drvdata->num_clks; i++) + drvdata->clks[i].id = variant->clk_name[i]; - ret = clk_prepare_enable(drvdata->pcnoc_mport_clk); + ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks); if (ret) { - dev_err(&pdev->dev, "Error enabling pcnoc-mport-clk: %d\n", - ret); + dev_err(dev, "Failed to get clocks %d\n", ret); return ret; } - drvdata->pcnoc_sway_clk = devm_clk_get(dev, "pcnoc-sway-clk"); - if (IS_ERR(drvdata->pcnoc_sway_clk)) { - dev_err(&pdev->dev, "error getting pcnoc-sway-clk: %ld\n", - PTR_ERR(drvdata->pcnoc_sway_clk)); - return PTR_ERR(drvdata->pcnoc_sway_clk); - } - - ret = clk_prepare_enable(drvdata->pcnoc_sway_clk); + ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks); if (ret) { - dev_err(&pdev->dev, "Error enabling pcnoc_sway_clk: %d\n", ret); + dev_err(dev, "ao8016 clk_enable failed\n"); return ret; } @@ -198,8 +191,7 @@ static int apq8016_lpass_exit(struct platform_device *pdev) { struct lpass_data *drvdata = platform_get_drvdata(pdev); - clk_disable_unprepare(drvdata->pcnoc_mport_clk); - clk_disable_unprepare(drvdata->pcnoc_sway_clk); + clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks); return 0; } @@ -220,6 +212,11 @@ static int apq8016_lpass_exit(struct platform_device *pdev) .wrdma_reg_stride = 0x1000, .wrdma_channel_start = 5, .wrdma_channels = 2, + .clk_name = (const char*[]) { + "pcnoc-mport-clk", + "pcnoc-sway-clk", + }, + .num_clks = 2, .dai_driver = apq8016_lpass_cpu_dai_driver, .num_dai = ARRAY_SIZE(apq8016_lpass_cpu_dai_driver), .dai_osr_clk_names = (const char *[]) { diff --git a/sound/soc/qcom/lpass.h b/sound/soc/qcom/lpass.h index b729686..279cd02 100644 --- a/sound/soc/qcom/lpass.h +++ b/sound/soc/qcom/lpass.h @@ -49,9 +49,9 @@ struct lpass_data { /* used it for handling interrupt per dma channel */ struct snd_pcm_substream *substream[LPASS_MAX_DMA_CHANNELS]; - /* 8016 specific */ - struct clk *pcnoc_mport_clk; - struct clk *pcnoc_sway_clk; + /* SOC specific clock list */ + struct clk_bulk_data *clks; + int num_clks; }; @@ -87,6 +87,10 @@ struct lpass_variant { int num_dai; const char * const *dai_osr_clk_names; const char * const *dai_bit_clk_names; + + /* SOC specific clocks configuration */ + const char **clk_name; + int num_clks; }; /* register the platform driver from the CPU DAI driver */ From patchwork Sat Apr 11 08:02:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Pandey X-Patchwork-Id: 202187 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E18ECC2BB85 for ; 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Sat, 11 Apr 2020 08:04:20 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id C1725C433F2; Sat, 11 Apr 2020 08:04:19 +0000 (UTC) Received: from c-ajitp-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ajitp) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3C6D9C433CB; Sat, 11 Apr 2020 08:04:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3C6D9C433CB Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=ajitp@codeaurora.org From: Ajit Pandey To: alsa-devel@alsa-project.org, broonie@kernel.org, devicetree@vger.kernel.org, plai@codeaurora.org, bgoswami@codeaurora.org, srinivas.kandagatla@linaro.org Cc: linux-kernel@vger.kernel.org, tiwai@suse.com, Ajit Pandey Subject: [PATCH 06/11] dt-bindings: sound: Add bindings related to lpass-cpu configuration Date: Sat, 11 Apr 2020 13:32:46 +0530 Message-Id: <1586592171-31644-7-git-send-email-ajitp@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1586592171-31644-1-git-send-email-ajitp@codeaurora.org> References: <1586592171-31644-1-git-send-email-ajitp@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add header defining dts properties related to lpass cpu MI2S dai's. Signed-off-by: Ajit Pandey --- include/dt-bindings/sound/qcom,lpass.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 include/dt-bindings/sound/qcom,lpass.h diff --git a/include/dt-bindings/sound/qcom,lpass.h b/include/dt-bindings/sound/qcom,lpass.h new file mode 100644 index 00000000..4e6c6bc --- /dev/null +++ b/include/dt-bindings/sound/qcom,lpass.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * lpass.h -- DT bindings properties related to LPASS MI2S dai's + */ + +#ifndef _DT_BINDINGS_LPASS_H +#define _DT_BINDINGS_LPASS_H + +/* MI2S dai id */ +#define MI2S_PRIMARY 0 +#define MI2S_SECONDARY 1 +#define MI2S_TERTIARY 2 +#define MI2S_QUATERNARY 3 + +/* MI2S dai's data line mask */ +#define SD0 1 +#define SD1 2 +#define SD2 3 +#define SD3 4 + +/*MI2S dai' loopback mask */ +#define DISABLE 0 +#define ENABLE 1 + +/* MI2S dai's wssrc mask */ +#define INTERNAL 0 +#define EXTERNAL 1 + +#endif /* __DT_BINDINGS_LPASS_H__ */ From patchwork Sat Apr 11 08:02:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Pandey X-Patchwork-Id: 202186 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A144C2BB85 for ; Sat, 11 Apr 2020 08:04:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3A91B20692 for ; Sat, 11 Apr 2020 08:04:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="QUWnkVIE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726716AbgDKIEg (ORCPT ); Sat, 11 Apr 2020 04:04:36 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:25069 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726689AbgDKIEc (ORCPT ); Sat, 11 Apr 2020 04:04:32 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1586592271; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=Bnz6MJ/qFfPiLKy+tJVoenTR3jVnJA77P0RTyIyn02s=; b=QUWnkVIEdgQeUXtS4j8MVgbLlEVF6ASWF9lhEOE5xUAJfLBXP8cQqL+EmFlWVcRwnWfQ/4wp F8MPciKE6o4O0pStFOfWyAl5tWL7pJLzFbwqhfnSN5lO4nycA1G2QeWEtCq/wCWrJWKy33OS LfLDH4GvztgIC2R++nDHGhxN3nA= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e917a0f.7f0d06be3768-smtp-out-n04; Sat, 11 Apr 2020 08:04:31 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id BE094C433F2; Sat, 11 Apr 2020 08:04:30 +0000 (UTC) Received: from c-ajitp-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ajitp) by smtp.codeaurora.org (Postfix) with ESMTPSA id B1E94C433CB; Sat, 11 Apr 2020 08:04:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B1E94C433CB Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=ajitp@codeaurora.org From: Ajit Pandey To: alsa-devel@alsa-project.org, broonie@kernel.org, devicetree@vger.kernel.org, plai@codeaurora.org, bgoswami@codeaurora.org, srinivas.kandagatla@linaro.org Cc: linux-kernel@vger.kernel.org, tiwai@suse.com, Ajit Pandey Subject: [PATCH 08/11] ASoC: qcom : lpass: Add support to configure dai's connection mode Date: Sat, 11 Apr 2020 13:32:48 +0530 Message-Id: <1586592171-31644-9-git-send-email-ajitp@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1586592171-31644-1-git-send-email-ajitp@codeaurora.org> References: <1586592171-31644-1-git-send-email-ajitp@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Few dai configuration depends on board layout and use cases. Add new variables in dai_data to configure dai modes based on values defined in device tree configuration of board. Signed-off-by: Ajit Pandey --- sound/soc/qcom/lpass-cpu.c | 70 ++++++++++++++++++++++++++++++++++++++++++++-- sound/soc/qcom/lpass.h | 6 ++++ 2 files changed, 74 insertions(+), 2 deletions(-) diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c index 006ba5a..f96338f 100644 --- a/sound/soc/qcom/lpass-cpu.c +++ b/sound/soc/qcom/lpass-cpu.c @@ -90,8 +90,9 @@ static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, return bitwidth; } - regval = LPAIF_I2SCTL(v, LOOPBACK_DISABLE); - regval |= LPAIF_I2SCTL(v, WSSRC_INTERNAL); + /* default to Loopback disable & wssrc internal */ + regval = dai_data->loopback << (LPAIF_I2SCTL(v, LOOPBACK_SHIFT)); + regval |= dai_data->wssrc << (LPAIF_I2SCTL(v, WSSRC_SHIFT)); switch (bitwidth) { case 16: @@ -172,6 +173,28 @@ static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, return ret; } + /* Overwrite spk & mic mode bits with device tree value if specified */ + if (dai_data->spkmode != 0) { + regval = dai_data->spkmode << (LPAIF_I2SCTL(v, SPKMODE_SHIFT)); + ret = regmap_update_bits(drvdata->lpaif_map, + LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), + LPAIF_I2SCTL(v, SPKMODE_MASK), regval); + if (ret) + dev_err(dai->dev, "error writing to i2sctl reg: %d\n", + ret); + } + + + if (dai_data->micmode != 0) { + regval = dai_data->micmode << (LPAIF_I2SCTL(v, MICMODE_SHIFT)); + ret = regmap_update_bits(drvdata->lpaif_map, + LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), + LPAIF_I2SCTL(v, MICMODE_MASK), regval); + if (ret) + dev_err(dai->dev, "error writing to i2sctl reg: %d\n", + ret); + } + ret = clk_set_rate(dai_data->bit_clk, rate * bitwidth * 2); if (ret) { dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n", @@ -423,6 +446,46 @@ static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg) .cache_type = REGCACHE_FLAT, }; +static void of_qcom_parse_dai_data(struct device *dev, + struct lpass_data *drvdata) +{ + struct device_node *node; + struct lpass_dai *dai; + int ret; + + for_each_child_of_node(dev->of_node, node) { + int id; + + ret = of_property_read_u32(node, "id", &id); + if (ret || id < 0 || id >= LPASS_MAX_MI2S_PORTS) { + dev_err(dev, "valid dai id not found:%d\n", ret); + continue; + } + + dai = drvdata->dai_priv[id]; + switch (id) { + case MI2S_PRIMARY... MI2S_QUATERNARY: + /* MI2S specific properties */ + ret = of_property_read_u32(node, "qcom,spkmode-mask", + &dai->spkmode); + + ret = of_property_read_u32(node, "qcom,micmode-mask", + &dai->micmode); + + ret = of_property_read_u32(node, "qcom,wssrc-mask", + &dai->wssrc); + + ret = of_property_read_u32(node, "qcom,loopback-mask", + &dai->loopback); + + break; + default: + dev_err(dev, "valid dai not found:%d\n", id); + break; + } + } +} + static int lpass_init_dai_clocks(struct device *dev, struct lpass_data *drvdata) { @@ -501,6 +564,9 @@ int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) GFP_KERNEL); } + /* parse dai data from dts */ + of_qcom_parse_dai_data(dev, drvdata); + ret = lpass_init_dai_clocks(dev, drvdata); if (ret) { dev_err(&pdev->dev, "error intializing dai clock: %d\n", ret); diff --git a/sound/soc/qcom/lpass.h b/sound/soc/qcom/lpass.h index 384f4b8..960ee97 100644 --- a/sound/soc/qcom/lpass.h +++ b/sound/soc/qcom/lpass.h @@ -12,6 +12,7 @@ #include #include #include +#include #define LPASS_AHBIX_CLOCK_FREQUENCY 131072000 #define LPASS_MAX_MI2S_PORTS (8) @@ -23,6 +24,11 @@ struct lpass_dai { struct clk *osr_clk; struct clk *bit_clk; + + uint32_t spkmode; + uint32_t micmode; + uint32_t wssrc; + uint32_t loopback; }; /* Both the CPU DAI and platform drivers will access this data */ From patchwork Sat Apr 11 08:02:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Pandey X-Patchwork-Id: 202185 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C67FEC2BA2B for ; Sat, 11 Apr 2020 08:04:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9677120692 for ; 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Sat, 11 Apr 2020 08:04:43 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id F302DC432C2; Sat, 11 Apr 2020 08:04:41 +0000 (UTC) Received: from c-ajitp-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ajitp) by smtp.codeaurora.org (Postfix) with ESMTPSA id 89612C433F2; Sat, 11 Apr 2020 08:04:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 89612C433F2 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=ajitp@codeaurora.org From: Ajit Pandey To: alsa-devel@alsa-project.org, broonie@kernel.org, devicetree@vger.kernel.org, plai@codeaurora.org, bgoswami@codeaurora.org, srinivas.kandagatla@linaro.org Cc: linux-kernel@vger.kernel.org, tiwai@suse.com, Ajit Pandey Subject: [PATCH 10/11] ASoC: qcom: lpass-sc7180: Add platform driver for lpass audio Date: Sat, 11 Apr 2020 13:32:50 +0530 Message-Id: <1586592171-31644-11-git-send-email-ajitp@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1586592171-31644-1-git-send-email-ajitp@codeaurora.org> References: <1586592171-31644-1-git-send-email-ajitp@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Create a platform driver for configuring sc7180 lpass core I2S and DMA configuration to support playback & capture to external codecs connected over primary & secondary MI2S interfaces. Signed-off-by: Ajit Pandey --- sound/soc/qcom/Kconfig | 5 ++ sound/soc/qcom/Makefile | 2 + sound/soc/qcom/lpass-sc7180.c | 192 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 199 insertions(+) create mode 100644 sound/soc/qcom/lpass-sc7180.c diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig index 6008685..23fd9e6 100644 --- a/sound/soc/qcom/Kconfig +++ b/sound/soc/qcom/Kconfig @@ -24,6 +24,11 @@ config SND_SOC_LPASS_APQ8016 select SND_SOC_LPASS_CPU select SND_SOC_LPASS_PLATFORM +config SND_SOC_LPASS_SC7180 + tristate + select SND_SOC_LPASS_CPU + select SND_SOC_LPASS_PLATFORM + config SND_SOC_STORM tristate "ASoC I2S support for Storm boards" depends on SND_SOC_QCOM diff --git a/sound/soc/qcom/Makefile b/sound/soc/qcom/Makefile index 41b2c7a..7972c94 100644 --- a/sound/soc/qcom/Makefile +++ b/sound/soc/qcom/Makefile @@ -4,11 +4,13 @@ snd-soc-lpass-cpu-objs := lpass-cpu.o snd-soc-lpass-platform-objs := lpass-platform.o snd-soc-lpass-ipq806x-objs := lpass-ipq806x.o snd-soc-lpass-apq8016-objs := lpass-apq8016.o +snd-soc-lpass-sc7180-objs := lpass-sc7180.o obj-$(CONFIG_SND_SOC_LPASS_CPU) += snd-soc-lpass-cpu.o obj-$(CONFIG_SND_SOC_LPASS_PLATFORM) += snd-soc-lpass-platform.o obj-$(CONFIG_SND_SOC_LPASS_IPQ806X) += snd-soc-lpass-ipq806x.o obj-$(CONFIG_SND_SOC_LPASS_APQ8016) += snd-soc-lpass-apq8016.o +obj-$(CONFIG_SND_SOC_LPASS_SC7180) += snd-soc-lpass-sc7180.o # Machine snd-soc-storm-objs := storm.o diff --git a/sound/soc/qcom/lpass-sc7180.c b/sound/soc/qcom/lpass-sc7180.c new file mode 100644 index 00000000..879f3a5 --- /dev/null +++ b/sound/soc/qcom/lpass-sc7180.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * lpass-sc7180.c -- ALSA SoC platform-machine driver for QTi LPASS + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "lpass-lpaif-reg.h" +#include "lpass.h" + +static struct snd_soc_dai_driver sc7180_lpass_cpu_dai_driver[] = { + [MI2S_PRIMARY] = { + .id = MI2S_PRIMARY, + .name = "Primary MI2S", + .playback = { + .stream_name = "Primary Playback", + .formats = SNDRV_PCM_FMTBIT_S16, + .rates = SNDRV_PCM_RATE_48000, + .rate_min = 48000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + }, + .capture = { + .stream_name = "Primary Capture", + .formats = SNDRV_PCM_FMTBIT_S16, + .rates = SNDRV_PCM_RATE_48000, + .rate_min = 48000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + }, + .probe = &asoc_qcom_lpass_cpu_dai_probe, + .ops = &asoc_qcom_lpass_cpu_dai_ops, + }, + + [MI2S_SECONDARY] = { + .id = MI2S_SECONDARY, + .name = "Secondary MI2S", + .playback = { + .stream_name = "Secondary Playback", + .formats = SNDRV_PCM_FMTBIT_S16, + .rates = SNDRV_PCM_RATE_48000, + .rate_min = 48000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + }, + .probe = &asoc_qcom_lpass_cpu_dai_probe, + .ops = &asoc_qcom_lpass_cpu_dai_ops, + }, +}; + +static int sc7180_lpass_alloc_dma_channel(struct lpass_data *drvdata, + int direction) +{ + struct lpass_variant *v = drvdata->variant; + int chan = 0; + + if (direction == SNDRV_PCM_STREAM_PLAYBACK) { + chan = find_first_zero_bit(&drvdata->dma_ch_bit_map, + v->rdma_channels); + + if (chan >= v->rdma_channels) + return -EBUSY; + } else { + chan = find_next_zero_bit(&drvdata->dma_ch_bit_map, + v->wrdma_channel_start + + v->wrdma_channels, + v->wrdma_channel_start); + + if (chan >= v->wrdma_channel_start + v->wrdma_channels) + return -EBUSY; + } + + set_bit(chan, &drvdata->dma_ch_bit_map); + + return chan; +} + +static int sc7180_lpass_free_dma_channel(struct lpass_data *drvdata, int chan) +{ + clear_bit(chan, &drvdata->dma_ch_bit_map); + + return 0; +} + +static int sc7180_lpass_init(struct platform_device *pdev) +{ + struct lpass_data *drvdata = platform_get_drvdata(pdev); + struct lpass_variant *variant = drvdata->variant; + struct device *dev = &pdev->dev; + int ret, i; + + drvdata->clks = devm_kcalloc(dev, variant->num_clks, + sizeof(*drvdata->clks), GFP_KERNEL); + drvdata->num_clks = variant->num_clks; + + for (i = 0; i < drvdata->num_clks; i++) + drvdata->clks[i].id = variant->clk_name[i]; + + ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks); + if (ret) { + dev_err(dev, "Failed to get clocks %d\n", ret); + return ret; + } + + ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks); + if (ret) { + dev_err(dev, "sc7180 clk_enable failed\n"); + return ret; + } + + return 0; +} + +static int sc7180_lpass_exit(struct platform_device *pdev) +{ + struct lpass_data *drvdata = platform_get_drvdata(pdev); + + clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks); + + return 0; +} + +static struct lpass_variant sc7180_data = { + .i2sctrl_reg_base = 0x1000, + .i2sctrl_reg_stride = 0x1000, + .i2s_ports = 3, + .irq_reg_base = 0x9000, + .irq_reg_stride = 0x1000, + .irq_ports = 3, + .rdma_reg_base = 0xC000, + .rdma_reg_stride = 0x1000, + .rdma_channels = 5, + .dmactl_audif_start = 1, + .wrdma_reg_base = 0x18000, + .wrdma_reg_stride = 0x1000, + .wrdma_channel_start = 5, + .wrdma_channels = 4, + .id = LPASS_VARIANT_V2, + .clk_name = (const char*[]) { + "noc", + "audio-core", + "sysnoc_mport", + }, + .num_clks = 3, + .dai_driver = sc7180_lpass_cpu_dai_driver, + .num_dai = ARRAY_SIZE(sc7180_lpass_cpu_dai_driver), + .dai_osr_clk_names = (const char *[]) { + "mclk0", + "null", + }, + .dai_bit_clk_names = (const char *[]) { + "pri_ibit", + "sec_ibit", + }, + .init = sc7180_lpass_init, + .exit = sc7180_lpass_exit, + .alloc_dma_channel = sc7180_lpass_alloc_dma_channel, + .free_dma_channel = sc7180_lpass_free_dma_channel, + +}; + +static const struct of_device_id sc7180_lpass_cpu_device_id[] = { + {.compatible = "qcom,lpass-cpu-sc7180", .data = &sc7180_data}, + {} +}; + +static struct platform_driver sc7180_lpass_cpu_platform_driver = { + .driver = { + .name = "sc7180-lpass-cpu", + .of_match_table = of_match_ptr(sc7180_lpass_cpu_device_id), + }, + .probe = asoc_qcom_lpass_cpu_platform_probe, + .remove = asoc_qcom_lpass_cpu_platform_probe, +}; + +module_platform_driver(sc7180_lpass_cpu_platform_driver); + +MODULE_DESCRIPTION("SC7180 LPASS CPU DRIVER"); +MODULE_LICENSE("GPL v2");