From patchwork Thu Aug 17 03:25:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 110293 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1622191qge; Wed, 16 Aug 2017 20:26:13 -0700 (PDT) X-Received: by 10.98.23.69 with SMTP id 66mr3847939pfx.305.1502940373293; Wed, 16 Aug 2017 20:26:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502940373; cv=none; d=google.com; s=arc-20160816; b=WDbgUagUen2pohcYWlLcxIGil/BLEPH/IaLcr2CKpjlwEFw+3KhtEEsqfQbBOJuFdZ ZMh2eFxZEaNVw5XObiSL1o2TmSlQ75durqrsNC2oRBD21HIWacBqWnTcfc+0QUzJs3Qs juTSmsHITt5BQbONUIXV8JAFo+KsNo77AXOK8c72mUaAul3wAqyKjap212SBwvDO89QM hxcV0VtdwucrROYoVG40i2HfRMa+3j4R0hFQ7ZAM0a7JvaEzCli68A9ZxctOohW6/2hj orG2Rpa+wxMwi7WxBVE0aV6S9igKqKyz+JQuAh5TXPn+fW522nUN7XXAX2IuvTKGfHCS RBoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=i+RRu7YjSlMRtqzOYrbT38esgLWwPdi474cVUCEVmNs=; b=n3GNzHKVfomMfjLywhYI5wS8TjyYVBJtOR4EmsnM8HQxgg77CvzKwHDepoFM+Rotyl Fp45gpvFIVPkCFgc1ObvfN2TR8QoP6DIoT6fT1HTjy11EGMifE5k21YQwDXyTAwuItLf kChD+4ASRe5AC9p3Cu5d9eUwJYih1i5hTkAu+UKgHg8zi7NNKplJY70GRJOcC5c8+qg+ SJ7N667mDrEetZ84lhOYuiklweEY95mWXICJWljRZg9J43B+jib9Z3YX4atDoPWa0cj1 Dgtt+ZyfXFtrGEXHzwpqX3/KJ0+BvTEZOtH4rBOxrM+95QBHaF3BMwF3L87C35/GiQKy wDgg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l8si1574283pli.304.2017.08.16.20.26.12; Wed, 16 Aug 2017 20:26:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752202AbdHQDZj (ORCPT + 26 others); Wed, 16 Aug 2017 23:25:39 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:4013 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751549AbdHQDZh (ORCPT ); Wed, 16 Aug 2017 23:25:37 -0400 Received: from 172.30.72.60 (EHLO DGGEMS407-HUB.china.huawei.com) ([172.30.72.60]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFI21414; Thu, 17 Aug 2017 11:25:28 +0800 (CST) Received: from localhost (10.177.23.32) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.301.0; Thu, 17 Aug 2017 11:25:20 +0800 From: Ding Tianhong To: , , , , , , , , CC: Ding Tianhong Subject: [PATCH net v2 1/2] Revert commit 1a8b6d76dc5b ("net:add one common config...") Date: Thu, 17 Aug 2017 11:25:15 +0800 Message-ID: <1502940316-13384-2-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1502940316-13384-1-git-send-email-dingtianhong@huawei.com> References: <1502940316-13384-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020204.59950CA9.005C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 64dbe2e65100cde6982a9bb328c3a722 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING has been added to indicate that Relaxed Ordering Attributes (RO) should not be used for Transaction Layer Packets (TLP) targeted toward these affected Root Port, it will clear the bit4 in the PCIe Device Control register, so the PCIe device drivers could query PCIe configuration space to determine if it can send TLPs to Root Port with the Relaxed Ordering Attributes set. With this new flag we don't need the config ARCH_WANT_RELAX_ORDER to control the Relaxed Ordering Attributes for the ixgbe drivers just like the commit 1a8b6d76dc5b ("net:add one common config...") did, so revert this commit. Signed-off-by: Ding Tianhong --- arch/Kconfig | 3 --- arch/sparc/Kconfig | 1 - drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 2 +- 3 files changed, 1 insertion(+), 5 deletions(-) -- 1.8.3.1 diff --git a/arch/Kconfig b/arch/Kconfig index 21d0089..00cfc63 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -928,9 +928,6 @@ config STRICT_MODULE_RWX and non-text memory will be made non-executable. This provides protection against certain security exploits (e.g. writing to text) -config ARCH_WANT_RELAX_ORDER - bool - config REFCOUNT_FULL bool "Perform full reference count validation at the expense of speed" help diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index a4a6261..987a575 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -44,7 +44,6 @@ config SPARC select ARCH_HAS_SG_CHAIN select CPU_NO_EFFICIENT_FFS select LOCKDEP_SMALL if LOCKDEP - select ARCH_WANT_RELAX_ORDER config SPARC32 def_bool !64BIT diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c index 4e35e70..d4933d2 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c @@ -350,7 +350,7 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) } IXGBE_WRITE_FLUSH(hw); -#ifndef CONFIG_ARCH_WANT_RELAX_ORDER +#ifndef CONFIG_SPARC /* Disable relaxed ordering */ for (i = 0; i < hw->mac.max_tx_queues; i++) { u32 regval; From patchwork Thu Aug 17 03:25:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 110292 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1621869qge; Wed, 16 Aug 2017 20:25:45 -0700 (PDT) X-Received: by 10.99.100.134 with SMTP id y128mr3569023pgb.365.1502940345873; Wed, 16 Aug 2017 20:25:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502940345; cv=none; d=google.com; s=arc-20160816; b=tG1uCDD3TqkYAj4BT/KOwffAePzRr9edy9/T/vj1aGoqqGpvGJoMWx6ZTRSCnnc0it k+xwMvxIyfIEp4GALziJKe731C0W+P8zfDcirvuYl+hhqWHxn+nJU61anjcXEpyoMXF9 rzbb08kmvZpjKKDG+rmyA8azyTEm0c/oY4T0y+ju+TWKeqT8dsUKvZMKsV6+0QB8gv5c Ti4MtUKRnsdKg8Ewl6EMXvO3VUqtwzdQPqx/SAIGOKQ/2qke0U7h55dEABj0nZWcEtsW u4BE+pF1ahfDEUxqOq5hgoTRY96JpxfpN7vIeWWCbqEmjK7IYm4j6gUYUJwdkJp7wwfA avoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=Bh57R29Vfe48ZZoqbl/i7WVjRmr7EB2tWIvNu3KO17g=; b=oUkQdA+BCbkABFpY1WvwQOIqWITMSdaG19kJNMIYdwwdARwvQzI0tpR0+DrwSjmDBd 3nd/obGVu6gDU+evV+SNsnWuE+SBFusTqDJnamFxpaZwt7mGbIJy5Vzt318/UsI8NKw0 qP1pzYLkX1nwN90JKuq1UjV6+OXa0mluzgMprnYHqoEICl/UsUG/60cCHyxSTdlHHamr dqBem+FrlzQ5vyyvGLYycr31EGHr0y5JNrmh/L6zK0ITx1j3BvT/QmHULqh2j/udSs2h /k1Mzql9rkMCzpY47n95yTswyTVV/BiL4dGw+bFNldJQed5xQvajlvXKWMQC0gGqfTUC QucA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 78si1373382pgb.117.2017.08.16.20.25.45; Wed, 16 Aug 2017 20:25:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752309AbdHQDZm (ORCPT + 26 others); Wed, 16 Aug 2017 23:25:42 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:3578 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751578AbdHQDZi (ORCPT ); Wed, 16 Aug 2017 23:25:38 -0400 Received: from 172.30.72.59 (EHLO DGGEMS412-HUB.china.huawei.com) ([172.30.72.59]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFK21757; Thu, 17 Aug 2017 11:25:30 +0800 (CST) Received: from localhost (10.177.23.32) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.301.0; Thu, 17 Aug 2017 11:25:21 +0800 From: Ding Tianhong To: , , , , , , , , CC: Ding Tianhong Subject: [PATCH net v2 2/2] net: ixgbe: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Date: Thu, 17 Aug 2017 11:25:16 +0800 Message-ID: <1502940316-13384-3-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1502940316-13384-1-git-send-email-dingtianhong@huawei.com> References: <1502940316-13384-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.59950CAA.0111, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 4359600221f6405cd4801a103428c3d8 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ixgbe driver use the compile check to determine if it can send TLPs to Root Port with the Relaxed Ordering Attribute set, this is too inconvenient, now the new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING has been added to the kernel and we could check the bit4 in the PCIe Device Control register to determine whether we should use the Relaxed Ordering Attributes or not, so use this new way in the ixgbe driver. Signed-off-by: Ding Tianhong --- drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c | 37 ++++++++++++------------- drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 32 +++++++++++---------- 2 files changed, 35 insertions(+), 34 deletions(-) -- 1.8.3.1 diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c index 523f9d0..d1571e3 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c @@ -175,31 +175,30 @@ static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) **/ static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) { -#ifndef CONFIG_SPARC - u32 regval; - u32 i; -#endif + u32 regval, i; s32 ret_val; + struct ixgbe_adapter *adapter = hw->back; ret_val = ixgbe_start_hw_generic(hw); -#ifndef CONFIG_SPARC - /* Disable relaxed ordering */ - for (i = 0; ((i < hw->mac.max_tx_queues) && - (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { - regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); - regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; - IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); - } + if (!pcie_relaxed_ordering_enabled(adapter->pdev)) { + /* Disable relaxed ordering */ + for (i = 0; ((i < hw->mac.max_tx_queues) && + (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { + regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); + regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; + IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); + } - for (i = 0; ((i < hw->mac.max_rx_queues) && - (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { - regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); - regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | - IXGBE_DCA_RXCTRL_HEAD_WRO_EN); - IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); + for (i = 0; ((i < hw->mac.max_rx_queues) && + (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { + regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); + regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | + IXGBE_DCA_RXCTRL_HEAD_WRO_EN); + IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); + } } -#endif + if (ret_val) return ret_val; diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c index d4933d2..d1052ee 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c @@ -342,6 +342,7 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) { u32 i; + struct ixgbe_adapter *adapter = hw->back; /* Clear the rate limiters */ for (i = 0; i < hw->mac.max_tx_queues; i++) { @@ -350,25 +351,26 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) } IXGBE_WRITE_FLUSH(hw); -#ifndef CONFIG_SPARC - /* Disable relaxed ordering */ - for (i = 0; i < hw->mac.max_tx_queues; i++) { - u32 regval; + if (!pcie_relaxed_ordering_enabled(adapter->pdev)) { + /* Disable relaxed ordering */ + for (i = 0; i < hw->mac.max_tx_queues; i++) { + u32 regval; - regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); - regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; - IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); - } + regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); + regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; + IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); + } - for (i = 0; i < hw->mac.max_rx_queues; i++) { - u32 regval; + for (i = 0; i < hw->mac.max_rx_queues; i++) { + u32 regval; - regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); - regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | - IXGBE_DCA_RXCTRL_HEAD_WRO_EN); - IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); + regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); + regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | + IXGBE_DCA_RXCTRL_HEAD_WRO_EN); + IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); + } } -#endif + return 0; }