From patchwork Wed Aug 16 09:41:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 110216 Delivered-To: patch@linaro.org Received: by 10.182.109.195 with SMTP id hu3csp612619obb; Wed, 16 Aug 2017 02:44:31 -0700 (PDT) X-Received: by 10.98.61.13 with SMTP id k13mr1074017pfa.75.1502876671693; Wed, 16 Aug 2017 02:44:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502876671; cv=none; d=google.com; s=arc-20160816; b=EJM6YjJkd3hRsSnShlhPdZZMeooRLh08C6zvlU9q3DbL7Fhn0xuFKW33V9RiUPwfVG AVrpbHHK98Jn4jp3duzkoq/51p5fc6Qcgg/jyCaFCjGsPNFkcfbOG17eKpIKhJEETEql c/4u8YfGLumQNKjnyetrkg/w6r9pE+OrlQEHbrCfsH+sivojysjF4aaggK6Mz1GX/7jM FfPND/gqTKcpO+z5H1+akeGosyyCnPkk94c3ZLUc0e6ka8ekIw7hRszfd28Js0n4rmJ8 MhIyowGIalr9n9fO4+svEuKEgvWSjPjSe+K336iK6CWQ5VGLV6fxYEXZ1JO7ZYpVg353 boeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=i+RRu7YjSlMRtqzOYrbT38esgLWwPdi474cVUCEVmNs=; b=jhKhlCuo0XRIR09+fyLmmau49xL6iA+24rdNsCJQKSSeLSspK93yQdmXOp8nWMYTyc 37w/pKsCzO9rbzMLM0GsnGDa2uLA7NONem4Pocnw8aJKWWYgTwK5Ie2woUeqe4auJeqc 3hOXVZRHn9uQmGEiuH+syVY5D56J9Pc/gK+SyJ/HmhEJPWY2YdIy9Mzrv/nJN5nswT5V GsAMVupTSMGuqu+gG/7pJ+GBZbTUCCgbG2bhOiY5YikWsPiwPWqw7dJj2iW/Y8vx7oAQ NXrqYQURjtF+sSqX1pP7zz9vDX5cHpZzR0Rj/EaQd/3Ry9CsteYGg1p7EcLQBMd/s1mT P9xA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q2si301871plh.584.2017.08.16.02.44.31; Wed, 16 Aug 2017 02:44:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752246AbdHPJo1 (ORCPT + 26 others); Wed, 16 Aug 2017 05:44:27 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:3986 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751530AbdHPJoY (ORCPT ); Wed, 16 Aug 2017 05:44:24 -0400 Received: from 172.30.72.60 (EHLO DGGEMS404-HUB.china.huawei.com) ([172.30.72.60]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFG50637; Wed, 16 Aug 2017 17:44:17 +0800 (CST) Received: from localhost (10.177.23.32) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.301.0; Wed, 16 Aug 2017 17:44:11 +0800 From: Ding Tianhong To: , , , , , , , CC: Ding Tianhong Subject: [PATCH net 1/2] Revert commit 1a8b6d76dc5b ("net:add one common config...") Date: Wed, 16 Aug 2017 17:41:46 +0800 Message-ID: <1502876507-9360-2-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1502876507-9360-1-git-send-email-dingtianhong@huawei.com> References: <1502876507-9360-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.599413F1.0102, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: e295e9d6280a0d34da6de634ed072264 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING has been added to indicate that Relaxed Ordering Attributes (RO) should not be used for Transaction Layer Packets (TLP) targeted toward these affected Root Port, it will clear the bit4 in the PCIe Device Control register, so the PCIe device drivers could query PCIe configuration space to determine if it can send TLPs to Root Port with the Relaxed Ordering Attributes set. With this new flag we don't need the config ARCH_WANT_RELAX_ORDER to control the Relaxed Ordering Attributes for the ixgbe drivers just like the commit 1a8b6d76dc5b ("net:add one common config...") did, so revert this commit. Signed-off-by: Ding Tianhong --- arch/Kconfig | 3 --- arch/sparc/Kconfig | 1 - drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 2 +- 3 files changed, 1 insertion(+), 5 deletions(-) -- 1.8.3.1 diff --git a/arch/Kconfig b/arch/Kconfig index 21d0089..00cfc63 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -928,9 +928,6 @@ config STRICT_MODULE_RWX and non-text memory will be made non-executable. This provides protection against certain security exploits (e.g. writing to text) -config ARCH_WANT_RELAX_ORDER - bool - config REFCOUNT_FULL bool "Perform full reference count validation at the expense of speed" help diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index a4a6261..987a575 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -44,7 +44,6 @@ config SPARC select ARCH_HAS_SG_CHAIN select CPU_NO_EFFICIENT_FFS select LOCKDEP_SMALL if LOCKDEP - select ARCH_WANT_RELAX_ORDER config SPARC32 def_bool !64BIT diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c index 4e35e70..d4933d2 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c @@ -350,7 +350,7 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) } IXGBE_WRITE_FLUSH(hw); -#ifndef CONFIG_ARCH_WANT_RELAX_ORDER +#ifndef CONFIG_SPARC /* Disable relaxed ordering */ for (i = 0; i < hw->mac.max_tx_queues; i++) { u32 regval; From patchwork Wed Aug 16 09:41:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 110217 Delivered-To: patch@linaro.org Received: by 10.182.109.195 with SMTP id hu3csp612642obb; Wed, 16 Aug 2017 02:44:33 -0700 (PDT) X-Received: by 10.98.152.155 with SMTP id d27mr1036769pfk.245.1502876673190; Wed, 16 Aug 2017 02:44:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502876673; cv=none; d=google.com; s=arc-20160816; b=sczBZdswMIXt74T5/YxFjgIIVYAWcAnniNdX2MOOn8F+8NrVu4OJ2Q0O3tflrshoEI nL3A8+m9dqSP6h2s++Frt77ZG2zriK+7eAG4sU5+RlPrkEl4JR36GuD8pgX78RzRuj/B tTkhtEXAynbZ3bqt99evR/jXOUcXD/a+jvulq6VDWsDJttDgCXzcFqshIyR/lb2UjyZx qpcNXw/LUuidvsV9vZwl9RITPBtSuSJO2giFEEg6s1oySrE8olPkXbq/w5mtOCFqtp7d mfbeuPq+B3dJhoITHfffdiCnr3xnx/ZqgIC3zwxe8Zz0E3Ti+2k7QHUIghRsUY3WgR8/ WYgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=11wwjIG+IRE/qtVPXiy0PiZfzv7ThU+G0fPjQv4oA9c=; b=aTu1qiNeOu1T0X2m9akK00HZ3QGt5AwcBsZMCYe0qvJTewtc/s8y82VNN3cmcLaMr4 bxw5UddihYQqB1vwEN7/ME6WSo9RdnlHgyAzGu1u2i90ioHfI61IEQPkJNxXzE2CBW54 ZVBoEFRbP/U6xi2HvSDYoQ6nVFDJ6jJgHW/W030sHUvwEgfrNNDoinz1ujAl3G1rK/pt aInwAVJUzVU+/0h/oVgQucPxMq81IsyV+CnWh4g5sf7DGn8dNXOUBL8BdQSwCbndyZI4 bSU/HSXsW26pxReoDeH68LdH7pktIOLjDLV+IjRfMQU2mkFIHQFHpupxO2aJFsZ04ejK uYBQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x66si285256pfb.38.2017.08.16.02.44.32; Wed, 16 Aug 2017 02:44:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752297AbdHPJoa (ORCPT + 26 others); Wed, 16 Aug 2017 05:44:30 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:3987 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751542AbdHPJo1 (ORCPT ); Wed, 16 Aug 2017 05:44:27 -0400 Received: from 172.30.72.58 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFG50646; Wed, 16 Aug 2017 17:44:21 +0800 (CST) Received: from localhost (10.177.23.32) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.301.0; Wed, 16 Aug 2017 17:44:14 +0800 From: Ding Tianhong To: , , , , , , , CC: Ding Tianhong Subject: [PATCH net 2/2] net: ixgbe: Use new IXGBE_FLAG2_ROOT_NO_RELAXED_ORDERING flag Date: Wed, 16 Aug 2017 17:41:47 +0800 Message-ID: <1502876507-9360-3-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1502876507-9360-1-git-send-email-dingtianhong@huawei.com> References: <1502876507-9360-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.599413F5.00E2, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 55aea1ccfda985d52dfeb37fc65fca0d Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ixgbe driver use the compile check to determine if it can send TLPs to Root Port with the Relaxed Ordering Attribute set, this is too inconvenient, now the new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING has been added to the kernel and we could check the bit4 in the PCIe Davice Control register to determine whether we should use the Relaxed Ordering Attributes or not, so we add a new flag which called IXGBE_FLAG2_ROOT_NO_RELAXED_ORDERING to the ixgbe driver, it will be set if the Root Port couldn't deal the upstream TLPs with Relaxed Ordering Attribute, then the driver could know what to do next. Signed-off-by: Ding Tianhong --- drivers/net/ethernet/intel/ixgbe/ixgbe.h | 1 + drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c | 37 ++++++++++++------------- drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 32 +++++++++++---------- drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 17 ++++++++++++ 4 files changed, 53 insertions(+), 34 deletions(-) -- 1.8.3.1 diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe.h b/drivers/net/ethernet/intel/ixgbe/ixgbe.h index dd55787..50e0553 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe.h +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe.h @@ -621,6 +621,7 @@ struct ixgbe_adapter { #define IXGBE_FLAG2_EEE_CAPABLE BIT(14) #define IXGBE_FLAG2_EEE_ENABLED BIT(15) #define IXGBE_FLAG2_RX_LEGACY BIT(16) +#define IXGBE_FLAG2_ROOT_NO_RELAXED_ORDERING BIT(17) /* Tx fast path data */ int num_tx_queues; diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c index 523f9d0..0727a30 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c @@ -175,31 +175,30 @@ static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) **/ static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) { -#ifndef CONFIG_SPARC - u32 regval; - u32 i; -#endif + u32 regval, i; s32 ret_val; + struct ixgbe_adapter *adapter = hw->back; ret_val = ixgbe_start_hw_generic(hw); -#ifndef CONFIG_SPARC - /* Disable relaxed ordering */ - for (i = 0; ((i < hw->mac.max_tx_queues) && - (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { - regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); - regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; - IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); - } + if (adapter->flags2 & IXGBE_FLAG2_ROOT_NO_RELAXED_ORDERING) { + /* Disable relaxed ordering */ + for (i = 0; ((i < hw->mac.max_tx_queues) && + (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { + regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); + regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; + IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); + } - for (i = 0; ((i < hw->mac.max_rx_queues) && - (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { - regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); - regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | - IXGBE_DCA_RXCTRL_HEAD_WRO_EN); - IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); + for (i = 0; ((i < hw->mac.max_rx_queues) && + (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { + regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); + regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | + IXGBE_DCA_RXCTRL_HEAD_WRO_EN); + IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); + } } -#endif + if (ret_val) return ret_val; diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c index d4933d2..2473c0b 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c @@ -342,6 +342,7 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) { u32 i; + struct ixgbe_adapter *adapter = hw->back; /* Clear the rate limiters */ for (i = 0; i < hw->mac.max_tx_queues; i++) { @@ -350,25 +351,26 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) } IXGBE_WRITE_FLUSH(hw); -#ifndef CONFIG_SPARC - /* Disable relaxed ordering */ - for (i = 0; i < hw->mac.max_tx_queues; i++) { - u32 regval; + if (adapter->flags2 & IXGBE_FLAG2_ROOT_NO_RELAXED_ORDERING) { + /* Disable relaxed ordering */ + for (i = 0; i < hw->mac.max_tx_queues; i++) { + u32 regval; - regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); - regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; - IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); - } + regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); + regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; + IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); + } - for (i = 0; i < hw->mac.max_rx_queues; i++) { - u32 regval; + for (i = 0; i < hw->mac.max_rx_queues; i++) { + u32 regval; - regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); - regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | - IXGBE_DCA_RXCTRL_HEAD_WRO_EN); - IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); + regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); + regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | + IXGBE_DCA_RXCTRL_HEAD_WRO_EN); + IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); + } } -#endif + return 0; } diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c index f1dbdf2..f576be7 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c @@ -10081,6 +10081,23 @@ static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) goto err_ioremap; } + /* If possible, we use PCIe Relaxed Ordering Attribute to deliver + * Ingress Packet Data to Free List Buffers in order to allow for + * chipset performance optimizations between the Root Complex and + * Memory Controllers. (Messages to the associated Ingress Queue + * notifying new Packet Placement in the Free Lists Buffers will be + * send without the Relaxed Ordering Attribute thus guaranteeing that + * all preceding PCIe Transaction Layer Packets will be processed + * first.) But some Root Complexes have various issues with Upstream + * Transaction Layer Packets with the Relaxed Ordering Attribute set. + * The PCIe devices which under the Root Complexes will be cleared the + * Relaxed Ordering bit in the configuration space, So we check our + * PCIe configuration space to see if it's flagged with advice against + * using Relaxed Ordering. + */ + if (!pcie_relaxed_ordering_enabled(pdev)) + adapter->flags2 |= IXGBE_FLAG2_ROOT_NO_RELAXED_ORDERING; + netdev->netdev_ops = &ixgbe_netdev_ops; ixgbe_set_ethtool_ops(netdev); netdev->watchdog_timeo = 5 * HZ;