From patchwork Mon Apr 27 23:56:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bi1IdW5nIFd1ICjlt6vpp7/lro8p?= X-Patchwork-Id: 201426 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57AB3C83004 for ; Mon, 27 Apr 2020 23:57:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 33CDF20775 for ; Mon, 27 Apr 2020 23:57:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="HzTCrtEY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726520AbgD0X5X (ORCPT ); Mon, 27 Apr 2020 19:57:23 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:7418 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726472AbgD0X5W (ORCPT ); Mon, 27 Apr 2020 19:57:22 -0400 X-UUID: 1596a3af7b894470a7fc18519ca4281e-20200428 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=KIB6Wc6OlR9OdFAkZ9URtiP7nJvudaOVXuS/SxVSoHI=; b=HzTCrtEY7w6Mok7Rc1XGpr/fP31B0pG7BUs7dT8C+j1WH++jGa0LghhBAd0TKByhzz+7WGxnFgqCZzd8Om3RCX1QivdDFEWZKjvqCiuNWGWOk6sQdj3mmgOSeu8fsQqbMlspzfZghkaHoSS/dJaGDn4mn3smUPnZyC4ko9hp2Bk=; X-UUID: 1596a3af7b894470a7fc18519ca4281e-20200428 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 122815350; Tue, 28 Apr 2020 07:57:14 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 28 Apr 2020 07:57:08 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 28 Apr 2020 07:57:12 +0800 From: Chun-Hung Wu To: , Jonathan Hunter , Al Cooper , Adrian Hunter , Florian Fainelli , , Andy Gross , Bjorn Andersson , Michal Simek , Thierry Reding , Chaotian Jing , Ulf Hansson , Rob Herring , Mark Rutland , Matthias Brugger , Linus Walleij , Pavel Machek , Kate Stewart , Greg Kroah-Hartman , Martin Blumenstingl , Pan Bian , Thomas Gleixner , Allison Randal , Mathieu Malaterre , Stanley Chu , Kuohong Wang , Yong Mao CC: , , , , , , , , , Chun-Hung Wu Subject: [PATCH v5 1/5] mmc: core: Extend mmc_of_parse() to parse CQE bindings Date: Tue, 28 Apr 2020 07:56:04 +0800 Message-ID: <1588031768-23677-2-git-send-email-chun-hung.wu@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1588031768-23677-1-git-send-email-chun-hung.wu@mediatek.com> References: <1588031768-23677-1-git-send-email-chun-hung.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Parse CQE bindings "supports-cqe" and "disable-cqe-dcmd" in mmc_of_parse(). Signed-off-by: Chun-Hung Wu --- drivers/mmc/core/host.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.6.4 diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index c876872..47521c6 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -302,6 +302,11 @@ int mmc_of_parse(struct mmc_host *host) host->caps2 |= MMC_CAP2_NO_SD; if (device_property_read_bool(dev, "no-mmc")) host->caps2 |= MMC_CAP2_NO_MMC; + if (device_property_read_bool(dev, "supports-cqe")) + host->caps2 |= MMC_CAP2_CQE; + if (!device_property_read_bool(dev, "disable-cqe-dcmd")) { + host->caps2 |= MMC_CAP2_CQE_DCMD; + } /* Must be after "non-removable" check */ if (device_property_read_u32(dev, "fixed-emmc-driver-type", &drv_type) == 0) { From patchwork Mon Apr 27 23:56:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bi1IdW5nIFd1ICjlt6vpp7/lro8p?= X-Patchwork-Id: 201425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0090DC83007 for ; Mon, 27 Apr 2020 23:57:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CAA1C20775 for ; Mon, 27 Apr 2020 23:57:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="BProQaA5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726512AbgD0X5X (ORCPT ); Mon, 27 Apr 2020 19:57:23 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:16479 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726470AbgD0X5T (ORCPT ); Mon, 27 Apr 2020 19:57:19 -0400 X-UUID: 072fa0113eb34f04bdaa0a04aa8a9613-20200428 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=+sx88la9jukwwPydWrvJ7BtN1WCn5H7eGpl+1G7y/Z8=; b=BProQaA5YxpS9zb2gHI6qt5AEiojAjAcS8fvHYKRflGm1ef/v7+mufUppMhKC9EW2rQWj/s568CeUbGDnWrqcLzsIRROuM/k2R8I1Z8RhSl0q7iBD+LraaMFqlhyD5JHx+kXNdIJaJ+uy+T017RGSrD7KCRAhkgp1ayS80EwMxA=; X-UUID: 072fa0113eb34f04bdaa0a04aa8a9613-20200428 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 769041113; Tue, 28 Apr 2020 07:57:14 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 28 Apr 2020 07:57:08 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 28 Apr 2020 07:57:12 +0800 From: Chun-Hung Wu To: , Jonathan Hunter , Al Cooper , Adrian Hunter , Florian Fainelli , , Andy Gross , Bjorn Andersson , Michal Simek , Thierry Reding , Chaotian Jing , Ulf Hansson , Rob Herring , Mark Rutland , Matthias Brugger , Linus Walleij , Pavel Machek , Kate Stewart , Greg Kroah-Hartman , Martin Blumenstingl , Pan Bian , Thomas Gleixner , Allison Randal , Mathieu Malaterre , Stanley Chu , Kuohong Wang , Yong Mao CC: , , , , , , , , , Chun-Hung Wu Subject: [PATCH v5 2/5] mmc: host: Remove redundant CQE bindings Date: Tue, 28 Apr 2020 07:56:05 +0800 Message-ID: <1588031768-23677-3-git-send-email-chun-hung.wu@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1588031768-23677-1-git-send-email-chun-hung.wu@mediatek.com> References: <1588031768-23677-1-git-send-email-chun-hung.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org CQE bindings "supports-cqe" and "disable-cqe-dcmd" is parsed in mmc_of_parse(). Remove vendor code which parses CQE bindings, and use mmc_host->caps2 to decide support CQE or not. Signed-off-by: Chun-Hung Wu Acked-by: Al Cooper --- drivers/mmc/host/sdhci-brcmstb.c | 11 ++++++----- drivers/mmc/host/sdhci-msm.c | 3 +-- drivers/mmc/host/sdhci-of-arasan.c | 3 --- drivers/mmc/host/sdhci-tegra.c | 2 +- 4 files changed, 8 insertions(+), 11 deletions(-) -- 2.6.4 diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index ad01f64..07c90c6 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -247,10 +247,6 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) return res; memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata)); - if (device_property_read_bool(&pdev->dev, "supports-cqe")) { - has_cqe = true; - match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; - } brcmstb_pdata.ops = match_priv->ops; host = sdhci_pltfm_init(pdev, &brcmstb_pdata, sizeof(struct sdhci_brcmstb_priv)); @@ -261,7 +257,6 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) pltfm_host = sdhci_priv(host); priv = sdhci_pltfm_priv(pltfm_host); - priv->has_cqe = has_cqe; /* Map in the non-standard CFG registers */ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1); @@ -276,6 +271,12 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) if (res) goto err; + if (host->mmc->caps2 & MMC_CAP2_CQE) { + has_cqe = true; + match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; + } + priv->has_cqe = has_cqe; + /* * If the chip has enhanced strobe and it's enabled, add * callback diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index c3a160c..fbb2f57 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1880,7 +1880,6 @@ static int sdhci_msm_probe(struct platform_device *pdev) u8 core_major; const struct sdhci_msm_offset *msm_offset; const struct sdhci_msm_variant_info *var_info; - struct device_node *node = pdev->dev.of_node; host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host)); if (IS_ERR(host)) @@ -2076,7 +2075,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) pm_runtime_use_autosuspend(&pdev->dev); host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning; - if (of_property_read_bool(node, "supports-cqe")) + if (host->mmc->caps2 & MMC_CAP2_CQE) ret = sdhci_msm_cqe_add_host(host, pdev); else ret = sdhci_add_host(host); diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index e49b44b..359eff6 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -1281,9 +1281,6 @@ static int sdhci_arasan_probe(struct platform_device *pdev) sdhci_arasan_voltage_switch; sdhci_arasan->has_cqe = true; host->mmc->caps2 |= MMC_CAP2_CQE; - - if (!of_property_read_bool(np, "disable-cqe-dcmd")) - host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; } ret = sdhci_arasan_add_host(sdhci_arasan); diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 403ac44..d09abdd 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -715,7 +715,7 @@ static void tegra_sdhci_parse_dt(struct sdhci_host *host) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); - if (device_property_read_bool(host->mmc->parent, "supports-cqe")) + if (host->mmc->caps2 & MMC_CAP2_CQE) tegra_host->enable_hwcq = true; else tegra_host->enable_hwcq = false; From patchwork Mon Apr 27 23:56:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bi1IdW5nIFd1ICjlt6vpp7/lro8p?= X-Patchwork-Id: 201427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93855C83002 for ; Mon, 27 Apr 2020 23:57:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 65EBA208FE for ; Mon, 27 Apr 2020 23:57:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="mgUtCl3B" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726539AbgD0X5Z (ORCPT ); Mon, 27 Apr 2020 19:57:25 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:64043 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726508AbgD0X5Y (ORCPT ); Mon, 27 Apr 2020 19:57:24 -0400 X-UUID: 178f777f09244bc28e223dc678b09c1f-20200428 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Ka1VpXu+0E+Smr9pkPy8HfDlYfiuvLYEfO8kgaZYtQM=; b=mgUtCl3BylwJRMmKRwok4zYhDEqkV1+Ink18Ev18ic75DJdJVo1sz3p9p9fGDf0mnCKfu6gTJUntIloujK2YkZKppgCg5qjpsxjN0lzc2wcjCbeYZW4Ja1+2gOHVLcianuAt/0YSLXI8eRxKC8xwiVvv9wI/CiceGG4cxkDifnc=; X-UUID: 178f777f09244bc28e223dc678b09c1f-20200428 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 36155996; Tue, 28 Apr 2020 07:57:15 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 28 Apr 2020 07:57:13 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 28 Apr 2020 07:57:13 +0800 From: Chun-Hung Wu To: , Jonathan Hunter , Al Cooper , Adrian Hunter , Florian Fainelli , , Andy Gross , Bjorn Andersson , Michal Simek , Thierry Reding , Chaotian Jing , Ulf Hansson , Rob Herring , Mark Rutland , Matthias Brugger , Linus Walleij , Pavel Machek , Kate Stewart , Greg Kroah-Hartman , Martin Blumenstingl , Pan Bian , Thomas Gleixner , Allison Randal , Mathieu Malaterre , Stanley Chu , Kuohong Wang , Yong Mao CC: , , , , , , , , , Chun-Hung Wu Subject: [PATCH v5 4/5] mmc: mediatek: command queue support Date: Tue, 28 Apr 2020 07:56:07 +0800 Message-ID: <1588031768-23677-5-git-send-email-chun-hung.wu@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1588031768-23677-1-git-send-email-chun-hung.wu@mediatek.com> References: <1588031768-23677-1-git-send-email-chun-hung.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Support command queue for mt6779 platform. a. Add msdc_set_busy_timeout() to calculate emmc write timeout b. Connect mtk msdc driver to cqhci driver through host->cq_host->ops = &msdc_cmdq_ops; c. msdc_cmdq_irq() will link up with cqchi_irq(). Besides, it provides more irq error messages like RSPCRCERR/CMDTO/DATACRCERR/DATTMO. d. Use the options below to separate support for CQHCI or not, because some of our platform does not support CQHCI hence no kernel option: CONFIG_MMC_CQHCI. #if IS_ENABLED(CONFIG_MMC_CQHCI) XXX //Support CQHCI #else XXX //Not support CQHCI #endif Signed-off-by: Chun-Hung Wu --- drivers/mmc/host/mtk-sd.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) -- 2.6.4 diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index a2328fb..8516888 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -31,6 +31,8 @@ #include #include +#include "cqhci.h" + #define MAX_BD_NUM 1024 /*--------------------------------------------------------------------------*/ @@ -151,6 +153,7 @@ #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ +#define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ /* MSDC_INTEN mask */ #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ @@ -181,6 +184,7 @@ /* SDC_CFG mask */ #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ +#define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ #define SDC_CFG_SDIO (0x1 << 19) /* RW */ #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ @@ -229,6 +233,7 @@ #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ +#define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ @@ -432,6 +437,7 @@ struct msdc_host { struct msdc_save_para save_para; /* used when gate HCLK */ struct msdc_tune_para def_tune_para; /* default tune setting */ struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ + struct cqhci_host *cq_host; }; static const struct mtk_mmc_compatible mt8135_compat = { @@ -528,6 +534,18 @@ static const struct mtk_mmc_compatible mt7620_compat = { .use_internal_cd = true, }; +static const struct mtk_mmc_compatible mt6779_compat = { + .clk_div_bits = 12, + .hs400_tune = false, + .pad_tune_reg = MSDC_PAD_TUNE0, + .async_fifo = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, + .enhance_rx = true, + .support_64g = true, +}; + static const struct of_device_id msdc_of_ids[] = { { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, @@ -537,6 +555,7 @@ static const struct of_device_id msdc_of_ids[] = { { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, + { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, {} }; MODULE_DEVICE_TABLE(of, msdc_of_ids); @@ -740,6 +759,15 @@ static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) (u32)(timeout > 255 ? 255 : timeout)); } +static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) +{ + u64 timeout; + + timeout = msdc_timeout_cal(host, ns, clks); + sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, + (u32)(timeout > 8191 ? 8191 : timeout)); +} + static void msdc_gate_clock(struct msdc_host *host) { clk_disable_unprepare(host->src_clk_cg); @@ -1426,6 +1454,36 @@ static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) pm_runtime_put_noidle(host->dev); } +#if IS_ENABLED(CONFIG_MMC_CQHCI) +static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) +{ + int cmd_err = 0, dat_err = 0; + + if (intsts & MSDC_INT_RSPCRCERR) { + cmd_err = (unsigned int)-EILSEQ; + dev_err(host->dev, "%s: CMD CRC ERR", __func__); + } else if (intsts & MSDC_INT_CMDTMO) { + cmd_err = (unsigned int)-ETIMEDOUT; + dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); + } + + if (intsts & MSDC_INT_DATCRCERR) { + dat_err = (unsigned int)-EILSEQ; + dev_err(host->dev, "%s: DATA CRC ERR", __func__); + } else if (intsts & MSDC_INT_DATTMO) { + dat_err = (unsigned int)-ETIMEDOUT; + dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); + } + + if (cmd_err || dat_err) { + dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", + cmd_err, dat_err, intsts); + } + + return cqhci_irq(host->mmc, 0, cmd_err, dat_err); +} +#endif + static irqreturn_t msdc_irq(int irq, void *dev_id) { struct msdc_host *host = (struct msdc_host *) dev_id; @@ -1462,6 +1520,16 @@ static irqreturn_t msdc_irq(int irq, void *dev_id) if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) break; +#if IS_ENABLED(CONFIG_MMC_CQHCI) + if ((host->mmc->caps2 & MMC_CAP2_CQE) && + (events & MSDC_INT_CMDQ)) { + msdc_cmdq_irq(host, events); + /* clear interrupts */ + writel(events, host->base + MSDC_INT); + return IRQ_HANDLED; + } +#endif + if (!mrq) { dev_err(host->dev, "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", @@ -2146,6 +2214,36 @@ static int msdc_get_cd(struct mmc_host *mmc) return !val; } +static void msdc_cqe_enable(struct mmc_host *mmc) +{ + struct msdc_host *host = mmc_priv(mmc); + + /* enable cmdq irq */ + writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); + /* enable busy check */ + sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); + /* default write data / busy timeout 20s */ + msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); + /* default read data timeout 1s */ + msdc_set_timeout(host, 1000000000ULL, 0); +} + +void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) +{ + struct msdc_host *host = mmc_priv(mmc); + + /* disable cmdq irq */ + sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); + /* disable busy check */ + sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); + + if (recovery) { + sdr_set_field(host->base + MSDC_DMA_CTRL, + MSDC_DMA_CTRL_STOP, 1); + msdc_reset_hw(host); + } +} + static const struct mmc_host_ops mt_msdc_ops = { .post_req = msdc_post_req, .pre_req = msdc_pre_req, @@ -2162,6 +2260,11 @@ static const struct mmc_host_ops mt_msdc_ops = { .hw_reset = msdc_hw_reset, }; +static const struct cqhci_host_ops msdc_cmdq_ops = { + .enable = msdc_cqe_enable, + .disable = msdc_cqe_disable, +}; + static void msdc_of_property_parse(struct platform_device *pdev, struct msdc_host *host) { @@ -2312,6 +2415,22 @@ static int msdc_drv_probe(struct platform_device *pdev) host->dma_mask = DMA_BIT_MASK(32); mmc_dev(mmc)->dma_mask = &host->dma_mask; +#if IS_ENABLED(CONFIG_MMC_CQHCI) + if (mmc->caps2 & MMC_CAP2_CQE) { + host->cq_host = devm_kzalloc(host->mmc->parent, + sizeof(*host->cq_host), + GFP_KERNEL); + host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; + host->cq_host->mmio = host->base + 0x800; + host->cq_host->ops = &msdc_cmdq_ops; + cqhci_init(host->cq_host, mmc, true); + mmc->max_segs = 128; + /* cqhci 16bit length */ + /* 0 size, means 65536 so we don't have to -1 here */ + mmc->max_seg_size = 64 * 1024; + } +#endif + host->timeout_clks = 3 * 1048576; host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2 * sizeof(struct mt_gpdma_desc),