From patchwork Wed Apr 29 20:46:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 201354 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIM_ADSP_ALL, DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3976C8300A for ; Wed, 29 Apr 2020 20:46:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CD82C20BED for ; Wed, 29 Apr 2020 20:46:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="muALmyfm" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727071AbgD2Uq1 (ORCPT ); Wed, 29 Apr 2020 16:46:27 -0400 Received: from plaes.org ([188.166.43.21]:34982 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727049AbgD2Uq0 (ORCPT ); Wed, 29 Apr 2020 16:46:26 -0400 Received: from localhost (unknown [IPv6:2001:1530:1000:d397:940e:6b9e:3deb:3]) by plaes.org (Postfix) with ESMTPSA id C509740A4A; Wed, 29 Apr 2020 20:46:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1588193184; bh=vozgkxdGukZkw97VZxaA46SLq3vMd9Wmn6ITkjlRwzM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=muALmyfmKI5x02+uA4+LCgaYszU/T90rPKS7f7FgI4pIQlHoNk7s5FwLpp4xM67Na jJEHh26IsedVkgQUJCl97efrVgZ7RVu5bpO70jDVACHPg+LAJ479am0pxeSV98vGgC sY5Fi02A24DqBoH0mNLyVQ+06ZQfGIh3smIr/IXVQbbHCW8FFMG330IPYs3oyHmVNk iuU5yBW+CUIDi3KRTWXBZSyPey/ZW47CGomzkHtWQIlz4eNpwmVqAA258nRSZuGi6f gUa1Zs62dB4pSgSl8i7j57zVL/suFmKeNOgNohkF1Hefkld6NjUk8fmEJQj0JJGxd0 +t8DGmoFk2jgQ== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH v2 3/6] net: stmmac: dwmac-sunxi: Implement syscon-based clock handling Date: Wed, 29 Apr 2020 23:46:09 +0300 Message-Id: <20200429204612.31883-4-plaes@plaes.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429204612.31883-1-plaes@plaes.org> References: <20200429204612.31883-1-plaes@plaes.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the sun7i-gmac driver to use a regmap-based driver, instead of relying on the custom clock implementation. This allows to get rid of the last custom clock in the sun7i device tree making the sun7i fully CCU-compatible. Compatibility with existing devicetrees is retained. Signed-off-by: Priit Laes --- .../net/ethernet/stmicro/stmmac/dwmac-sunxi.c | 130 ++++++++++++++++-- 1 file changed, 122 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c index 0e1ca2cba3c7..206398f7a2af 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c @@ -12,8 +12,11 @@ #include #include #include +#include #include #include +#include +#include #include "stmmac_platform.h" @@ -22,11 +25,23 @@ struct sunxi_priv_data { int clk_enabled; struct clk *tx_clk; struct regulator *regulator; + struct regmap_field *regmap_field; +}; + +/* EMAC clock register @ 0x164 in the CCU address range */ +static const struct reg_field ccu_reg_field = { + .reg = 0x164, + .lsb = 0, + .msb = 31, }; #define SUN7I_GMAC_GMII_RGMII_RATE 125000000 #define SUN7I_GMAC_MII_RATE 25000000 +#define SUN7I_A20_CLK_MASK GENMASK(2, 0) +#define SUN7I_A20_RGMII_CLK (BIT(2) | BIT(1)) +#define SUN7I_A20_MII_CLK 0 + static int sun7i_gmac_init(struct platform_device *pdev, void *priv) { struct sunxi_priv_data *gmac = priv; @@ -38,7 +53,20 @@ static int sun7i_gmac_init(struct platform_device *pdev, void *priv) return ret; } - /* Set GMAC interface port mode + if (gmac->regmap_field) { + if (phy_interface_mode_is_rgmii(gmac->interface)) { + regmap_field_update_bits(gmac->regmap_field, + SUN7I_A20_CLK_MASK, + SUN7I_A20_RGMII_CLK); + return clk_prepare_enable(gmac->tx_clk); + } + regmap_field_update_bits(gmac->regmap_field, + SUN7I_A20_CLK_MASK, + SUN7I_A20_MII_CLK); + return clk_enable(gmac->tx_clk); + } + + /* Legacy devicetree clock (allwinner,sun7i-a20-gmac-clk) support: * * The GMAC TX clock lines are configured by setting the clock * rate, which then uses the auto-reparenting feature of the @@ -62,9 +90,16 @@ static void sun7i_gmac_exit(struct platform_device *pdev, void *priv) { struct sunxi_priv_data *gmac = priv; - if (gmac->clk_enabled) { + if (gmac->regmap_field) { + regmap_field_update_bits(gmac->regmap_field, + SUN7I_A20_CLK_MASK, 0); clk_disable(gmac->tx_clk); - gmac->clk_enabled = 0; + } else { + /* Handle legacy devicetree clock (sun7i-a20-gmac-clk) */ + if (gmac->clk_enabled) { + clk_disable(gmac->tx_clk); + gmac->clk_enabled = 0; + } } clk_unprepare(gmac->tx_clk); @@ -72,10 +107,55 @@ static void sun7i_gmac_exit(struct platform_device *pdev, void *priv) regulator_disable(gmac->regulator); } +static struct regmap *sun7i_gmac_get_syscon_from_dev(struct device_node *node) +{ + struct device_node *syscon_node; + struct platform_device *syscon_pdev; + struct regmap *regmap = NULL; + + syscon_node = of_parse_phandle(node, "syscon", 0); + if (!syscon_node) + return ERR_PTR(-ENODEV); + + syscon_pdev = of_find_device_by_node(syscon_node); + if (!syscon_pdev) { + /* platform device might not be probed yet */ + regmap = ERR_PTR(-EPROBE_DEFER); + goto out_put_node; + } + + /* If no regmap is found then the other device driver is at fault */ + regmap = dev_get_regmap(&syscon_pdev->dev, NULL); + if (!regmap) + regmap = ERR_PTR(-EINVAL); + + platform_device_put(syscon_pdev); +out_put_node: + of_node_put(syscon_node); + return regmap; +} + static void sun7i_fix_speed(void *priv, unsigned int speed) { struct sunxi_priv_data *gmac = priv; + if (gmac->regmap_field) { + clk_disable(gmac->tx_clk); + clk_unprepare(gmac->tx_clk); + if (speed == 1000) + regmap_field_update_bits(gmac->regmap_field, + SUN7I_A20_CLK_MASK, + SUN7I_A20_RGMII_CLK); + else + regmap_field_update_bits(gmac->regmap_field, + SUN7I_A20_CLK_MASK, + SUN7I_A20_MII_CLK); + clk_prepare_enable(gmac->tx_clk); + return; + } + + /* Handle legacy devicetree clock (sun7i-a20-gmac-clk) */ + /* only GMII mode requires us to reconfigure the clock lines */ if (gmac->interface != PHY_INTERFACE_MODE_GMII) return; @@ -102,6 +182,8 @@ static int sun7i_gmac_probe(struct platform_device *pdev) struct stmmac_resources stmmac_res; struct sunxi_priv_data *gmac; struct device *dev = &pdev->dev; + struct device_node *syscon_node; + struct regmap *regmap = NULL; int ret; ret = stmmac_get_platform_resources(pdev, &stmmac_res); @@ -124,11 +206,43 @@ static int sun7i_gmac_probe(struct platform_device *pdev) goto err_remove_config_dt; } - gmac->tx_clk = devm_clk_get(dev, "allwinner_gmac_tx"); - if (IS_ERR(gmac->tx_clk)) { - dev_err(dev, "could not get tx clock\n"); - ret = PTR_ERR(gmac->tx_clk); - goto err_remove_config_dt; + /* Attempt to fetch syscon node... */ + syscon_node = of_parse_phandle(dev->of_node, "syscon", 0); + if (syscon_node) { + gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); + if (IS_ERR(gmac->tx_clk)) { + dev_err(dev, "Could not get TX clock\n"); + ret = PTR_ERR(gmac->tx_clk); + goto err_remove_config_dt; + } + + regmap = sun7i_gmac_get_syscon_from_dev(pdev->dev.of_node); + if (IS_ERR(regmap)) + regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "syscon"); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); + goto err_remove_config_dt; + } + + gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, + ccu_reg_field); + + if (IS_ERR(gmac->regmap_field)) { + ret = PTR_ERR(gmac->regmap_field); + dev_err(dev, "Unable to map syscon register: %d\n", ret); + goto err_remove_config_dt; + } + /* ...or fall back to legacy clock setup */ + } else { + gmac->tx_clk = devm_clk_get(dev, "allwinner_gmac_tx"); + if (IS_ERR(gmac->tx_clk)) { + dev_err(dev, "could not get tx clock\n"); + ret = PTR_ERR(gmac->tx_clk); + goto err_remove_config_dt; + } + dev_info(dev, "allwinner_gmac_tx support is deprecated!\n"); } /* Optional regulator for PHY */ From patchwork Wed Apr 29 20:46:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 201352 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIM_ADSP_ALL, DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75CF1C83004 for ; Wed, 29 Apr 2020 20:47:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4B8532137B for ; Wed, 29 Apr 2020 20:47:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="iXIpe3Y+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727894AbgD2UrD (ORCPT ); Wed, 29 Apr 2020 16:47:03 -0400 Received: from plaes.org ([188.166.43.21]:35034 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727874AbgD2UrC (ORCPT ); Wed, 29 Apr 2020 16:47:02 -0400 Received: from localhost (unknown [IPv6:2001:1530:1000:d397:940e:6b9e:3deb:3]) by plaes.org (Postfix) with ESMTPSA id 27C2F406D2; Wed, 29 Apr 2020 20:46:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1588193189; bh=hD8MO8nZG7cWOQMyvrg2gESOCiX1BXG9t5neHczu/iA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iXIpe3Y+PbIFsrKy3pI5oWGv70swaGWQqS0jNKqF7Fa+apASm3B0MrhusmrrJct93 apTgFtSE9y10wyorWdpzYyKvpYnoAoLHS9WsVhI85vFWnpdNgOY6X3m1BMjVnXWNvi o9575D9Z3tGZHvKXj4E9BCpabTbKzYDx3kxJieWWTIz+bw1eYx7+SFBxvcnxfwyRke OXvYI21clbu6d52frM234CHwkvxIq8JelPajlOQmVK8uCWFAbvK1X2ftMF/7VhUjmn qPy3JuXulTak3ZaFlnenKIVtgdGLHxoTW8F2s/59pxl+bzI1SOLS1ErlzZsOONWpzY ywl/yvEglystw== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH v2 6/6] ARM: dts: sun6i: Use syscon-based implementation for gmac Date: Wed, 29 Apr 2020 23:46:12 +0300 Message-Id: <20200429204612.31883-7-plaes@plaes.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429204612.31883-1-plaes@plaes.org> References: <20200429204612.31883-1-plaes@plaes.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use syscon-based approach to access gmac clock configuration register instead of relying on a custom clock driver. As a bonus, we can now drop the custom clock implementation and the dummy clocks. Signed-off-by: Priit Laes --- arch/arm/boot/dts/sun6i-a31.dtsi | 35 +++----------------------------- 1 file changed, 3 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index f3425a66fc0a..fcf8a242741f 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -228,36 +228,6 @@ osc32k: clk-32k { clock-output-names = "ext_osc32k"; }; - /* - * The following two are dummy clocks, placeholders - * used in the gmac_tx clock. The gmac driver will - * choose one parent depending on the PHY interface - * mode, using clk_set_rate auto-reparenting. - * - * The actual TX clock rate is not controlled by the - * gmac_tx clock. - */ - mii_phy_tx_clk: clk-mii-phy-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; - }; - - gmac_int_tx_clk: clk-gmac-int-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; - }; - - gmac_tx_clk: clk@1c200d0 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x01c200d0 0x4>; - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac_tx"; - }; }; de: display-engine { @@ -943,11 +913,12 @@ i2c3: i2c@1c2b800 { gmac: ethernet@1c30000 { compatible = "allwinner,sun7i-a20-gmac"; + syscon = <&ccu>; reg = <0x01c30000 0x1054>; interrupts = ; interrupt-names = "macirq"; - clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; + clocks = <&ccu CLK_AHB1_EMAC>; + clock-names = "stmmaceth"; resets = <&ccu RST_AHB1_EMAC>; reset-names = "stmmaceth"; snps,pbl = <2>;