From patchwork Wed Apr 29 21:53:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 201343 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9C8EC8300E for ; Wed, 29 Apr 2020 21:55:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A180720757 for ; Wed, 29 Apr 2020 21:55:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727777AbgD2VyL (ORCPT ); Wed, 29 Apr 2020 17:54:11 -0400 Received: from muru.com ([72.249.23.125]:51782 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726511AbgD2VyK (ORCPT ); Wed, 29 Apr 2020 17:54:10 -0400 Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id E37B2819C; Wed, 29 Apr 2020 21:54:55 +0000 (UTC) From: Tony Lindgren To: Daniel Lezcano , Thomas Gleixner Cc: linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Keerthy , Lokesh Vutla , Tero Kristo , "H. Nikolaus Schaller" , Aaro Koskinen , Adam Ford , Andreas Kemnade , Brian Hutchinson , Graeme Smecher , Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 01/15] clocksource/drivers/timer-ti-32k: Add support for initializing directly Date: Wed, 29 Apr 2020 14:53:48 -0700 Message-Id: <20200429215402.18125-2-tony@atomide.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429215402.18125-1-tony@atomide.com> References: <20200429215402.18125-1-tony@atomide.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Let's allow probing the 32k counter directly based on devicetree data to prepare for dropping the related legacy platform code. Let's only do this if the parent node is compatible with ti-sysc to make sure we have the related devicetree data available. Let's also show the 32k counter information before registering the clocksource, now we see it after the clocksource information which is a bit confusing. Cc: linux-kernel@vger.kernel.org Cc: linux-omap@vger.kernel.org Cc: Daniel Lezcano Cc: Keerthy Cc: Lokesh Vutla Cc: Tero Kristo Cc: Thomas Gleixner Signed-off-by: Tony Lindgren --- drivers/clocksource/timer-ti-32k.c | 48 +++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-ti-32k.c b/drivers/clocksource/timer-ti-32k.c --- a/drivers/clocksource/timer-ti-32k.c +++ b/drivers/clocksource/timer-ti-32k.c @@ -24,6 +24,7 @@ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com */ +#include #include #include #include @@ -76,6 +77,49 @@ static u64 notrace omap_32k_read_sched_clock(void) return ti_32k_read_cycles(&ti_32k_timer.cs); } +static void __init ti_32k_timer_enable_clock(struct device_node *np, + const char *name) +{ + struct clk *clock; + int error; + + clock = of_clk_get_by_name(np->parent, name); + if (IS_ERR(clock)) { + /* Only some SoCs have a separate interface clock */ + if (PTR_ERR(clock) == -EINVAL && !strncmp("ick", name, 3)) + return; + + pr_warn("%s: could not get clock %s %li\n", + __func__, name, PTR_ERR(clock)); + return; + } + + error = clk_prepare_enable(clock); + if (error) { + pr_warn("%s: could not enable %s: %i\n", + __func__, name, error); + return; + } +} + +static void __init ti_32k_timer_module_init(struct device_node *np, + void __iomem *base) +{ + void __iomem *sysc = base + 4; + + if (!of_device_is_compatible(np->parent, "ti,sysc")) + return; + + ti_32k_timer_enable_clock(np, "fck"); + ti_32k_timer_enable_clock(np, "ick"); + + /* + * Force idle module as wkup domain is active with MPU. + * No need to tag the module disabled for ti-sysc probe. + */ + writel_relaxed(0, sysc); +} + static int __init ti_32k_timer_init(struct device_node *np) { int ret; @@ -90,6 +134,7 @@ static int __init ti_32k_timer_init(struct device_node *np) ti_32k_timer.cs.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; ti_32k_timer.counter = ti_32k_timer.base; + ti_32k_timer_module_init(np, ti_32k_timer.base); /* * 32k sync Counter IP register offsets vary between the highlander @@ -104,6 +149,8 @@ static int __init ti_32k_timer_init(struct device_node *np) else ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_LOW; + pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n"); + ret = clocksource_register_hz(&ti_32k_timer.cs, 32768); if (ret) { pr_err("32k_counter: can't register clocksource\n"); @@ -111,7 +158,6 @@ static int __init ti_32k_timer_init(struct device_node *np) } sched_clock_register(omap_32k_read_sched_clock, 32, 32768); - pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n"); return 0; } From patchwork Wed Apr 29 21:53:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 201344 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4029DC8300C for ; Wed, 29 Apr 2020 21:55:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1DDAC20BED for ; Wed, 29 Apr 2020 21:55:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727874AbgD2VyT (ORCPT ); Wed, 29 Apr 2020 17:54:19 -0400 Received: from muru.com ([72.249.23.125]:51876 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727871AbgD2VyS (ORCPT ); Wed, 29 Apr 2020 17:54:18 -0400 Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id 0B508819C; Wed, 29 Apr 2020 21:55:05 +0000 (UTC) From: Tony Lindgren To: Daniel Lezcano , Thomas Gleixner Cc: linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Keerthy , Lokesh Vutla , Tero Kristo , "H. Nikolaus Schaller" , Aaro Koskinen , Adam Ford , Andreas Kemnade , Brian Hutchinson , Graeme Smecher , Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 05/15] bus: ti-sysc: Ignore timer12 on secure omap3 Date: Wed, 29 Apr 2020 14:53:52 -0700 Message-Id: <20200429215402.18125-6-tony@atomide.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429215402.18125-1-tony@atomide.com> References: <20200429215402.18125-1-tony@atomide.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some early omap3 boards use timer12 for system timer, but for secure SoCs like on n900 it's not accessible. Likely we will be configuring unavailable devices for other SoCs too based on runtime SoC detection, so let's use a switch to start with. Cc: Keerthy Cc: Lokesh Vutla Cc: Tero Kristo Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -2744,6 +2744,17 @@ static int sysc_init_soc(struct sysc *ddata) if (match && match->data) sysc_soc->soc = (int)match->data; + /* Ignore devices that are not available on HS and EMU SoCs */ + if (!sysc_soc->general_purpose) { + switch (sysc_soc->soc) { + case SOC_3430 ... SOC_3630: + sysc_add_disabled(0x48304000); /* timer12 */ + break; + default: + break; + }; + } + match = soc_device_match(sysc_soc_feat_match); if (!match) return 0; From patchwork Wed Apr 29 21:53:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 201349 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2124AC8300A for ; Wed, 29 Apr 2020 21:54:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0793720BED for ; Wed, 29 Apr 2020 21:54:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726858AbgD2VyZ (ORCPT ); Wed, 29 Apr 2020 17:54:25 -0400 Received: from muru.com ([72.249.23.125]:51904 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727908AbgD2VyY (ORCPT ); Wed, 29 Apr 2020 17:54:24 -0400 Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id 1FDB1810A; Wed, 29 Apr 2020 21:55:10 +0000 (UTC) From: Tony Lindgren To: Daniel Lezcano , Thomas Gleixner Cc: linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Keerthy , Lokesh Vutla , Tero Kristo , "H. Nikolaus Schaller" , Aaro Koskinen , Adam Ford , Andreas Kemnade , Brian Hutchinson , Graeme Smecher , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org Subject: [PATCH 07/15] ARM: dts: Configure system timers for am335x Date: Wed, 29 Apr 2020 14:53:54 -0700 Message-Id: <20200429215402.18125-8-tony@atomide.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429215402.18125-1-tony@atomide.com> References: <20200429215402.18125-1-tony@atomide.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We can now init system timers using the dmtimer and 32k counter based on only devicetree data and drivers/clocksource timers. Let's configure the clocksource and clockevent, and drop the old unused platform data. As we're just dropping platform data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Since the dmtimer can use both 32k clock and system clock as the source, let's also configure the SoC specific default values. The board specific dts files can reconfigure these with assigned-clocks and assigned-clock-parents as needed. Cc: devicetree@vger.kernel.org Cc: Keerthy Cc: Lokesh Vutla Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 6 ++--- arch/arm/boot/dts/am33xx.dtsi | 24 +++++++++++++++++++ arch/arm/mach-omap2/board-generic.c | 2 +- .../omap_hwmod_33xx_43xx_ipblock_data.c | 2 -- arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 10 -------- 5 files changed, 27 insertions(+), 17 deletions(-) diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -330,9 +330,8 @@ scm_clockdomains: clockdomains { }; }; - target-module@31000 { /* 0x44e31000, ap 25 40.0 */ + timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */ compatible = "ti,sysc-omap2-timer", "ti,sysc"; - ti,hwmods = "timer1"; reg = <0x31000 0x4>, <0x31010 0x4>, <0x31014 0x4>; @@ -1117,9 +1116,8 @@ mcasp1: mcasp@0 { }; }; - target-module@40000 { /* 0x48040000, ap 22 1e.0 */ + timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer2"; reg = <0x40000 0x4>, <0x40010 0x4>, <0x40014 0x4>; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -619,3 +619,27 @@ prm_gfx: prm@1100 { #reset-cells = <1>; }; }; + +/* Timer for clocksource, configured without interrupts */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + compatible = "ti,dmtimer"; + /delete-property/interrupts; + /delete-property/interrupts-extended; + assigned-clocks = <&timer1_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; + +/* Timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + compatible = "ti,dmtimer"; + assigned-clocks = <&timer2_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -236,7 +236,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)") .init_early = am33xx_init_early, .init_machine = omap_generic_init, .init_late = am33xx_init_late, - .init_time = omap3_gptimer_timer_init, + .init_time = omap_init_time_of, .dt_compat = am33xx_boards_compat, .restart = am33xx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -367,12 +367,10 @@ struct omap_hwmod am33xx_timer2_hwmod = { static void omap_hwmod_am33xx_clkctrl(void) { - CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET); CLKCTRL(am33xx_smartreflex0_hwmod, AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET); CLKCTRL(am33xx_smartreflex1_hwmod, AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET); CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET); PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET); CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET); diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -265,14 +265,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { .user = OCP_USER_MPU, }; -/* l4 wkup -> timer1 */ -static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_timer1_hwmod, - .clk = "dpll_core_m4_div2_ck", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l3_main__emif, &am33xx_mpu__l3_main, @@ -291,9 +283,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l4_wkup__control, &am33xx_l4_wkup__smartreflex0, &am33xx_l4_wkup__smartreflex1, - &am33xx_l4_wkup__timer1, &am33xx_l4_wkup__rtc, - &am33xx_l4_ls__timer2, &am33xx_l3_s__gpmc, &am33xx_l3_main__ocmc, NULL, From patchwork Wed Apr 29 21:53:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 201345 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8E1CC8300F for ; Wed, 29 Apr 2020 21:55:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CC91620757 for ; Wed, 29 Apr 2020 21:55:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727772AbgD2Vye (ORCPT ); Wed, 29 Apr 2020 17:54:34 -0400 Received: from muru.com ([72.249.23.125]:51984 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727774AbgD2Vyd (ORCPT ); Wed, 29 Apr 2020 17:54:33 -0400 Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id B244481B1; Wed, 29 Apr 2020 21:55:17 +0000 (UTC) From: Tony Lindgren To: Daniel Lezcano , Thomas Gleixner Cc: linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Keerthy , Lokesh Vutla , Tero Kristo , "H. Nikolaus Schaller" , Aaro Koskinen , Adam Ford , Andreas Kemnade , Brian Hutchinson , Graeme Smecher , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org Subject: [PATCH 10/15] ARM: dts: Configure system timers for omap5 and dra7 Date: Wed, 29 Apr 2020 14:53:57 -0700 Message-Id: <20200429215402.18125-11-tony@atomide.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429215402.18125-1-tony@atomide.com> References: <20200429215402.18125-1-tony@atomide.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We can now init system timers using the dmtimer and 32k counter based on only devicetree data and drivers/clocksource timers. Let's configure the clocksource and clockevent, and drop the old unused platform data. As we're just dropping platform data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Since the dmtimer can use both 32k clock and system clock as the source, let's also configure the SoC specific default values. The board specific dts files can reconfigure these with assigned-clocks and assigned-clock-parents as needed. Note that similar to omap_init_time_of(), we now need to call omap_clk_init() also from omap5_realtime_timer_init(). Cc: devicetree@vger.kernel.org Cc: Keerthy Cc: Lokesh Vutla Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 7 +- arch/arm/boot/dts/dra7.dtsi | 11 ++ arch/arm/boot/dts/omap5-l4.dtsi | 4 +- arch/arm/boot/dts/omap5.dtsi | 11 ++ arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 89 ----------- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 176 --------------------- arch/arm/mach-omap2/timer.c | 17 +- 7 files changed, 25 insertions(+), 290 deletions(-) diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -1143,7 +1143,6 @@ uart3: serial@0 { target-module@32000 { /* 0x48032000, ap 5 3e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer2"; reg = <0x32000 0x4>, <0x32010 0x4>; reg-names = "rev", "sysc"; @@ -1171,7 +1170,6 @@ timer2: timer@0 { target-module@34000 { /* 0x48034000, ap 7 46.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer3"; reg = <0x34000 0x4>, <0x34010 0x4>; reg-names = "rev", "sysc"; @@ -1199,7 +1197,6 @@ timer3: timer@0 { target-module@36000 { /* 0x48036000, ap 9 4e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer4"; reg = <0x36000 0x4>, <0x36010 0x4>; reg-names = "rev", "sysc"; @@ -4295,7 +4292,6 @@ segment@0 { /* 0x4ae00000 */ target-module@4000 { /* 0x4ae04000, ap 15 40.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "counter_32k"; reg = <0x4000 0x4>, <0x4010 0x4>; reg-names = "rev", "sysc"; @@ -4430,9 +4426,8 @@ wdt2: wdt@0 { }; }; - target-module@8000 { /* 0x4ae18000, ap 9 30.0 */ + timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer1"; reg = <0x8000 0x4>, <0x8010 0x4>; reg-names = "rev", "sysc"; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1044,3 +1044,14 @@ prm_eve4: prm@1c00 { reg = <0x1c00 0x60>; }; }; + +/* Timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + compatible = "ti,dmtimer"; + assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>; + assigned-clock-parents = <&sys_32k_ck>; + }; +}; diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -2150,7 +2150,6 @@ segment@0 { /* 0x4ae00000 */ target-module@4000 { /* 0x4ae04000, ap 17 20.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "counter_32k"; reg = <0x4000 0x4>, <0x4010 0x4>; reg-names = "rev", "sysc"; @@ -2336,9 +2335,8 @@ wdt2: wdt@0 { }; }; - target-module@8000 { /* 0x4ae18000, ap 9 18.0 */ + timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 18.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer1"; reg = <0x8000 0x4>, <0x8010 0x4>; reg-names = "rev", "sysc"; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -581,3 +581,14 @@ prm_device: prm@1c00 { #reset-cells = <1>; }; }; + +/* Timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + compatible = "ti,dmtimer"; + assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; + assigned-clock-parents = <&sys_32k_ck>; + }; +}; diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -193,39 +193,6 @@ static struct omap_hwmod omap54xx_mpu_private_hwmod = { }, }; -/* - * 'counter' class - * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock - */ - -static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap54xx_counter_hwmod_class = { - .name = "counter", - .sysc = &omap54xx_counter_sysc, -}; - -/* counter_32k */ -static struct omap_hwmod omap54xx_counter_32k_hwmod = { - .name = "counter_32k", - .class = &omap54xx_counter_hwmod_class, - .clkdm_name = "wkupaon_clkdm", - .flags = HWMOD_SWSUP_SIDLE, - .main_clk = "wkupaon_iclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET, - }, - }, -}; - /* * 'emif' class * external memory interface no1 (wrapper) @@ -299,44 +266,6 @@ static struct omap_hwmod omap54xx_mpu_hwmod = { }, }; - -/* - * 'timer' class - * general purpose timer module with accurate 1ms tick - * This class contains several variants: ['timer_1ms', 'timer'] - */ - -static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = { - .name = "timer", - .sysc = &omap54xx_timer_1ms_sysc, -}; - -/* timer1 */ -static struct omap_hwmod omap54xx_timer1_hwmod = { - .name = "timer1", - .class = &omap54xx_timer_1ms_hwmod_class, - .clkdm_name = "wkupaon_clkdm", - .main_clk = "timer1_gfclk_mux", - .flags = HWMOD_SET_DEFAULT_CLOCKACT, - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* * 'usb_host_hs' class * high-speed multi-port usb host controller @@ -666,14 +595,6 @@ static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_wkup -> counter_32k */ -static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = { - .master = &omap54xx_l4_wkup_hwmod, - .slave = &omap54xx_counter_32k_hwmod, - .clk = "wkupaon_iclk_mux", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* mpu -> emif1 */ static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = { .master = &omap54xx_mpu_hwmod, @@ -698,14 +619,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = { - .master = &omap54xx_l4_wkup_hwmod, - .slave = &omap54xx_timer1_hwmod, - .clk = "wkupaon_iclk_mux", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_cfg -> usb_host_hs */ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = { .master = &omap54xx_l4_cfg_hwmod, @@ -747,11 +660,9 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_l3_main_2__l4_per, &omap54xx_l3_main_1__l4_wkup, &omap54xx_mpu__mpu_private, - &omap54xx_l4_wkup__counter_32k, &omap54xx_mpu__emif1, &omap54xx_mpu__emif2, &omap54xx_l4_cfg__mpu, - &omap54xx_l4_wkup__timer1, &omap54xx_l4_cfg__usb_host_hs, &omap54xx_l4_cfg__usb_tll_hs, &omap54xx_l4_cfg__usb_otg_ss, diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -221,40 +221,6 @@ static struct omap_hwmod dra7xx_bb2d_hwmod = { }, }; -/* - * 'counter' class - * - */ - -static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class dra7xx_counter_hwmod_class = { - .name = "counter", - .sysc = &dra7xx_counter_sysc, -}; - -/* counter_32k */ -static struct omap_hwmod dra7xx_counter_32k_hwmod = { - .name = "counter_32k", - .class = &dra7xx_counter_hwmod_class, - .clkdm_name = "wkupaon_clkdm", - .flags = HWMOD_SWSUP_SIDLE, - .main_clk = "wkupaon_iclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET, - }, - }, -}; - /* * 'ctrl_module' class * @@ -525,103 +491,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = { }, }; -/* - * 'timer' class - * - * This class contains several variants: ['timer_1ms', 'timer_secure', - * 'timer'] - */ - -static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = { - .name = "timer", - .sysc = &dra7xx_timer_1ms_sysc, -}; - -static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class dra7xx_timer_hwmod_class = { - .name = "timer", - .sysc = &dra7xx_timer_sysc, -}; - -/* timer1 */ -static struct omap_hwmod dra7xx_timer1_hwmod = { - .name = "timer1", - .class = &dra7xx_timer_1ms_hwmod_class, - .clkdm_name = "wkupaon_clkdm", - .main_clk = "timer1_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer2 */ -static struct omap_hwmod dra7xx_timer2_hwmod = { - .name = "timer2", - .class = &dra7xx_timer_1ms_hwmod_class, - .clkdm_name = "l4per_clkdm", - .main_clk = "timer2_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer3 */ -static struct omap_hwmod dra7xx_timer3_hwmod = { - .name = "timer3", - .class = &dra7xx_timer_hwmod_class, - .clkdm_name = "l4per_clkdm", - .main_clk = "timer3_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer4 */ -static struct omap_hwmod dra7xx_timer4_hwmod = { - .name = "timer4", - .class = &dra7xx_timer_hwmod_class, - .clkdm_name = "l4per_clkdm", - .main_clk = "timer4_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* * 'usb_otg_ss' class * @@ -864,14 +733,6 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_wkup -> counter_32k */ -static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = { - .master = &dra7xx_l4_wkup_hwmod, - .slave = &dra7xx_counter_32k_hwmod, - .clk = "wkupaon_iclk_mux", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_wkup -> ctrl_module_wkup */ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = { .master = &dra7xx_l4_wkup_hwmod, @@ -952,38 +813,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = { - .master = &dra7xx_l4_wkup_hwmod, - .slave = &dra7xx_timer1_hwmod, - .clk = "wkupaon_iclk_mux", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per1 -> timer2 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = { - .master = &dra7xx_l4_per1_hwmod, - .slave = &dra7xx_timer2_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per1 -> timer3 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = { - .master = &dra7xx_l4_per1_hwmod, - .slave = &dra7xx_timer3_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per1 -> timer4 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = { - .master = &dra7xx_l4_per1_hwmod, - .slave = &dra7xx_timer4_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_per3 -> usb_otg_ss1 */ static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = { .master = &dra7xx_l4_per3_hwmod, @@ -1062,7 +891,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l3_main_1__l4_wkup, &dra7xx_l4_per2__atl, &dra7xx_l3_main_1__bb2d, - &dra7xx_l4_wkup__counter_32k, &dra7xx_l4_wkup__ctrl_module_wkup, &dra7xx_l3_main_1__gpmc, &dra7xx_l4_cfg__mpu, @@ -1072,10 +900,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_cfg__pciess2, &dra7xx_l3_main_1__qspi, &dra7xx_l4_cfg__sata, - &dra7xx_l4_wkup__timer1, - &dra7xx_l4_per1__timer2, - &dra7xx_l4_per1__timer3, - &dra7xx_l4_per1__timer4, &dra7xx_l4_per3__usb_otg_ss1, &dra7xx_l4_per3__usb_otg_ss2, &dra7xx_l4_per3__usb_otg_ss3, diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -576,21 +576,6 @@ void __init omap3_gptimer_timer_init(void) } #endif -#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ - defined(CONFIG_SOC_DRA7XX) -static void __init omap4_sync32k_timer_init(void) -{ - __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", - 0, NULL, NULL, false); -} - -void __init omap4_local_timer_init(void) -{ - omap4_sync32k_timer_init(); - timer_probe(); -} -#endif - #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) /* @@ -708,7 +693,7 @@ static void __init realtime_counter_init(void) void __init omap5_realtime_timer_init(void) { - omap4_sync32k_timer_init(); + omap_clk_init(); realtime_counter_init(); timer_probe(); From patchwork Wed Apr 29 21:53:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 201346 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CEC2C83000 for ; Wed, 29 Apr 2020 21:55:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 33B6A20757 for ; Wed, 29 Apr 2020 21:55:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727986AbgD2Vyh (ORCPT ); Wed, 29 Apr 2020 17:54:37 -0400 Received: from muru.com ([72.249.23.125]:52018 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727917AbgD2Vyg (ORCPT ); Wed, 29 Apr 2020 17:54:36 -0400 Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id A94E1810A; Wed, 29 Apr 2020 21:55:20 +0000 (UTC) From: Tony Lindgren To: Daniel Lezcano , Thomas Gleixner Cc: linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Adam Ford , Andreas Kemnade , "H. Nikolaus Schaller" , Keerthy , Lokesh Vutla , Tero Kristo , Aaro Koskinen , Brian Hutchinson , Graeme Smecher , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org Subject: [PATCH 11/15] ARM: dts: Configure system timers for omap3 Date: Wed, 29 Apr 2020 14:53:58 -0700 Message-Id: <20200429215402.18125-12-tony@atomide.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429215402.18125-1-tony@atomide.com> References: <20200429215402.18125-1-tony@atomide.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We can now init system timers using the dmtimer and 32k counter based on only devicetree data and drivers/clocksource timers. Let's configure the clocksource and clockevent, and drop the old unused platform data. As we're just dropping platform data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Since the dmtimer can use both 32k clock and system clock as the source, let's also configure the SoC specific default values. The board specific dts files can reconfigure these with assigned-clocks and assigned-clock-parents as needed. Let's also update the dts file to use #include while at it. Cc: devicetree@vger.kernel.org Cc: Adam Ford Cc: Andreas Kemnade Cc: "H. Nikolaus Schaller" Cc: Keerthy Cc: Lokesh Vutla Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am3517.dtsi | 28 +++- arch/arm/boot/dts/omap3-beagle.dts | 33 +++++ arch/arm/boot/dts/omap3-devkit8000.dts | 33 +++++ arch/arm/boot/dts/omap3.dtsi | 135 +++++++++++++++---- arch/arm/mach-omap2/board-generic.c | 10 +- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 146 +-------------------- 6 files changed, 210 insertions(+), 175 deletions(-) diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi --- a/arch/arm/boot/dts/am3517.dtsi +++ b/arch/arm/boot/dts/am3517.dtsi @@ -169,5 +169,29 @@ &mmu_isp { status = "disabled"; }; -/include/ "am35xx-clocks.dtsi" -/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" +#include "am35xx-clocks.dtsi" +#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" + +/* Timer for clocksource, configured without interrupts */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + compatible = "ti,dmtimer"; + /delete-property/interrupts; + /delete-property/interrupts-extended; + assigned-clocks = <&gpt1_fck>; + assigned-clock-parents = <&sys_ck>; + }; +}; + +/* Timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + compatible = "ti,dmtimer"; + assigned-clocks = <&gpt2_fck>; + assigned-clock-parents = <&sys_ck>; + }; +}; diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -304,6 +304,39 @@ &usbhsehci { phys = <0 &hsusb2_phy>; }; +/* Unusable as clockevent, allow to idle */ +&timer1_target { + /delete-property/ti,no-reset-on-init; + /delete-property/ti,no-idle; + timer@0 { + compatible = "ti,omap3430-timer"; + interrupts = <37>; + }; +}; + +/* Timer for clocksource, configured without interrupts */ +&timer12_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + compatible = "ti,dmtimer"; + /delete-property/interrupts; + /delete-property/interrupts-extended; + /* Always clocked by secure_32k_fck */ + }; +}; + +/* Timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + compatible = "ti,dmtimer"; + assigned-clocks = <&gpt2_fck>; + assigned-clock-parents = <&sys_ck>; + }; +}; + &twl_gpio { ti,use-leds; /* pullups: BIT(1) */ diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts --- a/arch/arm/boot/dts/omap3-devkit8000.dts +++ b/arch/arm/boot/dts/omap3-devkit8000.dts @@ -14,3 +14,36 @@ aliases { display2 = &tv0; }; }; + +/* Unusable as clockevent, allow to idle */ +&timer1_target { + /delete-property/ti,no-reset-on-init; + /delete-property/ti,no-idle; + timer@0 { + compatible = "ti,omap3430-timer"; + interrupts = <37>; + }; +}; + +/* Timer for clocksource, configured without interrupts */ +&timer12_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + compatible = "ti,dmtimer"; + /delete-property/interrupts; + /delete-property/interrupts-extended; + /* Always clocked by secure_32k_fck */ + }; +}; + +/* Timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + compatible = "ti,dmtimer"; + assigned-clocks = <&gpt2_fck>; + assigned-clock-parents = <&sys_ck>; + }; +}; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -193,10 +193,23 @@ cm_clockdomains: clockdomains { }; }; - counter32k: counter@48320000 { - compatible = "ti,omap-counter32k"; - reg = <0x48320000 0x20>; - ti,hwmods = "counter_32k"; + target-module@48320000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x48320000 0x4>, + <0x48320004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48320000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0x0 0x20>; + }; }; intc: interrupt-controller@48200000 { @@ -637,19 +650,63 @@ sham: sham@480c3000 { dma-names = "rx"; }; - timer1: timer@48318000 { - compatible = "ti,omap3430-timer"; - reg = <0x48318000 0x400>; - interrupts = <37>; - ti,hwmods = "timer1"; - ti,timer-alwon; + timer1_target: target-module@48318000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x48318000 0x4>, + <0x48318010 0x4>, + <0x48318014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt1_fck>, <&gpt1_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48318000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0x0 0x80>; + clocks = <&gpt1_fck>; + clock-names = "fck"; + interrupts = <37>; + ti,timer-alwon; + }; }; - timer2: timer@49032000 { - compatible = "ti,omap3430-timer"; - reg = <0x49032000 0x400>; - interrupts = <38>; - ti,hwmods = "timer2"; + timer2_target: target-module@49032000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x49032000 0x4>, + <0x49032010 0x4>, + <0x49032014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt2_fck>, <&gpt2_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49032000 0x1000>; + + timer2: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0 0x400>; + interrupts = <38>; + }; }; timer3: timer@49034000 { @@ -723,13 +780,34 @@ timer11: timer@48088000 { ti,timer-pwm; }; - timer12: timer@48304000 { - compatible = "ti,omap3430-timer"; - reg = <0x48304000 0x400>; - interrupts = <95>; - ti,hwmods = "timer12"; - ti,timer-alwon; - ti,timer-secure; + timer12_target: target-module@48304000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x48304000 0x4>, + <0x48304010 0x4>, + <0x48304014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt12_fck>, <&gpt12_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48304000 0x1000>; + + timer12: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0 0x400>; + interrupts = <95>; + ti,timer-alwon; + ti,timer-secure; + }; }; usbhstll: usbhstll@48062000 { @@ -886,4 +964,15 @@ ssi_port2: ssi-port@4805b000 { }; }; -/include/ "omap3xxx-clocks.dtsi" +#include "omap3xxx-clocks.dtsi" + +/* Timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + compatible = "ti,dmtimer"; + assigned-clocks = <&gpt1_fck>; + assigned-clock-parents = <&omap_32k_fck>; + }; +}; diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -114,7 +114,7 @@ DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board") .init_early = omap3430_init_early, .init_machine = omap_generic_init, .init_late = omap3_init_late, - .init_time = omap_init_time, + .init_time = omap_init_time_of, .dt_compat = n900_boards_compat, .restart = omap3xxx_restart, MACHINE_END @@ -132,7 +132,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") .init_early = omap3430_init_early, .init_machine = omap_generic_init, .init_late = omap3_init_late, - .init_time = omap_init_time, + .init_time = omap_init_time_of, .dt_compat = omap3_boards_compat, .restart = omap3xxx_restart, MACHINE_END @@ -149,7 +149,7 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)") .init_early = omap3630_init_early, .init_machine = omap_generic_init, .init_late = omap3_init_late, - .init_time = omap_init_time, + .init_time = omap_init_time_of, .dt_compat = omap36xx_boards_compat, .restart = omap3xxx_restart, MACHINE_END @@ -166,7 +166,7 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)") .init_early = omap3430_init_early, .init_machine = omap_generic_init, .init_late = omap3_init_late, - .init_time = omap3_secure_sync32k_timer_init, + .init_time = omap_init_time_of, .dt_compat = omap3_gp_boards_compat, .restart = omap3xxx_restart, MACHINE_END @@ -182,7 +182,7 @@ DT_MACHINE_START(AM3517_DT, "Generic AM3517 (Flattened Device Tree)") .init_early = am35xx_init_early, .init_machine = omap_generic_init, .init_late = omap3_init_late, - .init_time = omap3_gptimer_timer_init, + .init_time = omap_init_time_of, .dt_compat = am3517_boards_compat, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -147,36 +147,6 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { .sysc = &omap3xxx_timer_sysc, }; -/* timer1 */ -static struct omap_hwmod omap3xxx_timer1_hwmod = { - .name = "timer1", - .main_clk = "gpt1_fck", - .prcm = { - .omap2 = { - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, - }, - }, - .class = &omap3xxx_timer_hwmod_class, - .flags = HWMOD_SET_DEFAULT_CLOCKACT, -}; - -/* timer2 */ -static struct omap_hwmod omap3xxx_timer2_hwmod = { - .name = "timer2", - .main_clk = "gpt2_fck", - .prcm = { - .omap2 = { - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, - }, - }, - .class = &omap3xxx_timer_hwmod_class, - .flags = HWMOD_SET_DEFAULT_CLOCKACT, -}; - /* timer3 */ static struct omap_hwmod omap3xxx_timer3_hwmod = { .name = "timer3", @@ -312,21 +282,6 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = { .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; -/* timer12 */ -static struct omap_hwmod omap3xxx_timer12_hwmod = { - .name = "timer12", - .main_clk = "gpt12_fck", - .prcm = { - .omap2 = { - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, - }, - }, - .class = &omap3xxx_timer_hwmod_class, - .flags = HWMOD_SET_DEFAULT_CLOCKACT, -}; - /* * 'wd_timer' class * 32-bit watchdog upward counter that generates a pulse on the reset pin on @@ -1524,38 +1479,6 @@ static struct omap_hwmod omap3xxx_sad2d_hwmod = { .class = &omap3xxx_sad2d_class, }; -/* - * '32K sync counter' class - * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock - */ -static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0004, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap3xxx_counter_hwmod_class = { - .name = "counter", - .sysc = &omap3xxx_counter_sysc, -}; - -static struct omap_hwmod omap3xxx_counter_32k_hwmod = { - .name = "counter_32k", - .class = &omap3xxx_counter_hwmod_class, - .clkdm_name = "wkup_clkdm", - .flags = HWMOD_SWSUP_SIDLE, - .main_clk = "wkup_32k_fck", - .prcm = { - .omap2 = { - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT, - }, - }, -}; - /* * 'gpmc' class * general purpose memory controller @@ -1868,25 +1791,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; - -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_timer1_hwmod, - .clk = "gpt1_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - - -/* l4_per -> timer2 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer2_hwmod, - .clk = "gpt2_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - - /* l4_per -> timer3 */ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { .master = &omap3xxx_l4_per_hwmod, @@ -1965,15 +1869,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; - -/* l4_core -> timer12 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { - .master = &omap3xxx_l4_sec_hwmod, - .slave = &omap3xxx_timer12_hwmod, - .clk = "gpt12_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_wkup -> wd_timer2 */ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { @@ -2325,16 +2220,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, }; -/* l4_wkup -> 32ksync_counter */ - - -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_counter_32k_hwmod, - .clk = "omap_32ksync_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* am35xx has Davinci MDIO & EMAC */ static struct omap_hwmod_class am35xx_mdio_class = { .name = "davinci_mdio", @@ -2551,8 +2436,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap3_l4_core__i2c2, &omap3_l4_core__i2c3, &omap3xxx_l4_wkup__l4_sec, - &omap3xxx_l4_wkup__timer1, - &omap3xxx_l4_per__timer2, &omap3xxx_l4_per__timer3, &omap3xxx_l4_per__timer4, &omap3xxx_l4_per__timer5, @@ -2580,27 +2463,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap34xx_l4_core__mcspi2, &omap34xx_l4_core__mcspi3, &omap34xx_l4_core__mcspi4, - &omap3xxx_l4_wkup__counter_32k, &omap3xxx_l3_main__gpmc, NULL, }; -/* GP-only hwmod links */ -static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = { - &omap3xxx_l4_sec__timer12, - NULL, -}; - -static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = { - &omap3xxx_l4_sec__timer12, - NULL, -}; - -static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = { - &omap3xxx_l4_sec__timer12, - NULL, -}; - /* crypto hwmod links */ static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l4_core__sham, @@ -2774,7 +2640,7 @@ static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus, int __init omap3xxx_hwmod_init(void) { int r; - struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL; + struct omap_hwmod_ocp_if **h = NULL, **h_sham = NULL; struct omap_hwmod_ocp_if **h_aes = NULL; struct device_node *bus; unsigned int rev; @@ -2797,18 +2663,15 @@ int __init omap3xxx_hwmod_init(void) rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { h = omap34xx_hwmod_ocp_ifs; - h_gp = omap34xx_gp_hwmod_ocp_ifs; h_sham = omap34xx_sham_hwmod_ocp_ifs; h_aes = omap34xx_aes_hwmod_ocp_ifs; } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { h = am35xx_hwmod_ocp_ifs; - h_gp = am35xx_gp_hwmod_ocp_ifs; h_sham = am35xx_sham_hwmod_ocp_ifs; h_aes = am35xx_aes_hwmod_ocp_ifs; } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2) { h = omap36xx_hwmod_ocp_ifs; - h_gp = omap36xx_gp_hwmod_ocp_ifs; h_sham = omap36xx_sham_hwmod_ocp_ifs; h_aes = omap36xx_aes_hwmod_ocp_ifs; } else { @@ -2820,13 +2683,6 @@ int __init omap3xxx_hwmod_init(void) if (r < 0) return r; - /* Register GP-only hwmod links. */ - if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) { - r = omap_hwmod_register_links(h_gp); - if (r < 0) - return r; - } - /* * Register crypto hwmod links only if they are not disabled in DT. * If DT information is missing, enable them only for GP devices. From patchwork Wed Apr 29 21:53:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 201348 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1E83C8300B for ; Wed, 29 Apr 2020 21:54:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D2F0620BED for ; Wed, 29 Apr 2020 21:54:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728007AbgD2Vyj (ORCPT ); Wed, 29 Apr 2020 17:54:39 -0400 Received: from muru.com ([72.249.23.125]:52036 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727982AbgD2Vyi (ORCPT ); Wed, 29 Apr 2020 17:54:38 -0400 Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id 63311819C; Wed, 29 Apr 2020 21:55:23 +0000 (UTC) From: Tony Lindgren To: Daniel Lezcano , Thomas Gleixner Cc: linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Brian Hutchinson , Graeme Smecher , Keerthy , Lokesh Vutla , Tero Kristo , "H. Nikolaus Schaller" , Aaro Koskinen , Adam Ford , Andreas Kemnade , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org Subject: [PATCH 12/15] ARM: dts: Configure system timers for ti81xx Date: Wed, 29 Apr 2020 14:53:59 -0700 Message-Id: <20200429215402.18125-13-tony@atomide.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429215402.18125-1-tony@atomide.com> References: <20200429215402.18125-1-tony@atomide.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We can now init system timers using the dmtimer and 32k counter based on only devicetree data and drivers/clocksource timers. Let's configure the clocksource and clockevent, and drop the old unused platform data. As we're just dropping platform data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Since the dmtimer can use both 32k clock and system clock as the source, let's also configure the SoC specific default values. The board specific dts files can reconfigure these with assigned-clocks and assigned-clock-parents as needed. Note that for ti81xx, also timer1 is of type 2 unlike on am335x where timer1 is type1 while the rest of the timers are type 2. Cc: devicetree@vger.kernel.org Cc: Brian Hutchinson Cc: Graeme Smecher Cc: Keerthy Cc: Lokesh Vutla Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm814x.dtsi | 78 +++++++++++++++++--- arch/arm/boot/dts/dm816x.dtsi | 82 ++++++++++++++++++---- arch/arm/mach-omap2/board-generic.c | 4 +- arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 74 ------------------- 4 files changed, 138 insertions(+), 100 deletions(-) diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -308,14 +308,30 @@ mcspi4: spi@1a4000 { ti,hwmods = "mcspi4"; }; - timer1: timer@2e000 { - compatible = "ti,dm814-timer"; - reg = <0x2e000 0x2000>; - interrupts = <67>; - ti,hwmods = "timer1"; - ti,timer-alwon; + timer1_target: target-module@2e000 { + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x2e000 0x4>, + <0x2e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; clocks = <&timer1_fck>; clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2e000 0x1000>; + + timer1: timer@0 { + compatible = "ti,am335x-timer-1ms"; + reg = <0x0 0x400>; + interrupts = <67>; + ti,timer-alwon; + clocks = <&timer1_fck>; + clock-names = "fck"; + }; }; uart1: uart@20000 { @@ -348,13 +364,29 @@ uart3: uart@24000 { dma-names = "tx", "rx"; }; - timer2: timer@40000 { - compatible = "ti,dm814-timer"; - reg = <0x40000 0x2000>; - interrupts = <68>; - ti,hwmods = "timer2"; + timer2_target: target-module@40000 { + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x40000 0x4>, + <0x40010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; clocks = <&timer2_fck>; clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x1000>; + + timer2: timer@0 { + compatible = "ti,dm814-timer"; + reg = <0 0x1000>; + interrupts = <68>; + clocks = <&timer2_fck>; + clock-names = "fck"; + }; }; timer3: timer@42000 { @@ -735,3 +767,27 @@ gpmc: gpmc@50000000 { }; #include "dm814x-clocks.dtsi" + +/* Timer for clocksource, configured without interrupts */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + compatible = "ti,dmtimer"; + /delete-property/interrupts; + /delete-property/interrupts-extended; + assigned-clocks = <&timer1_fck>; + assigned-clock-parents = <&devosc_ck>; + }; +}; + +/* Timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + compatible = "ti,dmtimer"; + assigned-clocks = <&timer2_fck>; + assigned-clock-parents = <&devosc_ck>; + }; +}; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -440,23 +440,55 @@ mmc1: mmc@48060000 { dma-names = "tx", "rx"; }; - timer1: timer@4802e000 { - compatible = "ti,dm816-timer"; - reg = <0x4802e000 0x2000>; - interrupts = <67>; - ti,hwmods = "timer1"; - ti,timer-alwon; - clocks = <&timer1_fck>; + timer1_target: target-module@4802e000 { + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x4802e000 0x4>, + <0x4802e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>; clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4802e000 0x1000>; + + timer1: timer@0 { + compatible = "ti,dm816-timer"; + reg = <0 0x1000>; + interrupts = <67>; + ti,timer-alwon; + clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>; + clock-names = "fck"; + }; }; - timer2: timer@48040000 { - compatible = "ti,dm816-timer"; - reg = <0x48040000 0x2000>; - interrupts = <68>; - ti,hwmods = "timer2"; - clocks = <&timer2_fck>; + timer2_target: target-module@48040000 { + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x48040000 0x4>, + <0x48040010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>; clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48040000 0x1000>; + + timer2: timer@0 { + compatible = "ti,dm816-timer"; + reg = <0 0x1000>; + interrupts = <68>; + clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + }; }; timer3: timer@48042000 { @@ -642,3 +674,27 @@ wd_timer2: wd_timer@480c2000 { }; #include "dm816x-clocks.dtsi" + +/* Timer for clocksource, configured without interrupts */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + compatible = "ti,dmtimer"; + /delete-property/interrupts; + /delete-property/interrupts-extended; + assigned-clocks = <&timer1_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; + +/* Timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + compatible = "ti,dmtimer"; + assigned-clocks = <&timer2_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -201,7 +201,7 @@ DT_MACHINE_START(TI814X_DT, "Generic ti814x (Flattened Device Tree)") .init_early = ti814x_init_early, .init_machine = omap_generic_init, .init_late = ti81xx_init_late, - .init_time = omap3_gptimer_timer_init, + .init_time = omap_init_time_of, .dt_compat = ti814x_boards_compat, .restart = ti81xx_restart, MACHINE_END @@ -218,7 +218,7 @@ DT_MACHINE_START(TI816X_DT, "Generic ti816x (Flattened Device Tree)") .init_early = ti816x_init_early, .init_machine = omap_generic_init, .init_late = ti81xx_init_late, - .init_time = omap3_gptimer_timer_init, + .init_time = omap_init_time_of, .dt_compat = ti816x_boards_compat, .restart = ti81xx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -690,76 +690,6 @@ static struct omap_hwmod_class dm816x_timer_hwmod_class = { .sysc = &dm816x_timer_sysc, }; -static struct omap_hwmod dm814x_timer1_hwmod = { - .name = "timer1", - .clkdm_name = "alwon_l3s_clkdm", - .main_clk = "timer1_fck", - .class = &dm816x_timer_hwmod_class, - .flags = HWMOD_NO_IDLEST, -}; - -static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = { - .master = &dm81xx_l4_ls_hwmod, - .slave = &dm814x_timer1_hwmod, - .clk = "sysclk6_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod dm816x_timer1_hwmod = { - .name = "timer1", - .clkdm_name = "alwon_l3s_clkdm", - .main_clk = "timer1_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .class = &dm816x_timer_hwmod_class, -}; - -static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = { - .master = &dm81xx_l4_ls_hwmod, - .slave = &dm816x_timer1_hwmod, - .clk = "sysclk6_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod dm814x_timer2_hwmod = { - .name = "timer2", - .clkdm_name = "alwon_l3s_clkdm", - .main_clk = "timer2_fck", - .class = &dm816x_timer_hwmod_class, - .flags = HWMOD_NO_IDLEST, -}; - -static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = { - .master = &dm81xx_l4_ls_hwmod, - .slave = &dm814x_timer2_hwmod, - .clk = "sysclk6_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod dm816x_timer2_hwmod = { - .name = "timer2", - .clkdm_name = "alwon_l3s_clkdm", - .main_clk = "timer2_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .class = &dm816x_timer_hwmod_class, -}; - -static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = { - .master = &dm81xx_l4_ls_hwmod, - .slave = &dm816x_timer2_hwmod, - .clk = "sysclk6_ck", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod dm816x_timer3_hwmod = { .name = "timer3", .clkdm_name = "alwon_l3s_clkdm", @@ -1288,8 +1218,6 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { &dm814x_l4_ls__mmc1, &dm814x_l4_ls__mmc2, &ti81xx_l4_ls__rtc, - &dm814x_l4_ls__timer1, - &dm814x_l4_ls__timer2, &dm81xx_alwon_l3_slow__gpmc, &dm814x_default_l3_slow__usbss, &dm814x_alwon_l3_med__mmc3, @@ -1318,8 +1246,6 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { &dm81xx_l4_ls__elm, &ti81xx_l4_ls__rtc, &dm816x_l4_ls__mmc1, - &dm816x_l4_ls__timer1, - &dm816x_l4_ls__timer2, &dm816x_l4_ls__timer3, &dm816x_l4_ls__timer4, &dm816x_l4_ls__timer5, From patchwork Wed Apr 29 21:54:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 201347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB215C8300C for ; Wed, 29 Apr 2020 21:54:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A415520757 for ; Wed, 29 Apr 2020 21:54:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728025AbgD2Vym (ORCPT ); Wed, 29 Apr 2020 17:54:42 -0400 Received: from muru.com ([72.249.23.125]:52050 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728008AbgD2Vyl (ORCPT ); Wed, 29 Apr 2020 17:54:41 -0400 Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id DFED581AC; Wed, 29 Apr 2020 21:55:25 +0000 (UTC) From: Tony Lindgren To: Daniel Lezcano , Thomas Gleixner Cc: linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Aaro Koskinen , Keerthy , Lokesh Vutla , Tero Kristo , "H. Nikolaus Schaller" , Adam Ford , Andreas Kemnade , Brian Hutchinson , Graeme Smecher , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org Subject: [PATCH 13/15] ARM: dts: Configure system timers for omap2 Date: Wed, 29 Apr 2020 14:54:00 -0700 Message-Id: <20200429215402.18125-14-tony@atomide.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429215402.18125-1-tony@atomide.com> References: <20200429215402.18125-1-tony@atomide.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We can now init system timers using the dmtimer and 32k counter based on only devicetree data and drivers/clocksource timers. Let's configure the clocksource and clockevent, and drop the old unused platform data. As we're just dropping platform data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Since the dmtimer can use both 32k clock and system clock as the source, let's also configure the SoC specific default values. The board specific dts files can reconfigure these with assigned-clocks and assigned-clock-parents as needed. Let's also update the dts file to use #include while at it. Cc: devicetree@vger.kernel.org Cc: Aaro Koskinen Cc: Keerthy Cc: Lokesh Vutla Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap2.dtsi | 31 +++++++-- arch/arm/boot/dts/omap2420.dtsi | 69 +++++++++++++++---- arch/arm/boot/dts/omap2430.dtsi | 69 +++++++++++++++---- arch/arm/mach-omap2/board-generic.c | 4 +- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 20 ------ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 19 ----- .../omap_hwmod_2xxx_interconnect_data.c | 8 --- .../mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 47 ------------- arch/arm/mach-omap2/omap_hwmod_common_data.h | 3 - 9 files changed, 142 insertions(+), 128 deletions(-) diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi --- a/arch/arm/boot/dts/omap2.dtsi +++ b/arch/arm/boot/dts/omap2.dtsi @@ -201,11 +201,32 @@ uart3: serial@4806e000 { clock-frequency = <48000000>; }; - timer2: timer@4802a000 { - compatible = "ti,omap2420-timer"; - reg = <0x4802a000 0x400>; - interrupts = <38>; - ti,hwmods = "timer2"; + timer2_target: target-module@4802a000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x4802a000 0x4>, + <0x4802a010 0x4>, + <0x4802a014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt2_fck>, <&gpt2_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4802a000 0x1000>; + + timer2: timer@0 { + compatible = "ti,omap2420-timer"; + reg = <0 0x400>; + interrupts = <38>; + }; }; timer3: timer@48078000 { diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -68,10 +68,23 @@ scm_clockdomains: clockdomains { }; }; - counter32k: counter@4000 { - compatible = "ti,omap-counter32k"; - reg = <0x4000 0x20>; - ti,hwmods = "counter_32k"; + target-module@4000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4000 0x4>, + <0x4004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + clocks = <&func_32k_ck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0 0x20>; + }; }; }; @@ -194,12 +207,33 @@ mbox_iva: iva { }; }; - timer1: timer@48028000 { - compatible = "ti,omap2420-timer"; - reg = <0x48028000 0x400>; - interrupts = <37>; - ti,hwmods = "timer1"; - ti,timer-alwon; + timer1_target: target-module@48028000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x48028000 0x4>, + <0x48028010 0x4>, + <0x48028014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt1_fck>, <&gpt1_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48028000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap2420-timer"; + reg = <0 0x400>; + interrupts = <37>; + ti,timer-alwon; + }; }; wd_timer2: wdt@48022000 { @@ -218,5 +252,16 @@ &i2c2 { compatible = "ti,omap2420-i2c"; }; -/include/ "omap24xx-clocks.dtsi" -/include/ "omap2420-clocks.dtsi" +#include "omap24xx-clocks.dtsi" +#include "omap2420-clocks.dtsi" + +/* Timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + compatible = "ti,dmtimer"; + assigned-clocks = <&gpt1_fck>; + assigned-clock-parents = <&func_32k_ck>; + }; +}; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -81,10 +81,23 @@ scm_clockdomains: clockdomains { }; }; - counter32k: counter@20000 { - compatible = "ti,omap-counter32k"; - reg = <0x20000 0x20>; - ti,hwmods = "counter_32k"; + target-module@20000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x20000 0x4>, + <0x20004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + clocks = <&func_32k_ck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0 0x20>; + }; }; }; @@ -277,12 +290,33 @@ mbox_dsp: dsp { }; }; - timer1: timer@49018000 { - compatible = "ti,omap2420-timer"; - reg = <0x49018000 0x400>; - interrupts = <37>; - ti,hwmods = "timer1"; - ti,timer-alwon; + timer1_target: target-module@49018000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x49018000 0x4>, + <0x49018010 0x4>, + <0x49018014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt1_fck>, <&gpt1_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49018000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap2420-timer"; + reg = <0 0x400>; + interrupts = <37>; + ti,timer-alwon; + }; }; mcspi3: spi@480b8000 { @@ -321,5 +355,16 @@ &i2c2 { compatible = "ti,omap2430-i2c"; }; -/include/ "omap24xx-clocks.dtsi" -/include/ "omap2430-clocks.dtsi" +#include "omap24xx-clocks.dtsi" +#include "omap2430-clocks.dtsi" + +/* Timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + compatible = "ti,dmtimer"; + assigned-clocks = <&gpt1_fck>; + assigned-clock-parents = <&func_32k_ck>; + }; +}; diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -50,7 +50,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)") .map_io = omap242x_map_io, .init_early = omap2420_init_early, .init_machine = omap_generic_init, - .init_time = omap_init_time, + .init_time = omap_init_time_of, .dt_compat = omap242x_boards_compat, .restart = omap2xxx_restart, MACHINE_END @@ -67,7 +67,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)") .map_io = omap243x_map_io, .init_early = omap2430_init_early, .init_machine = omap_generic_init, - .init_time = omap_init_time, + .init_time = omap_init_time_of, .dt_compat = omap243x_boards_compat, .restart = omap2xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -264,14 +264,6 @@ static struct omap_hwmod_ocp_if omap2420_l3__dsp = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_timer1_hwmod, - .clk = "gpt1_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_wkup -> wd_timer2 */ static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { .master = &omap2xxx_l4_wkup_hwmod, @@ -352,15 +344,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = { .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, }; - -/* l4_wkup -> 32ksync_counter */ -static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_counter_32k_hwmod, - .clk = "sync_32k_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_ocp_if omap2420_l3__gpmc = { .master = &omap2xxx_l3_main_hwmod, .slave = &omap2xxx_gpmc_hwmod, @@ -382,8 +365,6 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2420_l4_core__i2c2, &omap2420_l3__iva, &omap2420_l3__dsp, - &omap2420_l4_wkup__timer1, - &omap2xxx_l4_core__timer2, &omap2xxx_l4_core__timer3, &omap2xxx_l4_core__timer4, &omap2xxx_l4_core__timer5, @@ -411,7 +392,6 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2xxx_l4_core__sham, &omap2xxx_l4_core__aes, &omap2420_l4_core__hdq1w, - &omap2420_l4_wkup__counter_32k, &omap2420_l3__gpmc, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -436,14 +436,6 @@ static struct omap_hwmod_ocp_if omap2430_l3__iva = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_timer1_hwmod, - .clk = "gpt1_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_wkup -> wd_timer2 */ static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { .master = &omap2xxx_l4_wkup_hwmod, @@ -548,14 +540,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = { .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, }; -/* l4_wkup -> 32ksync_counter */ -static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_counter_32k_hwmod, - .clk = "sync_32k_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_ocp_if omap2430_l3__gpmc = { .master = &omap2xxx_l3_main_hwmod, .slave = &omap2xxx_gpmc_hwmod, @@ -581,8 +565,6 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { &omap2xxx_l4_core__mcspi2, &omap2430_l4_core__mcspi3, &omap2430_l3__iva, - &omap2430_l4_wkup__timer1, - &omap2xxx_l4_core__timer2, &omap2xxx_l4_core__timer3, &omap2xxx_l4_core__timer4, &omap2xxx_l4_core__timer5, @@ -613,7 +595,6 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { &omap2xxx_l4_core__rng, &omap2xxx_l4_core__sham, &omap2xxx_l4_core__aes, - &omap2430_l4_wkup__counter_32k, &omap2430_l3__gpmc, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c @@ -95,14 +95,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_core -> timer2 */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_timer2_hwmod, - .clk = "gpt2_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_core -> timer3 */ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = { .master = &omap2xxx_l4_core_hwmod, diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -195,36 +195,6 @@ struct omap_hwmod omap2xxx_iva_hwmod = { .class = &iva_hwmod_class, }; -/* timer1 */ -struct omap_hwmod omap2xxx_timer1_hwmod = { - .name = "timer1", - .main_clk = "gpt1_fck", - .prcm = { - .omap2 = { - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, - }, - }, - .class = &omap2xxx_timer_hwmod_class, - .flags = HWMOD_SET_DEFAULT_CLOCKACT, -}; - -/* timer2 */ -struct omap_hwmod omap2xxx_timer2_hwmod = { - .name = "timer2", - .main_clk = "gpt2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, - }, - }, - .class = &omap2xxx_timer_hwmod_class, - .flags = HWMOD_SET_DEFAULT_CLOCKACT, -}; - /* timer3 */ struct omap_hwmod omap2xxx_timer3_hwmod = { .name = "timer3", @@ -595,23 +565,6 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = { .class = &omap2xxx_mcspi_class, }; -static struct omap_hwmod_class omap2xxx_counter_hwmod_class = { - .name = "counter", -}; - -struct omap_hwmod omap2xxx_counter_32k_hwmod = { - .name = "counter_32k", - .main_clk = "func_32k_ck", - .prcm = { - .omap2 = { - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT, - }, - }, - .class = &omap2xxx_counter_hwmod_class, -}; - /* gpmc */ struct omap_hwmod omap2xxx_gpmc_hwmod = { .name = "gpmc", diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -21,8 +21,6 @@ extern struct omap_hwmod omap2xxx_l4_core_hwmod; extern struct omap_hwmod omap2xxx_l4_wkup_hwmod; extern struct omap_hwmod omap2xxx_mpu_hwmod; extern struct omap_hwmod omap2xxx_iva_hwmod; -extern struct omap_hwmod omap2xxx_timer1_hwmod; -extern struct omap_hwmod omap2xxx_timer2_hwmod; extern struct omap_hwmod omap2xxx_timer3_hwmod; extern struct omap_hwmod omap2xxx_timer4_hwmod; extern struct omap_hwmod omap2xxx_timer5_hwmod; @@ -47,7 +45,6 @@ extern struct omap_hwmod omap2xxx_gpio3_hwmod; extern struct omap_hwmod omap2xxx_gpio4_hwmod; extern struct omap_hwmod omap2xxx_mcspi1_hwmod; extern struct omap_hwmod omap2xxx_mcspi2_hwmod; -extern struct omap_hwmod omap2xxx_counter_32k_hwmod; extern struct omap_hwmod omap2xxx_gpmc_hwmod; extern struct omap_hwmod omap2xxx_rng_hwmod; extern struct omap_hwmod omap2xxx_sham_hwmod;