From patchwork Thu Apr 30 08:06:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 201316 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CA1FC83009 for ; Thu, 30 Apr 2020 08:07:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DF34D21D79 for ; Thu, 30 Apr 2020 08:07:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588234056; bh=7Q6yx7BAcNGphXyMJ64Hizlmq02sPIkiGXe5IfpE7Z8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=0mj23VuDFXTzapietIPhjYG7rZcW8+QAIqK8ME9wVMsa0r8a+87VdZo5Rxy9JoWup 6f7zpbCafPnwcViFUC87Uw55YOsGA5/aefVhVoagFP4mwHZv3cUlMJRoiNtN5gsCFQ Z2PeFVWjZwXqsQ7xX5TafHJkZb/8XYAvIE4Bq0Qo= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726906AbgD3IHa (ORCPT ); Thu, 30 Apr 2020 04:07:30 -0400 Received: from mail.kernel.org ([198.145.29.99]:50848 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726871AbgD3IGn (ORCPT ); Thu, 30 Apr 2020 04:06:43 -0400 Received: from pali.im (pali.im [31.31.79.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E7E032192A; Thu, 30 Apr 2020 08:06:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588234003; bh=7Q6yx7BAcNGphXyMJ64Hizlmq02sPIkiGXe5IfpE7Z8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TtcL8ObD9ZShKGhTyCFi7x9xii5PxTKPG28YjJWpUDfsSnzJR2XRsB+IuWynuwZ5s FVggj8KBUEpbTwrAOvO0TrscLr5TJOODGSjQ8wfYnUasQD+lssLZCNSAjD00ONAR87 LuwCzjE1oAbDDpLUvris+w/1Bl6QBWsByjAMKaz8= Received: by pali.im (Postfix) id EF9F8AC9; Thu, 30 Apr 2020 10:06:40 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Thomas Petazzoni , Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Remi Pommarel , =?utf-8?q?Marek_Beh=C3=BAn?= , Tomasz Maciej Nowak , Xogium Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v4 02/12] PCI: aardvark: Don't blindly enable ASPM L0s and don't write to read-only register Date: Thu, 30 Apr 2020 10:06:15 +0200 Message-Id: <20200430080625.26070-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430080625.26070-1-pali@kernel.org> References: <20200430080625.26070-1-pali@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Trying to change Link Status register does not have any effect as this is a read-only register. Trying to overwrite bits for Negotiated Link Width does not make sense. In future proper change of link width can be done via Lane Count Select bits in PCIe Control 0 register. Trying to unconditionally enable ASPM L0s via ASPM Control bits in Link Control register is wrong. There should be at least some detection if endpoint supports L0s as isn't mandatory. Moreover ASPM Control bits in Link Control register are controlled by pcie/aspm.c code which sets it according to system ASPM settings, immediately after aardvark driver probes. So setting these bits by aardvark driver has no long running effect. Remove code which touches ASPM L0s bits from this driver and let kernel's ASPM implementation to set ASPM state properly. Some users are reporting issues that this code is problematic for some Intel wifi cards and removing it fixes them, see e.g.: https://bugzilla.kernel.org/show_bug.cgi?id=196339 If problems with Intel wifi cards occur even after this commit, then pcie/aspm.c code could be modified / hooked to not enable ASPM L0s state for affected problematic cards. Signed-off-by: Pali Rohár --- drivers/pci/controller/pci-aardvark.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index f9955b494267..74b90940a9d4 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -356,10 +356,6 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) advk_pcie_wait_for_link(pcie); - reg = PCIE_CORE_LINK_L0S_ENTRY | - (1 << PCIE_CORE_LINK_WIDTH_SHIFT); - advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); - reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | PCIE_CORE_CMD_IO_ACCESS_EN | From patchwork Thu Apr 30 08:06:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 201321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 797FEC8300A for ; Thu, 30 Apr 2020 08:06:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5741621D79 for ; Thu, 30 Apr 2020 08:06:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588234007; bh=TPnP78eeknSuUjBTOPPusY/VNyretW7NK7oJHlas4Mg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=rzd6LUG4t0UJCXgvLhs5GXtqMFaADIoa+sy1Vf3FW47650JmiHlemblWtvFgnH7yU 0n5HwxE21SaAoBNNE2S7MQNe3OedUxBtp8Hz2Uhhp+A17BXZ1F9ai2bkFd+/Sq+f2G V6W6tdeED5rGsanoetKLJ1ykP7ig+pKfNCWMa9qk= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726893AbgD3IGq (ORCPT ); Thu, 30 Apr 2020 04:06:46 -0400 Received: from mail.kernel.org ([198.145.29.99]:50972 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726885AbgD3IGo (ORCPT ); Thu, 30 Apr 2020 04:06:44 -0400 Received: from pali.im (pali.im [31.31.79.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E2B4021D7F; Thu, 30 Apr 2020 08:06:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588234004; bh=TPnP78eeknSuUjBTOPPusY/VNyretW7NK7oJHlas4Mg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oQl9HLUXC1bDoHro/6k7bDuGT4/va3vFcTfqQah95Ds91OcYxam5zgp1fztDwrhkm YJ4ZOkzb9jv7au88QTp6AAI3Lwaxagd4X77OheNUr1jA2SWwdIKT0EQAyEJk1kV0oH 9GX4b/LmwXHYNqEfExNiGskOZHCmd64cWndBZy2w= Received: by pali.im (Postfix) id 27FA27AD; Thu, 30 Apr 2020 10:06:42 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Thomas Petazzoni , Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Remi Pommarel , =?utf-8?q?Marek_Beh=C3=BAn?= , Tomasz Maciej Nowak , Xogium Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v4 03/12] PCI: of: Zero max-link-speed value is invalid Date: Thu, 30 Apr 2020 10:06:16 +0200 Message-Id: <20200430080625.26070-4-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430080625.26070-1-pali@kernel.org> References: <20200430080625.26070-1-pali@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Interpret zero value of max-link-speed property as invalid, as the device tree bindings documentation specifies. Signed-off-by: Pali Rohár --- drivers/pci/of.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 81ceeaa6f1d5..27839cd2459f 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -592,7 +592,7 @@ int of_pci_get_max_link_speed(struct device_node *node) u32 max_link_speed; if (of_property_read_u32(node, "max-link-speed", &max_link_speed) || - max_link_speed > 4) + max_link_speed == 0 || max_link_speed > 4) return -EINVAL; return max_link_speed; From patchwork Thu Apr 30 08:06:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 201317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09BE6C83001 for ; Thu, 30 Apr 2020 08:07:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DF7392186A for ; Thu, 30 Apr 2020 08:07:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588234047; bh=2uk4vuo8OceUNZZViPFMJEfPFWL6CEM3o4lkAfUrGCk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=lJbM6KxXQ0jFZb6NuziOXV+Ih3ekKkve5wj1IGOuQvVOp7GXK1kG8LijO+5hfvlsz 04CkF/ddzgQXkOGohm24jrjrjL6Xlp3F/J4fVcYtKqY6JOCZb/BEYVQ9ZzVs85iPck qdiGUEgHkNtn2ubwvluBWzwyKOfu7QnvQcaMZQmE= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726511AbgD3IHV (ORCPT ); Thu, 30 Apr 2020 04:07:21 -0400 Received: from mail.kernel.org ([198.145.29.99]:51072 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726906AbgD3IGr (ORCPT ); Thu, 30 Apr 2020 04:06:47 -0400 Received: from pali.im (pali.im [31.31.79.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 828F621974; Thu, 30 Apr 2020 08:06:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588234006; bh=2uk4vuo8OceUNZZViPFMJEfPFWL6CEM3o4lkAfUrGCk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IGaxNTLeS9yhWqzKvVjc2ESi38PzzhIq9ttgBe8qykNz2k7IXQkDDtofRL7t4MCS+ Yb27Ea/4lo1VxTzlvOJ+CUe6R/eVVALWyoOs0rArNa6S4w2aKrrf5sG5ZGhSy3Fqgk t4XoQn7wt4UR+deuF4t+R3w+5GMlssS8jokbZmHY= Received: by pali.im (Postfix) id ACD857AD; Thu, 30 Apr 2020 10:06:44 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Thomas Petazzoni , Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Remi Pommarel , =?utf-8?q?Marek_Beh=C3=BAn?= , Tomasz Maciej Nowak , Xogium Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v4 05/12] PCI: aardvark: Issue PERST via GPIO Date: Thu, 30 Apr 2020 10:06:18 +0200 Message-Id: <20200430080625.26070-6-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430080625.26070-1-pali@kernel.org> References: <20200430080625.26070-1-pali@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for issuing PERST via GPIO specified in 'reset-gpios' property (as described in PCI device tree bindings). Some buggy cards (e.g. Compex WLE900VX or WLE1216) are not detected after reboot when PERST is not issued during driver initialization. If bootloader already enabled link training then issuing PERST has no effect for some buggy cards (e.g. Compex WLE900VX) and these cards are not detected. We therefore clear the LINK_TRAINING_EN register before. It was observed that Compex WLE900VX card needs to be in PERST reset for at least 10ms if bootloader enabled link training. Tested on Turris MOX. Signed-off-by: Pali Rohár --- drivers/pci/controller/pci-aardvark.c | 43 ++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index e202f954eb84..2ecc79c03ade 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -18,6 +19,7 @@ #include #include #include +#include #include #include "../pci.h" @@ -204,6 +206,7 @@ struct advk_pcie { int root_bus_nr; int link_gen; struct pci_bridge_emul bridge; + struct gpio_desc *reset_gpio; }; static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) @@ -330,10 +333,31 @@ static void advk_pcie_train_link(struct advk_pcie *pcie) dev_err(dev, "link never came up\n"); } +static void advk_pcie_issue_perst(struct advk_pcie *pcie) +{ + u32 reg; + + if (!pcie->reset_gpio) + return; + + /* PERST does not work for some cards when link training is enabled */ + reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); + reg &= ~LINK_TRAINING_EN; + advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); + + /* 10ms delay is needed for some cards */ + dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); + gpiod_set_value_cansleep(pcie->reset_gpio, 1); + usleep_range(10000, 11000); + gpiod_set_value_cansleep(pcie->reset_gpio, 0); +} + static void advk_pcie_setup_hw(struct advk_pcie *pcie) { u32 reg; + advk_pcie_issue_perst(pcie); + /* Set to Direct mode */ reg = advk_readl(pcie, CTRL_CONFIG_REG); reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); @@ -406,7 +430,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) /* * PERST# signal could have been asserted by pinctrl subsystem before - * probe() callback has been called, making the endpoint going into + * probe() callback has been called or issued explicitly by reset gpio + * function advk_pcie_issue_perst(), making the endpoint going into * fundamental reset. As required by PCI Express spec a delay for at * least 100ms after such a reset before link training is needed. */ @@ -1046,6 +1071,22 @@ static int advk_pcie_probe(struct platform_device *pdev) } pcie->root_bus_nr = bus->start; + pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, + "reset-gpios", 0, + GPIOD_OUT_LOW, + "pcie1-reset"); + ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); + if (ret) { + if (ret == -ENOENT) { + pcie->reset_gpio = NULL; + } else { + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get reset-gpio: %i\n", + ret); + return ret; + } + } + ret = of_pci_get_max_link_speed(dev->of_node); if (ret <= 0 || ret > 3) pcie->link_gen = 3; From patchwork Thu Apr 30 08:06:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 201318 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8D08C83006 for ; Thu, 30 Apr 2020 08:07:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A6E422186A for ; Thu, 30 Apr 2020 08:07:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588234033; bh=kwMHrQRCUR0Xnjbf55cLJqGOENIDvbYB5y5ST/WRl6w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=JBw7pN1CxkTGsAEllRpgbpgrW/j7pzrKBa1lmAu0FVsrshVxh/9STuR80VmYEfp6K 24MMWaATjEkLzLKKh62ZI3yfNXttuSUr9ZehzSV1Tc67ZL2PU3Lch6m/dzc4KXBmGI aDY/smbLbC1uLPzR1SXZaitgoZAedfJZHs1MMIr0= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726961AbgD3IHM (ORCPT ); Thu, 30 Apr 2020 04:07:12 -0400 Received: from mail.kernel.org ([198.145.29.99]:51226 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726910AbgD3IGt (ORCPT ); Thu, 30 Apr 2020 04:06:49 -0400 Received: from pali.im (pali.im [31.31.79.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A47D72186A; Thu, 30 Apr 2020 08:06:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588234008; bh=kwMHrQRCUR0Xnjbf55cLJqGOENIDvbYB5y5ST/WRl6w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cn1xEq0YyV3o+vE/Xuar5Hm8tFbZ5uBt7y+LbKe1qe6T9tn95ytJUULutb3jxGAEm CVnVs+VQNxhGdMf8OeDZFH9ozwQoJS6m2W37Ly3vsP+QHNE1joV2Ja5bX8YWuEXjKs M7zDutva9fee7ChAlYVG33bcbpSm2be/Nn372Xgs= Received: by pali.im (Postfix) id DF46B7AD; Thu, 30 Apr 2020 10:06:46 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Thomas Petazzoni , Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Remi Pommarel , =?utf-8?q?Marek_Beh=C3=BAn?= , Tomasz Maciej Nowak , Xogium Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v4 07/12] PCI: aardvark: Add PHY support Date: Thu, 30 Apr 2020 10:06:20 +0200 Message-Id: <20200430080625.26070-8-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430080625.26070-1-pali@kernel.org> References: <20200430080625.26070-1-pali@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Marek Behún With recent proposed changes for U-Boot it is possible that bootloader won't initialize the PHY for this controller (currently the PHY is initialized regardless whether PCI is used in U-Boot, but with these proposed changes the PHY is initialized only on request). Since the mvebu-a3700-comphy driver by Miquèl Raynal supports enabling PCIe PHY, and since Linux' functionality should be independent on what bootloader did, add code for enabling generic PHY if found in device OF node. The mvebu-a3700-comphy driver does PHY powering via SMC calls to ARM Trusted Firmware. The corresponding code in ARM Trusted Firmware skips one register write which U-Boot does not: step 7 ("Enable TX"), see [1]. Instead ARM Trusted Firmware expects PCIe driver to do this step, probably because the register is in PCIe controller address space, instead of PHY address space. We therefore add this step into the advk_pcie_setup_hw function. [1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/drivers/marvell/comphy/phy-comphy-3700.c?h=v2.3-rc2#n836 Signed-off-by: Marek Behún Cc: Miquèl Raynal --- drivers/pci/controller/pci-aardvark.c | 69 +++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 8332c71d69fa..053ae6c19a3d 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -104,6 +105,8 @@ #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6) #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10) +#define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14) +#define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1) #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30) #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40) #define PCIE_MSG_PM_PME_MASK BIT(7) @@ -207,6 +210,7 @@ struct advk_pcie { int link_gen; struct pci_bridge_emul bridge; struct gpio_desc *reset_gpio; + struct phy *phy; }; static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) @@ -358,6 +362,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) advk_pcie_issue_perst(pcie); + /* Enable TX */ + reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); + reg |= PCIE_CORE_REF_CLK_TX_ENABLE; + advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG); + /* Set to Direct mode */ reg = advk_readl(pcie, CTRL_CONFIG_REG); reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); @@ -1041,6 +1050,62 @@ static irqreturn_t advk_pcie_irq_handler(int irq, void *arg) return IRQ_HANDLED; } +static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie) +{ + phy_power_off(pcie->phy); + phy_exit(pcie->phy); +} + +static int advk_pcie_enable_phy(struct advk_pcie *pcie) +{ + int ret; + + if (!pcie->phy) + return 0; + + ret = phy_init(pcie->phy); + if (ret) + return ret; + + ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); + if (ret) { + phy_exit(pcie->phy); + return ret; + } + + ret = phy_power_on(pcie->phy); + if (ret) { + phy_exit(pcie->phy); + return ret; + } + + return 0; +} + +static int advk_pcie_setup_phy(struct advk_pcie *pcie) +{ + struct device *dev = &pcie->pdev->dev; + struct device_node *node = dev->of_node; + int ret = 0; + + pcie->phy = devm_of_phy_get(dev, node, NULL); + if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) + return PTR_ERR(pcie->phy); + + /* Old bindings miss the PHY handle */ + if (IS_ERR(pcie->phy)) { + dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); + pcie->phy = NULL; + return 0; + } + + ret = advk_pcie_enable_phy(pcie); + if (ret) + dev_err(dev, "Failed to initialize PHY (%d)\n", ret); + + return ret; +} + static int advk_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1100,6 +1165,10 @@ static int advk_pcie_probe(struct platform_device *pdev) else pcie->link_gen = ret; + ret = advk_pcie_setup_phy(pcie); + if (ret) + return ret; + advk_pcie_setup_hw(pcie); advk_sw_pci_bridge_init(pcie); From patchwork Thu Apr 30 08:06:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 201319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74571C8300A for ; Thu, 30 Apr 2020 08:07:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4E6042073E for ; Thu, 30 Apr 2020 08:07:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588234032; bh=dkqvXTL9+Vx5TfVq+Qm+IxU+y+qPkG/crH1tOtt/POg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=P5tLahf6f/sxvwadrsUREIW7/vLD0/+4epNPQbMV2f/pWYMGSJFAnjvHQvbwYlUOh XGkTl3//Q/PAw/mNoA4axcD+3sFsEc0S4twyhUuYdYz168q4/NKuSrSsmWvTHPvUjf 90Tq393qBT/nCLxJQinMzFAPof32vxZzGiKvt1qA= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726849AbgD3IHC (ORCPT ); Thu, 30 Apr 2020 04:07:02 -0400 Received: from mail.kernel.org ([198.145.29.99]:51430 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726930AbgD3IGx (ORCPT ); Thu, 30 Apr 2020 04:06:53 -0400 Received: from pali.im (pali.im [31.31.79.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id F2BDC21D7F; Thu, 30 Apr 2020 08:06:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588234013; bh=dkqvXTL9+Vx5TfVq+Qm+IxU+y+qPkG/crH1tOtt/POg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=zTQfyTVepnOQCOx20RRVjLZSraoxjtBWeUawYEh2WtjnmvgO+3f2FkMIdszbGRf/B eukhcoPnJgJVe/42lJAEoM4WHCwGvoIfNxkVQYy85AiCO59cegPyWGWqIdv6uPN3Pv aEzwptwd0ZDfpN01UsxKiBAEzzzdaoobUFshhXFE= Received: by pali.im (Postfix) id 357297AD; Thu, 30 Apr 2020 10:06:51 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Thomas Petazzoni , Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Remi Pommarel , =?utf-8?q?Marek_Beh=C3=BAn?= , Tomasz Maciej Nowak , Xogium Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v4 11/12] arm64: dts: marvell: armada-37xx: Move PCIe comphy handle property Date: Thu, 30 Apr 2020 10:06:24 +0200 Message-Id: <20200430080625.26070-12-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430080625.26070-1-pali@kernel.org> References: <20200430080625.26070-1-pali@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Marek Behún Move the comphy handle property of the PCIe node from board specific device tree files (EspressoBin and Turris Mox) to the generic armada-37xx.dtsi. This is correct since this is the only possible PCIe PHY configuration on Armada 37xx, so when PCIe is enabled on any board, this handle is correct. Signed-off-by: Marek Behún --- arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 1 - arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 1 - arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 + 3 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi index c92ad664cb0e..b97218c72727 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi @@ -44,7 +44,6 @@ /* J9 */ &pcie0 { status = "okay"; - phys = <&comphy1 0>; pinctrl-names = "default"; pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index e496bd9d4737..15c1cf5c5b69 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -134,7 +134,6 @@ status = "okay"; max-link-speed = <2>; reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; - phys = <&comphy1 0>; /* enabled by U-Boot if PCIe module is present */ status = "disabled"; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 7909c146eabf..5aaad64a793d 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -493,6 +493,7 @@ <0 0 0 2 &pcie_intc 1>, <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; + phys = <&comphy1 0>; pcie_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; From patchwork Thu Apr 30 08:06:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 201320 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 028A0C83001 for ; Thu, 30 Apr 2020 08:07:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CA95521D79 for ; Thu, 30 Apr 2020 08:07:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588234021; bh=kuyAXwOATAjORZINANy8r5DfKQd5TrKERHhwlhi4j8U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=KoZSKs0lJvGqlyWvWuIbm6Hn7KEg9Cmt4cfedFaB4gI4JvILfC4RmUVr1DKJSrdZK C1ZEZDILl8MFSR/wOqteO5BbEng68/BRWUyG/iBqx5lYwvLEgkW2sSgo0XyahW4huZ 6jH2sldCN2tqHePK/J9MpecWvUT/o4LmHYTCTZ3o= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727061AbgD3IG4 (ORCPT ); Thu, 30 Apr 2020 04:06:56 -0400 Received: from mail.kernel.org ([198.145.29.99]:51494 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727047AbgD3IGy (ORCPT ); Thu, 30 Apr 2020 04:06:54 -0400 Received: from pali.im (pali.im [31.31.79.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 34D4321D91; Thu, 30 Apr 2020 08:06:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588234014; bh=kuyAXwOATAjORZINANy8r5DfKQd5TrKERHhwlhi4j8U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QzprLcgqDEonxaFzNfeojY+EjQDpkCWBj/1wxHIYvSOMaECE5CZRQH7oL6s6aJbSJ iEuNcNWSC+6q+z2UuQxnrNRupWKQBPWG2d15oax68vthdVOIS38AyRVelouP/a4ekg YsYTXeLW3Q1RrACGnl7BY6O9bNvRXsDyKukmDDUM= Received: by pali.im (Postfix) id 60A31A19; Thu, 30 Apr 2020 10:06:52 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Thomas Petazzoni , Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Remi Pommarel , =?utf-8?q?Marek_Beh=C3=BAn?= , Tomasz Maciej Nowak , Xogium Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v4 12/12] arm64: dts: marvell: armada-37xx: Move PCIe max-link-speed property Date: Thu, 30 Apr 2020 10:06:25 +0200 Message-Id: <20200430080625.26070-13-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430080625.26070-1-pali@kernel.org> References: <20200430080625.26070-1-pali@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Move the max-link-speed property of the PCIe node from board specific device tree files to the generic armada-37xx.dtsi. Armada 37xx supports only PCIe gen2 speed so max-link-speed property should be in the genetic armada-37xx.dtsi file. Signed-off-by: Pali Rohár --- arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 1 - arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index 15c1cf5c5b69..4cc735899c5d 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -132,7 +132,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; status = "okay"; - max-link-speed = <2>; reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; /* enabled by U-Boot if PCIe module is present */ diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 5aaad64a793d..2bbc69b4dc99 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -493,6 +493,7 @@ <0 0 0 2 &pcie_intc 1>, <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; + max-link-speed = <2>; phys = <&comphy1 0>; pcie_intc: interrupt-controller { interrupt-controller;