From patchwork Thu May 14 14:59:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 200557 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6FE5C433E1 for ; Thu, 14 May 2020 15:00:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B197F205CB for ; Thu, 14 May 2020 15:00:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="X/Wl4Vbp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727924AbgENPAI (ORCPT ); Thu, 14 May 2020 11:00:08 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:42036 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726146AbgENPAH (ORCPT ); Thu, 14 May 2020 11:00:07 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 04EExqYf028904; Thu, 14 May 2020 09:59:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1589468392; bh=Z+gfjunEdb+MDsFcXFEi3ESnDkoKrmf88fLI5DaHYFs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=X/Wl4VbpWfLMxOmffnMC5XzbbmI1jXt6otRkFudTKOj+MoTVRJczt1q1ijiz8PbYm LG0FXCXwcldlYOUogAFwDHXMwaVShOt8dfV//CH1ShO9R8K11L48jN6+fktEyKe7zR 11aOUUpMZGthBMF3SdVClabcjJccvC3xgf857vgs= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 04EExqUd117212 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 14 May 2020 09:59:52 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 14 May 2020 09:59:51 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 14 May 2020 09:59:51 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04EExgAj019279; Thu, 14 May 2020 09:59:47 -0500 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Arnd Bergmann , Jon Mason , Dave Jiang , Allen Hubbe , Tom Joseph , Bjorn Helgaas , Rob Herring CC: Greg Kroah-Hartman , Jonathan Corbet , , , , , , Kishon Vijay Abraham I Subject: [PATCH 01/19] dt-bindings: PCI: Endpoint: Add DT bindings for PCI EPF NTB Device Date: Thu, 14 May 2020 20:29:09 +0530 Message-ID: <20200514145927.17555-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200514145927.17555-1-kishon@ti.com> References: <20200514145927.17555-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree schema for PCI endpoint function bus to which endpoint function devices should be attached. Then add device tree schema for PCI endpoint function device to include bindings thats generic to all endpoint functions. Finally add device tree schema for PCI endpoint NTB function device by including the generic device tree schema for PCIe endpoint function. Signed-off-by: Kishon Vijay Abraham I --- .../bindings/pci/endpoint/pci-epf-bus.yaml | 42 +++++++++++ .../bindings/pci/endpoint/pci-epf-device.yaml | 69 +++++++++++++++++++ .../bindings/pci/endpoint/pci-epf-ntb.yaml | 68 ++++++++++++++++++ 3 files changed, 179 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/endpoint/pci-epf-bus.yaml create mode 100644 Documentation/devicetree/bindings/pci/endpoint/pci-epf-device.yaml create mode 100644 Documentation/devicetree/bindings/pci/endpoint/pci-epf-ntb.yaml diff --git a/Documentation/devicetree/bindings/pci/endpoint/pci-epf-bus.yaml b/Documentation/devicetree/bindings/pci/endpoint/pci-epf-bus.yaml new file mode 100644 index 000000000000..1c504f2e85e4 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/endpoint/pci-epf-bus.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/endpoint/pci-epf-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCI Endpoint Function Bus + +maintainers: + - Kishon Vijay Abraham I + +properties: + compatible: + const: pci-epf-bus + +patternProperties: + "^func@[0-9a-f]+$": + type: object + description: | + PCI Endpoint Function Bus node should have subnodes for each of + the implemented endpoint function. It should follow the bindings + specified for endpoint function in + Documentation/devicetree/bindings/pci/endpoint/ + +examples: + - | + epf_bus { + compatible = "pci-epf-bus"; + + func@0 { + compatible = "pci-epf-ntb"; + epcs = <&pcie0_ep>, <&pcie1_ep>; + epc-names = "primary", "secondary"; + reg = <0>; + epf,vendor-id = /bits/ 16 <0x104c>; + epf,device-id = /bits/ 16 <0xb00d>; + num-mws = <4>; + mws-size = <0x0 0x100000>, <0x0 0x100000>, <0x0 0x100000>, <0x0 0x100000>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/endpoint/pci-epf-device.yaml b/Documentation/devicetree/bindings/pci/endpoint/pci-epf-device.yaml new file mode 100644 index 000000000000..cee72864c8ca --- /dev/null +++ b/Documentation/devicetree/bindings/pci/endpoint/pci-epf-device.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/endpoint/pci-epf-device.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCI Endpoint Function Device + +maintainers: + - Kishon Vijay Abraham I + +properties: + compatible: + const: pci-epf-bus + +properties: + $nodename: + pattern: "^func@" + + epcs: + description: + Phandle to the endpoint controller device. Should have "2" entries for + NTB endpoint function and "1" entry for others. + minItems: 1 + maxItems: 2 + + epc-names: + description: + Must contain an entry for each entry in "epcs" when "epcs" have more than + one entry. + + reg: + maxItems: 0 + description: Must contain the index number of the function. + + epf,vendor-id: + description: + The PCI vendor ID + allOf: + - $ref: /schemas/types.yaml#/definitions/uint16 + + epf,device-id: + description: + The PCI device ID + allOf: + - $ref: /schemas/types.yaml#/definitions/uint16 + + epf,baseclass-code: + description: Code to classify the type of operation the function performs + allOf: + - $ref: /schemas/types.yaml#/definitions/uint8 + + epf,subclass-code: + description: + Specifies a base class sub-class, which identifies more specifically the + operation of the Function + allOf: + - $ref: /schemas/types.yaml#/definitions/uint8 + + epf,subsys-vendor-id: + description: Code to identify vendor of the add-in card or subsystem + allOf: + - $ref: /schemas/types.yaml#/definitions/uint16 + + epf,subsys-id: + description: Code to specify an id that is specific to a vendor + allOf: + - $ref: /schemas/types.yaml#/definitions/uint16 diff --git a/Documentation/devicetree/bindings/pci/endpoint/pci-epf-ntb.yaml b/Documentation/devicetree/bindings/pci/endpoint/pci-epf-ntb.yaml new file mode 100644 index 000000000000..92c2e522b9e5 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/endpoint/pci-epf-ntb.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/endpoint/pci-epf-ntb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCI Endpoint NTB Function Device + +maintainers: + - Kishon Vijay Abraham I + +allOf: + - $ref: "pci-epf-device.yaml#" + +properties: + compatible: + const: pci-epf-ntb + + epcs: + minItems: 2 + maxItems: 2 + + epc-names: + items: + - const: primary + - const: secondary + + num-mws: + description: + Specify the number of memory windows + allOf: + - $ref: /schemas/types.yaml#/definitions/uint8 + minimum: 1 + maximum: 4 + + mws-size: + description: + List of 'num-mws' entries containing size of each memory window. + minItems: 1 + maxItems: 4 + +required: + - compatible + - epcs + - epc-names + - epf,vendor-id + - epf,device-id + - num-mws + - mws-size + +examples: + - | + epf_bus { + compatible = "pci-epf-bus"; + + func@0 { + compatible = "pci-epf-ntb"; + reg = <0>; + epcs = <&pcie0_ep>, <&pcie1_ep>; + epc-names = "primary", "secondary"; + epf,vendor-id = /bits/ 16 <0x104c>; + epf,device-id = /bits/ 16 <0xb00d>; + num-mws = <4>; + mws-size = <0x0 0x100000>, <0x0 0x100000>, <0x0 0x100000>, <0x0 0x100000>; + }; + }; +... From patchwork Thu May 14 14:59:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 200556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D4B6C433E0 for ; Thu, 14 May 2020 15:00:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 78F71205CB for ; Thu, 14 May 2020 15:00:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="MkKcHfOX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727992AbgENPAW (ORCPT ); Thu, 14 May 2020 11:00:22 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:42116 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726146AbgENPAV (ORCPT ); Thu, 14 May 2020 11:00:21 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 04EF06Rd029135; Thu, 14 May 2020 10:00:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1589468406; bh=oPxuXqtF223OER+bcyGCz8Cb674T5LZwKws+2r6ddns=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MkKcHfOX0rkPf/0CruxXMcU/KDNgv7PfzNXoxweAGS0wa6ecFAEvPpP/K37TmmSmb Muc1KvKYi7OBEN/wPFkhaFxwWdgNqM3rPHdKkYoVv365sZNi2HVPqPogyD5qLel9IP TIt80aFUFEPdMTPyhdw1PlkTnDLp9CTxsgTYgFoM= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 04EF05qA117768 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 14 May 2020 10:00:06 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 14 May 2020 10:00:06 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 14 May 2020 10:00:05 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04EExgAm019279; Thu, 14 May 2020 10:00:01 -0500 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Arnd Bergmann , Jon Mason , Dave Jiang , Allen Hubbe , Tom Joseph , Bjorn Helgaas , Rob Herring CC: Greg Kroah-Hartman , Jonathan Corbet , , , , , , Kishon Vijay Abraham I Subject: [PATCH 04/19] PCI: endpoint: Add API to create EPF device from device tree Date: Thu, 14 May 2020 20:29:12 +0530 Message-ID: <20200514145927.17555-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200514145927.17555-1-kishon@ti.com> References: <20200514145927.17555-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add API to create EPF device from device tree and the device managed interface corresponding to it. This is added in order to define an endpoint function completely from device tree. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-epf-core.c | 68 +++++++++++++++++++++++++++++ include/linux/pci-epf.h | 6 +++ 2 files changed, 74 insertions(+) diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index 244e00f48c5c..cb6c7b886325 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -280,6 +280,73 @@ struct pci_epf *pci_epf_create(const char *name) } EXPORT_SYMBOL_GPL(pci_epf_create); +/** + * pci_epf_of_create() - create a new PCI EPF device from device tree node + * @node: the device node of the PCI EPF device. + * + * Invoke to create a new PCI EPF device by providing a device tree node + * with compatible property. + */ +struct pci_epf *pci_epf_of_create(struct device_node *node) +{ + struct pci_epf *epf; + const char *compat; + int ret; + + of_node_get(node); + + ret = of_property_read_string(node, "compatible", &compat); + if (ret) { + of_node_put(node); + return ERR_PTR(ret); + } + + epf = pci_epf_create(compat); + if (!IS_ERR(epf)) + epf->node = node; + + return epf; +} +EXPORT_SYMBOL_GPL(pci_epf_of_create); + +static void devm_epf_release(struct device *dev, void *res) +{ + struct pci_epf *epf = *(struct pci_epf **)res; + + pci_epf_destroy(epf); +} + +/** + * devm_pci_epf_of_create() - create a new PCI EPF device from device tree node + * @dev: device that is creating the new EPF + * @node: the device node of the PCI EPF device. + * + * Invoke to create a new PCI EPF device by providing a device tree node with + * compatible property. While at that, it also associates the device with the + * EPF using devres. On driver detach, release function is invoked on the devres + * data, where devres data is freed. + */ +struct pci_epf *devm_pci_epf_of_create(struct device *dev, + struct device_node *node) +{ + struct pci_epf **ptr, *epf; + + ptr = devres_alloc(devm_epf_release, sizeof(*ptr), GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + epf = pci_epf_of_create(node); + if (!IS_ERR(epf)) { + *ptr = epf; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + + return epf; +} +EXPORT_SYMBOL_GPL(devm_pci_epf_of_create); + const struct pci_epf_device_id * pci_epf_match_device(const struct pci_epf_device_id *id, struct pci_epf *epf) { @@ -300,6 +367,7 @@ static void pci_epf_dev_release(struct device *dev) { struct pci_epf *epf = to_pci_epf(dev); + of_node_put(epf->node); kfree(epf->name); kfree(epf); } diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index 6644ff3b0702..8fb77ab1968f 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -11,6 +11,7 @@ #include #include +#include #include struct pci_epf; @@ -108,6 +109,7 @@ struct pci_epf_bar { /** * struct pci_epf - represents the PCI EPF device * @dev: the PCI EPF device + * @node: the device tree node of the PCI EPF device * @name: the name of the PCI EPF device * @header: represents standard configuration header * @bar: represents the BAR of EPF device @@ -121,6 +123,7 @@ struct pci_epf_bar { */ struct pci_epf { struct device dev; + struct device_node *node; const char *name; struct pci_epf_header *header; struct pci_epf_bar bar[6]; @@ -167,6 +170,9 @@ static inline void *epf_get_drvdata(struct pci_epf *epf) const struct pci_epf_device_id * pci_epf_match_device(const struct pci_epf_device_id *id, struct pci_epf *epf); struct pci_epf *pci_epf_create(const char *name); +struct pci_epf *pci_epf_of_create(struct device_node *node); +struct pci_epf *devm_pci_epf_of_create(struct device *dev, + struct device_node *node); void pci_epf_destroy(struct pci_epf *epf); int __pci_epf_register_driver(struct pci_epf_driver *driver, struct module *owner); From patchwork Thu May 14 14:59:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 200550 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AA4FC433E2 for ; Thu, 14 May 2020 15:02:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E03C62074A for ; Thu, 14 May 2020 15:02:24 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Thu, 14 May 2020 10:00:16 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 14 May 2020 10:00:15 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 14 May 2020 10:00:15 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04EExgAo019279; Thu, 14 May 2020 10:00:11 -0500 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Arnd Bergmann , Jon Mason , Dave Jiang , Allen Hubbe , Tom Joseph , Bjorn Helgaas , Rob Herring CC: Greg Kroah-Hartman , Jonathan Corbet , , , , , , Kishon Vijay Abraham I Subject: [PATCH 06/19] PCI: endpoint: Make *_get_first_free_bar() take into account 64 bit BAR Date: Thu, 14 May 2020 20:29:14 +0530 Message-ID: <20200514145927.17555-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200514145927.17555-1-kishon@ti.com> References: <20200514145927.17555-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org pci_epc_get_first_free_bar() uses only "reserved_bar" member in epc_features to get the first unreserved BAR. However if the reserved BAR is also a 64-bit BAR, then the next BAR shouldn't be returned (since 64-bit BAR uses two BARs). Make pci_epc_get_first_free_bar() take into account 64 bit BAR while returning the first free unreserved BAR. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-epc-core.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 177a3fc1a0dd..49bffa2349c5 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -153,12 +153,20 @@ EXPORT_SYMBOL_GPL(of_pci_epc_get_by_name); unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features) { - int free_bar; + unsigned long free_bar; if (!epc_features) return 0; - free_bar = ffz(epc_features->reserved_bar); + /* Find if the reserved BAR is also a 64-bit BAR */ + free_bar = epc_features->reserved_bar & epc_features->bar_fixed_64bit; + + /* Set the adjacent bit if the reserved BAR is also a 64-bit BAR */ + free_bar <<= 1; + free_bar |= epc_features->reserved_bar; + + /* Now find the free BAR */ + free_bar = ffz(free_bar); if (free_bar > 5) return 0; From patchwork Thu May 14 14:59:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 200549 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC09EC433E0 for ; Thu, 14 May 2020 15:02:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B7C55205CB for ; Thu, 14 May 2020 15:02:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Zto/dwKC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728060AbgENPBI (ORCPT ); Thu, 14 May 2020 11:01:08 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:47208 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726726AbgENPBI (ORCPT ); Thu, 14 May 2020 11:01:08 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 04EF0L0x000397; Thu, 14 May 2020 10:00:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1589468421; bh=y89RQ0LlIPyIbyZ2I5CO0BLv3OcOvgocP9HIgT4BsH4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Zto/dwKCRWyoy0FiXsccjGH2DQnLJJ4JxrKBVvVdI6hVOnvsvX1Nz6F/HWgjXzSso 95VSJgxfc9sYo5d9DJsTsaDhJqkapIZq4SwSZU9hkk/M94x5+udYsFKc+YuLHXnXkr Q0yV28kAukxPTOnb3QNmup6bD8I7OnUt3Wjra+5s= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04EF0Kr3128969; Thu, 14 May 2020 10:00:20 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 14 May 2020 10:00:20 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 14 May 2020 10:00:20 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04EExgAp019279; Thu, 14 May 2020 10:00:16 -0500 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Arnd Bergmann , Jon Mason , Dave Jiang , Allen Hubbe , Tom Joseph , Bjorn Helgaas , Rob Herring CC: Greg Kroah-Hartman , Jonathan Corbet , , , , , , Kishon Vijay Abraham I Subject: [PATCH 07/19] PCI: endpoint: Add helper API to get the 'next' unreserved BAR Date: Thu, 14 May 2020 20:29:15 +0530 Message-ID: <20200514145927.17555-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200514145927.17555-1-kishon@ti.com> References: <20200514145927.17555-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add an API to get the next unreserved BAR starting from a given BAR number that can be used by the endpoint function. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-epc-core.c | 26 ++++++++++++++++++++++---- include/linux/pci-epc.h | 2 ++ 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 49bffa2349c5..85e542aae617 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -147,17 +147,36 @@ EXPORT_SYMBOL_GPL(of_pci_epc_get_by_name); * pci_epc_get_first_free_bar() - helper to get first unreserved BAR * @epc_features: pci_epc_features structure that holds the reserved bar bitmap * - * Invoke to get the first unreserved BAR that can be used for endpoint + * Invoke to get the first unreserved BAR that can be used by the endpoint * function. For any incorrect value in reserved_bar return '0'. */ unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features) +{ + return pci_epc_get_next_free_bar(epc_features, BAR_0); +} +EXPORT_SYMBOL_GPL(pci_epc_get_first_free_bar); + +/** + * pci_epc_get_next_free_bar() - helper to get unreserved BAR starting from @bar + * @epc_features: pci_epc_features structure that holds the reserved bar bitmap + * @bar: the starting BAR number from where unreserved BAR should be searched + * + * Invoke to get the next unreserved BAR starting from @bar that can be used + * for endpoint function. For any incorrect value in reserved_bar return '0'. + */ +unsigned int pci_epc_get_next_free_bar(const struct pci_epc_features + *epc_features, enum pci_barno bar) { unsigned long free_bar; if (!epc_features) return 0; + /* If 'bar - 1' is a 64-bit BAR, move to the next BAR */ + if ((epc_features->bar_fixed_64bit << 1) & 1 << bar) + bar++; + /* Find if the reserved BAR is also a 64-bit BAR */ free_bar = epc_features->reserved_bar & epc_features->bar_fixed_64bit; @@ -165,14 +184,13 @@ unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features free_bar <<= 1; free_bar |= epc_features->reserved_bar; - /* Now find the free BAR */ - free_bar = ffz(free_bar); + free_bar = find_next_zero_bit(&free_bar, 6, bar); if (free_bar > 5) return 0; return free_bar; } -EXPORT_SYMBOL_GPL(pci_epc_get_first_free_bar); +EXPORT_SYMBOL_GPL(pci_epc_get_next_free_bar); /** * pci_epc_get_features() - get the features supported by EPC diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index dd3c2d566c3d..68f7c0d81442 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -203,6 +203,8 @@ const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc, u8 func_no); unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features); +unsigned int pci_epc_get_next_free_bar(const struct pci_epc_features + *epc_features, enum pci_barno bar); struct pci_epc *pci_epc_get(const char *epc_name); void pci_epc_put(struct pci_epc *epc); From patchwork Thu May 14 14:59:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 200554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF52CC433DF for ; Thu, 14 May 2020 15:01:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8E65A20657 for ; Thu, 14 May 2020 15:01:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Ld4YaDO/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728270AbgENPBZ (ORCPT ); Thu, 14 May 2020 11:01:25 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:42282 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727123AbgENPBY (ORCPT ); Thu, 14 May 2020 11:01:24 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 04EF0Z7o029269; Thu, 14 May 2020 10:00:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1589468435; bh=3kot24pT8I54Qo+jrpEa45lAzMIAEzTZmm1JUxN+Bjc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Ld4YaDO/ufrRparGyNG/IyBUN/95uQw4hpuKaFIpoG1jGzOCx133M/kZcsqCyV+kj QgguIenZsF00Rg/954KX15zsVccuq9ZfIIUukgN75a4SKjMerpjsI21OcQ0gQVtbRj B5kWIsmUtKeAJNKrOX6eTKFGISOtv/aCrlkbcrMg= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04EF0ZGx129334; Thu, 14 May 2020 10:00:35 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 14 May 2020 10:00:34 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 14 May 2020 10:00:34 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04EExgAs019279; Thu, 14 May 2020 10:00:30 -0500 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Arnd Bergmann , Jon Mason , Dave Jiang , Allen Hubbe , Tom Joseph , Bjorn Helgaas , Rob Herring CC: Greg Kroah-Hartman , Jonathan Corbet , , , , , , Kishon Vijay Abraham I Subject: [PATCH 10/19] PCI: endpoint: Make pci_epf_driver ops optional Date: Thu, 14 May 2020 20:29:18 +0530 Message-ID: <20200514145927.17555-11-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200514145927.17555-1-kishon@ti.com> References: <20200514145927.17555-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org pci_epf_driver had two ops for bind and unbind which will be invoked when an endpoint controller is bound to an endpoint function (using configfs). Now that endpoint core has support to define an endpoint function using device tree alone, the bind and unbind ops can be optional. Make pci_epf_driver ops optional here. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-epf-core.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index f9ba2e8d4a99..f463eedcc3ad 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -201,11 +201,9 @@ int __pci_epf_register_driver(struct pci_epf_driver *driver, { int ret; - if (!driver->ops) - return -EINVAL; - - if (!driver->ops->bind || !driver->ops->unbind) - return -EINVAL; + if (!driver->ops || !driver->ops->bind || !driver->ops->unbind) + pr_debug("%s: Supports only pci_epf device created using DT\n", + driver->driver.name); driver->driver.bus = &pci_epf_bus_type; driver->driver.owner = owner; From patchwork Thu May 14 14:59:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 200555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18DCDC433E0 for ; Thu, 14 May 2020 15:01:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EA2B920643 for ; Thu, 14 May 2020 15:01:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="IYJF5ySR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728181AbgENPBR (ORCPT ); Thu, 14 May 2020 11:01:17 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:36016 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728176AbgENPBQ (ORCPT ); Thu, 14 May 2020 11:01:16 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 04EF0e7k102730; Thu, 14 May 2020 10:00:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1589468440; bh=JTb7YgvROaherg13FvnZRBqflcI4vuUymmflrjhSi4Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IYJF5ySRCYhEZz3qmkRG1jJ0EPpNDP/pEirpobrLA4HeVqY2SxI7O7Auss+m00L4B pgR4AeEL2dWRpZvZSwTLRo/UtZTNbH1GOT/FXLnWLIVPi18G34Io5EnNW4sgcFPjeq nPw4HSTnl2AJVgMQuJ2HHxsc3/FkIX6tbmWIDeis= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 04EF0e3X118803 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 14 May 2020 10:00:40 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 14 May 2020 10:00:39 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 14 May 2020 10:00:39 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04EExgAt019279; Thu, 14 May 2020 10:00:35 -0500 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Arnd Bergmann , Jon Mason , Dave Jiang , Allen Hubbe , Tom Joseph , Bjorn Helgaas , Rob Herring CC: Greg Kroah-Hartman , Jonathan Corbet , , , , , , Kishon Vijay Abraham I Subject: [PATCH 11/19] PCI: endpoint: Add helper API to populate header with values from DT Date: Thu, 14 May 2020 20:29:19 +0530 Message-ID: <20200514145927.17555-12-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200514145927.17555-1-kishon@ti.com> References: <20200514145927.17555-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add helper API pci_epc_of_parse_header() to populate header with values from device tree. These values will be written to the configuration space header in the endpoint controller. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-epc-core.c | 24 ++++++++++++++++++++++++ include/linux/pci-epc.h | 2 ++ 2 files changed, 26 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index df8789fee01e..31a82af397a3 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -31,6 +31,30 @@ static int devm_pci_epc_match(struct device *dev, void *res, void *match_data) return *epc == match_data; } +/** + * pci_epc_of_parse_header() - parse the device tree to get PCI config space + * header + * @node: The device tree node (of endpoint function) which has the PCI config + * space header values + * @header: standard configuration space header fields that has to be populated + * + * Invoke to populate *header* with the PCI configuration space values populated + * in device tree. + */ +void pci_epc_of_parse_header(struct device_node *node, + struct pci_epf_header *header) +{ + of_property_read_u16(node, "epf,vendor-id", &header->vendorid); + of_property_read_u16(node, "epf,device-id", &header->deviceid); + of_property_read_u8(node, "epf,baseclass-code", + &header->baseclass_code); + of_property_read_u8(node, "epf,subclass-code", &header->subclass_code); + of_property_read_u16(node, "epf,subsys-vendor-id", + &header->subsys_vendor_id); + of_property_read_u16(node, "epf,subsys-id", &header->subsys_id); +} +EXPORT_SYMBOL_GPL(pci_epc_of_parse_header); + /** * pci_epc_put() - release the PCI endpoint controller * @epc: epc returned by pci_epc_get() diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 463586889453..490a9077df52 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -199,6 +199,8 @@ int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, enum pci_epc_irq_type type, u16 interrupt_num); int pci_epc_start(struct pci_epc *epc); void pci_epc_stop(struct pci_epc *epc); +void pci_epc_of_parse_header(struct device_node *node, + struct pci_epf_header *header); const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc, u8 func_no); enum pci_barno From patchwork Thu May 14 14:59:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 200551 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB408C433DF for ; Thu, 14 May 2020 15:02:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B0D15205CB for ; Thu, 14 May 2020 15:02:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xcutUtJm" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728194AbgENPBS (ORCPT ); Thu, 14 May 2020 11:01:18 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:36018 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728179AbgENPBQ (ORCPT ); Thu, 14 May 2020 11:01:16 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 04EF0iav102750; Thu, 14 May 2020 10:00:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1589468444; bh=Rvt2032xBUVPb5hCaXR0nVbRlKB5NYJvIqKXfMFJ48k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xcutUtJmJVUw743oi8X4dRvDGLn6hxJ60FDWjtMXp8qLXq1ih0N3BAaLa56E6g9kB +7nmny8Z+l2g9/B3oDm94CkIcf7NwjTCdRMdMF3jRMQouw4/L1IRZc0+yuIXe3oj0Q 1oZLv4E1m1Xj4hrVCLds+gXmixOcPDrrHhkPUcso= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 04EF0iUj059557 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 14 May 2020 10:00:44 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 14 May 2020 10:00:44 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 14 May 2020 10:00:44 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04EExgAu019279; Thu, 14 May 2020 10:00:40 -0500 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Arnd Bergmann , Jon Mason , Dave Jiang , Allen Hubbe , Tom Joseph , Bjorn Helgaas , Rob Herring CC: Greg Kroah-Hartman , Jonathan Corbet , , , , , , Kishon Vijay Abraham I Subject: [PATCH 12/19] PCI: endpoint: Add support to associate secondary EPC with EPF Date: Thu, 14 May 2020 20:29:20 +0530 Message-ID: <20200514145927.17555-13-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200514145927.17555-1-kishon@ti.com> References: <20200514145927.17555-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the case of standard endpoint functions, only one endpoint controller (EPC) will be associated with an endpoint function (EPF). However for providing NTB (non transparent bridge) functionality, two EPCs should be associated with a single EPF. Add support to associate secondary EPC with EPF. This is in preparation for adding NTB endpoint function driver. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/functions/pci-epf-test.c | 11 ++-- drivers/pci/endpoint/pci-ep-cfs.c | 6 +- drivers/pci/endpoint/pci-epc-core.c | 50 ++++++++++++---- drivers/pci/endpoint/pci-epf-core.c | 57 +++++++++++++------ include/linux/pci-epc.h | 25 +++++++- include/linux/pci-epf.h | 17 +++++- 6 files changed, 128 insertions(+), 38 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index ba43e1e05958..b79d95f666ff 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -616,7 +616,8 @@ static void pci_epf_test_unbind(struct pci_epf *epf) if (epf_test->reg[bar]) { pci_epc_clear_bar(epc, epf->func_no, epf_bar); - pci_epf_free_space(epf, epf_test->reg[bar], bar); + pci_epf_free_space(epf, epf_test->reg[bar], bar, + PRIMARY_INTERFACE); } } } @@ -648,7 +649,8 @@ static int pci_epf_test_set_bar(struct pci_epf *epf) ret = pci_epc_set_bar(epc, epf->func_no, epf_bar); if (ret) { - pci_epf_free_space(epf, epf_test->reg[bar], bar); + pci_epf_free_space(epf, epf_test->reg[bar], bar, + PRIMARY_INTERFACE); dev_err(dev, "Failed to set BAR%d\n", bar); if (bar == test_reg_bar) return ret; @@ -768,7 +770,7 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf) } base = pci_epf_alloc_space(epf, test_reg_size, test_reg_bar, - epc_features->align); + epc_features->align, PRIMARY_INTERFACE); if (!base) { dev_err(dev, "Failed to allocated register space\n"); return -ENOMEM; @@ -786,7 +788,8 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf) continue; base = pci_epf_alloc_space(epf, bar_size[bar], bar, - epc_features->align); + epc_features->align, + PRIMARY_INTERFACE); if (!base) dev_err(dev, "Failed to allocate space for BAR%d\n", bar); diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c index 55edce50be96..0cd02caedd1c 100644 --- a/drivers/pci/endpoint/pci-ep-cfs.c +++ b/drivers/pci/endpoint/pci-ep-cfs.c @@ -94,13 +94,13 @@ static int pci_epc_epf_link(struct config_item *epc_item, struct pci_epc *epc = epc_group->epc; struct pci_epf *epf = epf_group->epf; - ret = pci_epc_add_epf(epc, epf); + ret = pci_epc_add_epf(epc, epf, PRIMARY_INTERFACE); if (ret) return ret; ret = pci_epf_bind(epf); if (ret) { - pci_epc_remove_epf(epc, epf); + pci_epc_remove_epf(epc, epf, PRIMARY_INTERFACE); return ret; } @@ -120,7 +120,7 @@ static void pci_epc_epf_unlink(struct config_item *epc_item, epc = epc_group->epc; epf = epf_group->epf; pci_epf_unbind(epf); - pci_epc_remove_epf(epc, epf); + pci_epc_remove_epf(epc, epf, PRIMARY_INTERFACE); } static struct configfs_item_operations pci_epc_item_ops = { diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 31a82af397a3..bd8f372c506f 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -577,22 +577,32 @@ EXPORT_SYMBOL_GPL(pci_epc_write_header); * pci_epc_add_epf() - bind PCI endpoint function to an endpoint controller * @epc: the EPC device to which the endpoint function should be added * @epf: the endpoint function to be added + * @type: Identifies if the EPC is connected to the primary or secondary + * interface of EPF * * A PCI endpoint device can have one or more functions. In the case of PCIe, * the specification allows up to 8 PCIe endpoint functions. Invoke * pci_epc_add_epf() to add a PCI endpoint function to an endpoint controller. */ -int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf) +int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf, + enum pci_epc_interface_type type) { + struct list_head *list; u32 func_no; int ret = 0; - if (epf->epc) - return -EBUSY; - if (IS_ERR(epc)) return -EINVAL; + if (epf->func_no > epc->max_functions - 1) + return -EINVAL; + + if (type == PRIMARY_INTERFACE && epf->epc) + return -EBUSY; + + if (type == SECONDARY_INTERFACE && epf->sec_epc) + return -EBUSY; + mutex_lock(&epc->lock); func_no = find_first_zero_bit(&epc->function_num_map, BITS_PER_LONG); @@ -608,11 +618,17 @@ int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf) } set_bit(func_no, &epc->function_num_map); - epf->func_no = func_no; - epf->epc = epc; - - list_add_tail(&epf->list, &epc->pci_epf); + if (type == PRIMARY_INTERFACE) { + epf->func_no = func_no; + epf->epc = epc; + list = &epf->list; + } else { + epf->sec_epc_func_no = func_no; + epf->sec_epc = epc; + list = &epf->sec_epc_list; + } + list_add_tail(list, &epc->pci_epf); ret: mutex_unlock(&epc->lock); @@ -627,14 +643,26 @@ EXPORT_SYMBOL_GPL(pci_epc_add_epf); * * Invoke to remove PCI endpoint function from the endpoint controller. */ -void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf) +void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf, + enum pci_epc_interface_type type) { + struct list_head *list; + u32 func_no = 0; + if (!epc || IS_ERR(epc) || !epf) return; + if (type == PRIMARY_INTERFACE) { + func_no = epf->func_no; + list = &epf->list; + } else { + func_no = epf->sec_epc_func_no; + list = &epf->sec_epc_list; + } + mutex_lock(&epc->lock); - clear_bit(epf->func_no, &epc->function_num_map); - list_del(&epf->list); + clear_bit(func_no, &epc->function_num_map); + list_del(list); epf->epc = NULL; mutex_unlock(&epc->lock); } diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index f463eedcc3ad..97ddb86faac5 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -73,24 +73,37 @@ EXPORT_SYMBOL_GPL(pci_epf_bind); * pci_epf_free_space() - free the allocated PCI EPF register space * @addr: the virtual address of the PCI EPF register space * @bar: the BAR number corresponding to the register space + * @type: Identifies if the allocated space is for primary EPC or secondary EPC * * Invoke to free the allocated PCI EPF register space. */ -void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar) +void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar, + enum pci_epc_interface_type type) { struct device *dev = epf->epc->dev.parent; + struct pci_epf_bar *epf_bar; + struct pci_epc *epc; if (!addr) return; - dma_free_coherent(dev, epf->bar[bar].size, addr, - epf->bar[bar].phys_addr); + if (type == PRIMARY_INTERFACE) { + epc = epf->epc; + epf_bar = epf->bar; + } else { + epc = epf->sec_epc; + epf_bar = epf->sec_epc_bar; + } + + dev = epc->dev.parent; + dma_free_coherent(dev, epf_bar[bar].size, addr, + epf_bar[bar].phys_addr); - epf->bar[bar].phys_addr = 0; - epf->bar[bar].addr = NULL; - epf->bar[bar].size = 0; - epf->bar[bar].barno = 0; - epf->bar[bar].flags = 0; + epf_bar[bar].phys_addr = 0; + epf_bar[bar].addr = NULL; + epf_bar[bar].size = 0; + epf_bar[bar].barno = 0; + epf_bar[bar].flags = 0; } EXPORT_SYMBOL_GPL(pci_epf_free_space); @@ -99,15 +112,18 @@ EXPORT_SYMBOL_GPL(pci_epf_free_space); * @size: the size of the memory that has to be allocated * @bar: the BAR number corresponding to the allocated register space * @align: alignment size for the allocation region + * @type: Identifies if the allocation is for primary EPC or secondary EPC * * Invoke to allocate memory for the PCI EPF register space. */ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, - size_t align) + size_t align, enum pci_epc_interface_type type) { - void *space; - struct device *dev = epf->epc->dev.parent; + struct pci_epf_bar *epf_bar; dma_addr_t phys_addr; + struct pci_epc *epc; + struct device *dev; + void *space; if (size < 128) size = 128; @@ -117,17 +133,26 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, else size = roundup_pow_of_two(size); + if (type == PRIMARY_INTERFACE) { + epc = epf->epc; + epf_bar = epf->bar; + } else { + epc = epf->sec_epc; + epf_bar = epf->sec_epc_bar; + } + + dev = epc->dev.parent; space = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL); if (!space) { dev_err(dev, "failed to allocate mem space\n"); return NULL; } - epf->bar[bar].phys_addr = phys_addr; - epf->bar[bar].addr = space; - epf->bar[bar].size = size; - epf->bar[bar].barno = bar; - epf->bar[bar].flags |= upper_32_bits(size) ? + epf_bar[bar].phys_addr = phys_addr; + epf_bar[bar].addr = space; + epf_bar[bar].size = size; + epf_bar[bar].barno = bar; + epf_bar[bar].flags |= upper_32_bits(size) ? PCI_BASE_ADDRESS_MEM_TYPE_64 : PCI_BASE_ADDRESS_MEM_TYPE_32; diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 490a9077df52..e7614dda4e0e 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -13,6 +13,12 @@ struct pci_epc; +enum pci_epc_interface_type { + UNKNOWN_INTERFACE = -1, + PRIMARY_INTERFACE, + SECONDARY_INTERFACE, +}; + enum pci_epc_irq_type { PCI_EPC_IRQ_UNKNOWN, PCI_EPC_IRQ_LEGACY, @@ -20,6 +26,19 @@ enum pci_epc_irq_type { PCI_EPC_IRQ_MSIX, }; +static inline const char * +pci_epc_interface_string(enum pci_epc_interface_type type) +{ + switch (type) { + case PRIMARY_INTERFACE: + return "primary"; + case SECONDARY_INTERFACE: + return "secondary"; + default: + return "UNKNOWN interface"; + } +} + /** * struct pci_epc_ops - set of function pointers for performing EPC operations * @write_header: ops to populate configuration space header @@ -175,10 +194,12 @@ __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, struct module *owner); void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc); void pci_epc_destroy(struct pci_epc *epc); -int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf); +int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf, + enum pci_epc_interface_type type); void pci_epc_linkup(struct pci_epc *epc); void pci_epc_init_notify(struct pci_epc *epc); -void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf); +void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf, + enum pci_epc_interface_type type); int pci_epc_write_header(struct pci_epc *epc, u8 func_no, struct pci_epf_header *hdr); int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index 9bd89f1be1c3..581fe121d670 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -15,6 +15,7 @@ #include struct pci_epf; +enum pci_epc_interface_type; enum pci_notify_event { CORE_INIT, @@ -121,6 +122,11 @@ struct pci_epf_bar { * @list: to add pci_epf as a list of PCI endpoint functions to pci_epc * @nb: notifier block to notify EPF of any EPC events (like linkup) * @lock: mutex to protect pci_epf_ops + * @sec_epc: the secondary EPC device to which this EPF device is bound + * @sec_epc_list: to add pci_epf as list of PCI endpoint functions to secondary + * EPC device + * @sec_epc_bar: represents the BAR of EPF device associated with secondary EPC + * @sec_epc_func_no: unique (physical) function number within the secondary EPC */ struct pci_epf { struct device dev; @@ -138,6 +144,12 @@ struct pci_epf { struct notifier_block nb; /* mutex to protect against concurrent access of pci_epf_ops */ struct mutex lock; + + /* Below members are to attach secondary EPC to an endpoint function */ + struct pci_epc *sec_epc; + struct list_head sec_epc_list; + struct pci_epf_bar sec_epc_bar[6]; + u8 sec_epc_func_no; }; /** @@ -177,8 +189,9 @@ int __pci_epf_register_driver(struct pci_epf_driver *driver, struct module *owner); void pci_epf_unregister_driver(struct pci_epf_driver *driver); void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, - size_t align); -void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar); + size_t align, enum pci_epc_interface_type type); +void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar, + enum pci_epc_interface_type type); int pci_epf_bind(struct pci_epf *epf); void pci_epf_unbind(struct pci_epf *epf); #endif /* __LINUX_PCI_EPF_H */ From patchwork Thu May 14 14:59:22 2020 Content-Type: text/plain; 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Thu, 14 May 2020 10:00:53 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 14 May 2020 10:00:53 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04EExgAw019279; Thu, 14 May 2020 10:00:49 -0500 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Arnd Bergmann , Jon Mason , Dave Jiang , Allen Hubbe , Tom Joseph , Bjorn Helgaas , Rob Herring CC: Greg Kroah-Hartman , Jonathan Corbet , , , , , , Kishon Vijay Abraham I Subject: [PATCH 14/19] PCI: cadence: Implement ->msi_map_irq() ops Date: Thu, 14 May 2020 20:29:22 +0530 Message-ID: <20200514145927.17555-15-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200514145927.17555-1-kishon@ti.com> References: <20200514145927.17555-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Implement ->msi_map_irq() ops in order to map physical address to MSI address and return MSI data. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/cadence/pcie-cadence-ep.c | 50 +++++++++++++++++++ drivers/pci/endpoint/pci-epc-core.c | 7 ++- include/linux/pci-epc.h | 2 +- 3 files changed, 54 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index e6588a0cd705..74d36fb9ea5d 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -380,6 +380,54 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, return 0; } +static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, + phys_addr_t addr, u8 interrupt_num, + u32 entry_size, u32 *msi_data) +{ + struct cdns_pcie_ep *ep = epc_get_drvdata(epc); + u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + struct cdns_pcie *pcie = &ep->pcie; + u16 flags, mme, data, data_mask; + u8 msi_count; + u64 pci_addr; + int ret; + int i; + + /* Check whether the MSI feature has been enabled by the PCI host. */ + flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + if (!(flags & PCI_MSI_FLAGS_ENABLE)) + return -EINVAL; + + /* Get the number of enabled MSIs */ + mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4; + msi_count = 1 << mme; + if (!interrupt_num || interrupt_num > msi_count) + return -EINVAL; + + /* Compute the data value to be written. */ + data_mask = msi_count - 1; + data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); + data = data & ~data_mask; + + /* Get the PCI address where to write the data into. */ + pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); + pci_addr <<= 32; + pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); + pci_addr &= GENMASK_ULL(63, 2); + + for (i = 0; i < interrupt_num; i++) { + ret = cdns_pcie_ep_map_addr(epc, fn, addr, pci_addr, + entry_size); + if (ret) + return ret; + addr = addr + entry_size; + } + + *msi_data = data; + + return 0; +} + static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u16 interrupt_num) { @@ -480,6 +528,7 @@ static const struct pci_epc_features cdns_pcie_epc_features = { .linkup_notifier = false, .msi_capable = true, .msix_capable = true, + .align = 256, }; static const struct pci_epc_features* @@ -499,6 +548,7 @@ static const struct pci_epc_ops cdns_pcie_epc_ops = { .set_msix = cdns_pcie_ep_set_msix, .get_msix = cdns_pcie_ep_get_msix, .raise_irq = cdns_pcie_ep_raise_irq, + .map_msi_irq = cdns_pcie_ep_map_msi_irq, .start = cdns_pcie_ep_start, .get_features = cdns_pcie_ep_get_features, }; diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 3f481a12d43d..ab5da996953e 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -319,7 +319,6 @@ EXPORT_SYMBOL_GPL(pci_epc_raise_irq); * MSI data * @epc: the EPC device which has the MSI capability * @func_no: the physical endpoint function number in the EPC device - * @vfunc_no: the virtual endpoint function number in the physical function * @phys_addr: the physical address of the outbound region * @interrupt_num: the MSI interrupt number * @entry_size: Size of Outbound address region for each interrupt @@ -333,7 +332,7 @@ EXPORT_SYMBOL_GPL(pci_epc_raise_irq); * physical address (in outbound region) of the other interface to ring * doorbell. */ -int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no, +int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, phys_addr_t phys_addr, u8 interrupt_num, u32 entry_size, u32 *msi_data) { @@ -346,8 +345,8 @@ int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no, return -EINVAL; mutex_lock(&epc->lock); - ret = epc->ops->map_msi_irq(epc, func_no, vfunc_no, phys_addr, - interrupt_num, entry_size, msi_data); + ret = epc->ops->map_msi_irq(epc, func_no, phys_addr, interrupt_num, + entry_size, msi_data); mutex_unlock(&epc->lock); return ret; diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 59cd4c967329..bb00f107c0dc 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -78,7 +78,7 @@ struct pci_epc_ops { int (*get_msix)(struct pci_epc *epc, u8 func_no); int (*raise_irq)(struct pci_epc *epc, u8 func_no, enum pci_epc_irq_type type, u16 interrupt_num); - int (*map_msi_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + int (*map_msi_irq)(struct pci_epc *epc, u8 func_no, phys_addr_t phys_addr, u8 interrupt_num, u32 entry_size, u32 *msi_data); int (*start)(struct pci_epc *epc); From patchwork Thu May 14 14:59:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 200552 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C40F6C433E1 for ; Thu, 14 May 2020 15:02:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9B3CC20643 for ; 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Thu, 14 May 2020 10:01:13 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 14 May 2020 10:01:12 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 14 May 2020 10:01:13 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04EExgB2019279; Thu, 14 May 2020 10:01:08 -0500 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Arnd Bergmann , Jon Mason , Dave Jiang , Allen Hubbe , Tom Joseph , Bjorn Helgaas , Rob Herring CC: Greg Kroah-Hartman , Jonathan Corbet , , , , , , Kishon Vijay Abraham I Subject: [PATCH 18/19] NTB: tool: Enable the NTB/PCIe link on the local or remote side of bridge Date: Thu, 14 May 2020 20:29:26 +0530 Message-ID: <20200514145927.17555-19-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200514145927.17555-1-kishon@ti.com> References: <20200514145927.17555-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Invoke ntb_link_enable() to enable the NTB/PCIe link on the local or remote side of the bridge. Signed-off-by: Kishon Vijay Abraham I --- drivers/ntb/test/ntb_tool.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/ntb/test/ntb_tool.c b/drivers/ntb/test/ntb_tool.c index 69da758fe64c..4b4f9e2a2c43 100644 --- a/drivers/ntb/test/ntb_tool.c +++ b/drivers/ntb/test/ntb_tool.c @@ -1638,6 +1638,7 @@ static int tool_probe(struct ntb_client *self, struct ntb_dev *ntb) tool_setup_dbgfs(tc); + ntb_link_enable(ntb, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); return 0; err_clear_mws: