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Mon, 18 May 2020 04:09:37 -0700 (PDT) From: dillon.minfei@gmail.com To: robh+dt@kernel.org, p.zabel@pengutronix.de, mcoquelin.stm32@gmail.com, broonie@kernel.org, devicetree@vger.kernel.org, alexandre.torgue@st.com, thierry.reding@gmail.com, sam@ravnborg.org, airlied@linux.ie, daniel@ffwll.ch, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, dillon min Subject: [PATCH v4 1/8] ARM: dts: stm32: Add dma config for spi5 Date: Mon, 18 May 2020 19:09:18 +0800 Message-Id: <1589800165-3271-2-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589800165-3271-1-git-send-email-dillon.minfei@gmail.com> References: <1589800165-3271-1-git-send-email-dillon.minfei@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: dillon min Enable spi5's dma configuration. for graphics data output to ilitek ili9341 panel via mipi dbi interface Signed-off-by: dillon min --- arch/arm/boot/dts/stm32f429.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index d777069..5820b11 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -660,6 +660,9 @@ reg = <0x40015000 0x400>; interrupts = <85>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>; + dmas = <&dma2 3 2 0x400 0x0>, + <&dma2 4 2 0x400 0x0>; + dma-names = "rx", "tx"; status = "disabled"; }; From patchwork Mon May 18 11:09:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 200415 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05B33C433E2 for ; Mon, 18 May 2020 11:09:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D34C42084C for ; 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Mon, 18 May 2020 04:09:48 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([103.206.190.146]) by smtp.gmail.com with ESMTPSA id a15sm8290630pju.3.2020.05.18.04.09.43 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 18 May 2020 04:09:47 -0700 (PDT) From: dillon.minfei@gmail.com To: robh+dt@kernel.org, p.zabel@pengutronix.de, mcoquelin.stm32@gmail.com, broonie@kernel.org, devicetree@vger.kernel.org, alexandre.torgue@st.com, thierry.reding@gmail.com, sam@ravnborg.org, airlied@linux.ie, daniel@ffwll.ch, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, dillon min Subject: [PATCH v4 3/8] spi: stm32: Add 'SPI_SIMPLEX_RX', 'SPI_3WIRE_RX' support for stm32f4 Date: Mon, 18 May 2020 19:09:20 +0800 Message-Id: <1589800165-3271-4-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589800165-3271-1-git-send-email-dillon.minfei@gmail.com> References: <1589800165-3271-1-git-send-email-dillon.minfei@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: dillon min in l3gd20 driver startup, there is a setup failed error return from stm32 spi driver " [ 2.687630] st-gyro-spi spi0.0: supply vdd not found, using dummy regulator [ 2.696869] st-gyro-spi spi0.0: supply vddio not found, using dummy regulator [ 2.706707] spi_stm32 40015000.spi: SPI transfer setup failed [ 2.713741] st-gyro-spi spi0.0: SPI transfer failed: -22 [ 2.721096] spi_master spi0: failed to transfer one message from queue [ 2.729268] iio iio:device0: failed to read Who-Am-I register. [ 2.737504] st-gyro-spi: probe of spi0.0 failed with error -22 " after debug into spi-stm32 driver, st-gyro-spi split two steps to read l3gd20 id first: send command to l3gd20 with read id command in tx_buf, rx_buf is null. second: read id with tx_buf is null, rx_buf not null. so, for second step, stm32 driver recongise this process is 'SPI_SIMPLE_RX' from stm32_spi_communication_type(), but there is no related process for this type in stm32f4_spi_set_mode(), then we get error from stm32_spi_transfer_one_setup(). we can use two method to fix this bug. 1, use stm32 spi's "In unidirectional receive-only mode (BIDIMODE=0 and RXONLY=1)". but as our code running in sdram, the read latency is too large to get so many receive overrun error in interrupts handler. 2, use stm32 spi's "In full-duplex (BIDIMODE=0 and RXONLY=0)", as tx_buf is null, we must add dummy data sent out before read data. so, add stm32f4_spi_tx_dummy() to handle this situation. Signed-off-by: dillon min --- drivers/spi/spi-stm32.c | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c index 44ac6eb3..72d9387 100644 --- a/drivers/spi/spi-stm32.c +++ b/drivers/spi/spi-stm32.c @@ -388,6 +388,14 @@ static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi) return count; } +static void stm32f4_spi_tx_dummy(struct stm32_spi *spi) +{ + if (spi->cur_bpw == 16) + writew_relaxed(0x5555, spi->base + STM32F4_SPI_DR); + else + writeb_relaxed(0x55, spi->base + STM32F4_SPI_DR); +} + /** * stm32f4_spi_get_bpw_mask - Return bits per word mask * @spi: pointer to the spi controller data structure @@ -811,7 +819,9 @@ static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id) mask |= STM32F4_SPI_SR_TXE; } - if (!spi->cur_usedma && spi->cur_comm == SPI_FULL_DUPLEX) { + if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX || + spi->cur_comm == SPI_SIMPLEX_RX || + spi->cur_comm == SPI_3WIRE_RX)) { /* TXE flag is set and is handled when RXNE flag occurs */ sr &= ~STM32F4_SPI_SR_TXE; mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR; @@ -850,8 +860,10 @@ static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id) stm32f4_spi_read_rx(spi); if (spi->rx_len == 0) end = true; - else /* Load data for discontinuous mode */ + else if (spi->tx_buf)/* Load data for discontinuous mode */ stm32f4_spi_write_tx(spi); + else if (spi->cur_comm == SPI_SIMPLEX_RX) + stm32f4_spi_tx_dummy(spi); } end_irq: @@ -1151,7 +1163,9 @@ static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi) /* Enable the interrupts relative to the current communication mode */ if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { cr2 |= STM32F4_SPI_CR2_TXEIE; - } else if (spi->cur_comm == SPI_FULL_DUPLEX) { + } else if (spi->cur_comm == SPI_FULL_DUPLEX || + spi->cur_comm == SPI_SIMPLEX_RX || + spi->cur_comm == SPI_3WIRE_RX) { /* In transmit-only mode, the OVR flag is set in the SR register * since the received data are never read. Therefore set OVR * interrupt only when rx buffer is available. @@ -1170,6 +1184,8 @@ static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi) /* starting data transfer when buffer is loaded */ if (spi->tx_buf) stm32f4_spi_write_tx(spi); + else if (spi->cur_comm == SPI_SIMPLEX_RX) + stm32f4_spi_tx_dummy(spi); spin_unlock_irqrestore(&spi->lock, flags); @@ -1462,10 +1478,16 @@ static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_BIDIMODE | STM32F4_SPI_CR1_BIDIOE); - } else if (comm_type == SPI_FULL_DUPLEX) { + } else if (comm_type == SPI_FULL_DUPLEX || + comm_type == SPI_SIMPLEX_RX) { stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_BIDIMODE | STM32F4_SPI_CR1_BIDIOE); + } else if (comm_type == SPI_3WIRE_RX) { + stm32_spi_set_bits(spi, STM32F4_SPI_CR1, + STM32F4_SPI_CR1_BIDIMODE); + stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, + STM32F4_SPI_CR1_BIDIOE); } else { return -EINVAL; } From patchwork Mon May 18 11:09:22 2020 Content-Type: text/plain; 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Mon, 18 May 2020 04:09:58 -0700 (PDT) From: dillon.minfei@gmail.com To: robh+dt@kernel.org, p.zabel@pengutronix.de, mcoquelin.stm32@gmail.com, broonie@kernel.org, devicetree@vger.kernel.org, alexandre.torgue@st.com, thierry.reding@gmail.com, sam@ravnborg.org, airlied@linux.ie, daniel@ffwll.ch, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, dillon min Subject: [PATCH v4 5/8] dt-bindings: display: panel: Add ilitek ili9341 panel bindings Date: Mon, 18 May 2020 19:09:22 +0800 Message-Id: <1589800165-3271-6-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589800165-3271-1-git-send-email-dillon.minfei@gmail.com> References: <1589800165-3271-1-git-send-email-dillon.minfei@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: dillon min Add documentation for "ilitek,ili9341" panel. Signed-off-by: dillon min --- .../bindings/display/panel/ilitek,ili9341.yaml | 69 ++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml new file mode 100644 index 0000000..2172f88 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/ilitek,ili9341.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ilitek-9341 Display Panel + +maintainers: + - Dillon Min + +description: | + Ilitek ILI9341 TFT panel driver with SPI control bus + This is a driver for 320x240 TFT panels, accepting a rgb input + streams with 16 bits or 18 bits. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + # ili9341 240*320 Color on stm32f429-disco board + - st,sf-tc240t-9370-t + - const: ilitek,ili9341 + + reg: true + + dc-gpios: + maxItems: 1 + description: Display data/command selection (D/CX) + + spi-3wire: true + + spi-max-frequency: + const: 10000000 + + port: true + +additionalProperties: false + +required: + - compatible + - reg + - dc-gpios + - port + +examples: + - |+ + spi { + #address-cells = <1>; + #size-cells = <0>; + panel: display@0 { + compatible = "st,sf-tc240t-9370-t", + "ilitek,ili9341"; + reg = <0>; + spi-3wire; + spi-max-frequency = <10000000>; + dc-gpios = <&gpiod 13 0>; + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + }; +... + From patchwork Mon May 18 11:09:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 200413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62B28C433E0 for ; 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Mon, 18 May 2020 04:10:08 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([103.206.190.146]) by smtp.gmail.com with ESMTPSA id a15sm8290630pju.3.2020.05.18.04.10.03 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 18 May 2020 04:10:08 -0700 (PDT) From: dillon.minfei@gmail.com To: robh+dt@kernel.org, p.zabel@pengutronix.de, mcoquelin.stm32@gmail.com, broonie@kernel.org, devicetree@vger.kernel.org, alexandre.torgue@st.com, thierry.reding@gmail.com, sam@ravnborg.org, airlied@linux.ie, daniel@ffwll.ch, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, dillon min Subject: [PATCH v4 7/8] clk: stm32: Fix stm32f429's ltdc driver hang in set clock rate. Date: Mon, 18 May 2020 19:09:24 +0800 Message-Id: <1589800165-3271-8-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589800165-3271-1-git-send-email-dillon.minfei@gmail.com> References: <1589800165-3271-1-git-send-email-dillon.minfei@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: dillon min fix duplicated ltdc clock register to 'clk_core' case ltdc's clock turn off by clk_disable_unused() ltdc set clock rate crashed: 'post_div_data[]''s pll_num is PLL_I2S, PLL_SAI (number is 1,2). but, as pll_num is offset of 'clks[]' input to clk_register_pll_div(), which is FCLK, CLK_LSI, defined in 'include/dt-bindings/clock/stm32fx-clock.h' so, this is a null object at the register time. then, in ltdc's clock is_enabled(), enable(), will call to_clk_gate(). will return a null object, cause kernel crashed. need change pll_num to PLL_VCO_I2S, PLL_VCO_SAI for 'post_div_data[]' duplicated ltdc clock 'stm32f429_gates[]' has a member 'ltdc' register to 'clk_core', but no upper driver use it, ltdc driver use the lcd-tft defined in 'stm32f429_aux_clk[]'. after system startup, as stm32f429_gates[]'s ltdc enable_count is zero, so turn off by clk_disable_unused() Signed-off-by: dillon min --- Hi Stephen Boyd: thanks for reviewing, this patch fix the wrong use of clk ignore unused. thanks. Changes since V3: 1 drop last wrong changes about 'CLK_IGNORE_UNUSED' patch 2 fix PLL_SAI mismatch with PLL_VCO_SAI drivers/clk/clk-stm32f4.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index 18117ce..fa62e99 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -129,7 +129,6 @@ static const struct stm32f4_gate_data stm32f429_gates[] __initconst = { { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" }, { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, - { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" }, }; static const struct stm32f4_gate_data stm32f469_gates[] __initconst = { @@ -557,13 +556,13 @@ static const struct clk_div_table post_divr_table[] = { #define MAX_POST_DIV 3 static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = { - { CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q", + { CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q", CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL}, - { CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q", + { CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q", CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL }, - { NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT, + { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table }, };