From patchwork Mon May 18 14:47:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 200398 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40EBBC433DF for ; Mon, 18 May 2020 14:57:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 29CD5207D8 for ; Mon, 18 May 2020 14:57:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728115AbgERO5h (ORCPT ); Mon, 18 May 2020 10:57:37 -0400 Received: from inva020.nxp.com ([92.121.34.13]:56316 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728113AbgERO53 (ORCPT ); Mon, 18 May 2020 10:57:29 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 0AF6D1A0B12; Mon, 18 May 2020 16:57:28 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 8F17E1A0B14; Mon, 18 May 2020 16:57:22 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id D0E09402AF; Mon, 18 May 2020 22:57:15 +0800 (SGT) From: Anson Huang To: daniel.lezcano@linaro.org, tglx@linutronix.de, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, ping.bai@nxp.com, aisheng.dong@nxp.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Linux-imx@nxp.com Subject: [PATCH 2/3] dt-bindings: timer: Convert i.MX TPM to json-schema Date: Mon, 18 May 2020 22:47:39 +0800 Message-Id: <1589813260-20036-3-git-send-email-Anson.Huang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589813260-20036-1-git-send-email-Anson.Huang@nxp.com> References: <1589813260-20036-1-git-send-email-Anson.Huang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the i.MX TPM binding to DT schema format using json-schema. Signed-off-by: Anson Huang --- .../devicetree/bindings/timer/nxp,tpm-timer.txt | 28 ---------- .../devicetree/bindings/timer/nxp,tpm-timer.yaml | 63 ++++++++++++++++++++++ 2 files changed, 63 insertions(+), 28 deletions(-) delete mode 100644 Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt create mode 100644 Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt deleted file mode 100644 index f82087b..0000000 --- a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt +++ /dev/null @@ -1,28 +0,0 @@ -NXP Low Power Timer/Pulse Width Modulation Module (TPM) - -The Timer/PWM Module (TPM) supports input capture, output compare, -and the generation of PWM signals to control electric motor and power -management applications. The counter, compare and capture registers -are clocked by an asynchronous clock that can remain enabled in low -power modes. TPM can support global counter bus where one TPM drives -the counter bus for the others, provided bit width is the same. - -Required properties: - -- compatible : should be "fsl,imx7ulp-tpm" -- reg : Specifies base physical address and size of the register sets - for the clock event device and clock source device. -- interrupts : Should be the clock event device interrupt. -- clocks : The clocks provided by the SoC to drive the timer, must contain - an entry for each entry in clock-names. -- clock-names : Must include the following entries: "ipg" and "per". - -Example: -tpm5: tpm@40260000 { - compatible = "fsl,imx7ulp-tpm"; - reg = <0x40260000 0x1000>; - interrupts = ; - clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, - <&clks IMX7ULP_CLK_LPTPM5>; - clock-names = "ipg", "per"; -}; diff --git a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml new file mode 100644 index 0000000..0d34610 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Low Power Timer/Pulse Width Modulation Module (TPM) + +maintainers: + - Dong Aisheng + +description: | + The Timer/PWM Module (TPM) supports input capture, output compare, + and the generation of PWM signals to control electric motor and power + management applications. The counter, compare and capture registers + are clocked by an asynchronous clock that can remain enabled in low + power modes. TPM can support global counter bus where one TPM drives + the counter bus for the others, provided bit width is the same. + +properties: + compatible: + const: fsl,imx7ulp-tpm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: SoC TPM ipg clock + - description: SoC TPM per clock + maxItems: 2 + + clock-names: + items: + - const: ipg + - const: per + maxItems: 2 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + timer@40260000 { + compatible = "fsl,imx7ulp-tpm"; + reg = <0x40260000 0x1000>; + interrupts = ; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&pcc2 IMX7ULP_CLK_LPTPM5>; + clock-names = "ipg", "per"; + }; From patchwork Mon May 18 14:47:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 200399 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47803C433DF for ; Mon, 18 May 2020 14:57:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 29DAB20756 for ; Mon, 18 May 2020 14:57:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728152AbgERO5b (ORCPT ); Mon, 18 May 2020 10:57:31 -0400 Received: from inva020.nxp.com ([92.121.34.13]:56358 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728115AbgERO5a (ORCPT ); Mon, 18 May 2020 10:57:30 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id DF4281A0B13; Mon, 18 May 2020 16:57:28 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6D0791A097E; Mon, 18 May 2020 16:57:23 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 138D6402B3; Mon, 18 May 2020 22:57:17 +0800 (SGT) From: Anson Huang To: daniel.lezcano@linaro.org, tglx@linutronix.de, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, ping.bai@nxp.com, aisheng.dong@nxp.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Linux-imx@nxp.com Subject: [PATCH 3/3] dt-bindings: timer: Convert i.MX SYSCTR to json-schema Date: Mon, 18 May 2020 22:47:40 +0800 Message-Id: <1589813260-20036-4-git-send-email-Anson.Huang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589813260-20036-1-git-send-email-Anson.Huang@nxp.com> References: <1589813260-20036-1-git-send-email-Anson.Huang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the i.MX SYSCTR binding to DT schema format using json-schema. Signed-off-by: Anson Huang --- .../devicetree/bindings/timer/nxp,sysctr-timer.txt | 25 ---------- .../bindings/timer/nxp,sysctr-timer.yaml | 54 ++++++++++++++++++++++ 2 files changed, 54 insertions(+), 25 deletions(-) delete mode 100644 Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt create mode 100644 Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt deleted file mode 100644 index d576599..0000000 --- a/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt +++ /dev/null @@ -1,25 +0,0 @@ -NXP System Counter Module(sys_ctr) - -The system counter(sys_ctr) is a programmable system counter which provides -a shared time base to Cortex A15, A7, A53, A73, etc. it is intended for use in -applications where the counter is always powered and support multiple, -unrelated clocks. The compare frame inside can be used for timer purpose. - -Required properties: - -- compatible : should be "nxp,sysctr-timer" -- reg : Specifies the base physical address and size of the comapre - frame and the counter control, read & compare. -- interrupts : should be the first compare frames' interrupt -- clocks : Specifies the counter clock. -- clock-names: Specifies the clock's name of this module - -Example: - - system_counter: timer@306a0000 { - compatible = "nxp,sysctr-timer"; - reg = <0x306a0000 0x20000>;/* system-counter-rd & compare */ - clocks = <&clk_8m>; - clock-names = "per"; - interrupts = ; - }; diff --git a/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml new file mode 100644 index 0000000..830211c --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/nxp,sysctr-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP System Counter Module(sys_ctr) + +maintainers: + - Bai Ping + +description: | + The system counter(sys_ctr) is a programmable system counter + which provides a shared time base to Cortex A15, A7, A53, A73, + etc. it is intended for use in applications where the counter + is always powered and support multiple, unrelated clocks. The + compare frame inside can be used for timer purpose. + +properties: + compatible: + const: nxp,sysctr-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: per + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + + timer@306a0000 { + compatible = "nxp,sysctr-timer"; + reg = <0x306a0000 0x20000>; + clocks = <&clk_8m>; + clock-names = "per"; + interrupts = ; + };