From patchwork Tue May 19 14:18:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 200363 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FF9DC433E0 for ; Tue, 19 May 2020 14:18:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3129120825 for ; Tue, 19 May 2020 14:18:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ADoH+zyr" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729211AbgESOSX (ORCPT ); Tue, 19 May 2020 10:18:23 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58230 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729193AbgESOSW (ORCPT ); Tue, 19 May 2020 10:18:22 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 04JEIIZE072941; Tue, 19 May 2020 09:18:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1589897898; bh=3+JLyobE6CLV4WmdNv4VMaXp4knXgWi6fteWMgKn13U=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ADoH+zyr5MIRS2MXLxf2ZMml+U1sLZaPUz1WZVYa6qpXSaxpca9eZM28NUgXkBVo1 bVl2nRJpXjY9ibRgL0hRiocT+khDedK4qBW7AMpbqRC9S2QRpY44x5N6b+YISr9moq j3SkgbWc2+VsXgwbbJVjpkVnENv7drfp3AZo/c40= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04JEIIm4026411; Tue, 19 May 2020 09:18:18 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 19 May 2020 09:18:18 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 19 May 2020 09:18:18 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04JEIHQr058715; Tue, 19 May 2020 09:18:17 -0500 From: Dan Murphy To: , , , CC: , , , Dan Murphy Subject: [PATCH net-next 2/4] net: phy: dp83869: Set opmode from straps Date: Tue, 19 May 2020 09:18:11 -0500 Message-ID: <20200519141813.28167-3-dmurphy@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200519141813.28167-1-dmurphy@ti.com> References: <20200519141813.28167-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org If the op-mode for the device is not set in the device tree then set the strapped op-mode and store it for later configuration. Signed-off-by: Dan Murphy --- drivers/net/phy/dp83869.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index 073a0f7754a5..64fa2d911074 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -65,6 +65,7 @@ #define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0) /* STRAP_STS1 bits */ +#define DP83869_STRAP_OP_MODE_MASK GENMASK(2, 0) #define DP83869_STRAP_STS1_RESERVED BIT(11) #define DP83869_STRAP_MIRROR_ENABLED BIT(12) @@ -161,6 +162,20 @@ static int dp83869_config_port_mirroring(struct phy_device *phydev) DP83869_CFG3_PORT_MIRROR_EN); } +static int dp83869_set_strapped_mode(struct phy_device *phydev) +{ + struct dp83869_private *dp83869 = phydev->priv; + u16 val; + + val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); + if (val < 0) + return val; + + dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK; + + return 0; +} + #ifdef CONFIG_OF_MDIO static int dp83869_of_init(struct phy_device *phydev) { @@ -185,6 +200,10 @@ static int dp83869_of_init(struct phy_device *phydev) if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) return -EINVAL; + } else { + ret = dp83869_set_strapped_mode(phydev); + if (ret) + return ret; } if (of_property_read_bool(of_node, "ti,max-output-impedance")) @@ -218,7 +237,7 @@ static int dp83869_of_init(struct phy_device *phydev) #else static int dp83869_of_init(struct phy_device *phydev) { - return 0; + return dp83869_set_strapped_mode(phydev); } #endif /* CONFIG_OF_MDIO */ From patchwork Tue May 19 14:18:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 200362 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D4C8C433DF for ; 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Tue, 19 May 2020 09:18:19 -0500 From: Dan Murphy To: , , , CC: , , , Dan Murphy Subject: [PATCH net-next 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 Date: Tue, 19 May 2020 09:18:12 -0500 Message-ID: <20200519141813.28167-4-dmurphy@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200519141813.28167-1-dmurphy@ti.com> References: <20200519141813.28167-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the internal delay values into the header and update the binding with the internal delay properties. Signed-off-by: Dan Murphy --- .../devicetree/bindings/net/ti,dp83869.yaml | 16 ++++++++++++++++ include/dt-bindings/net/ti-dp83869.h | 18 ++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ti,dp83869.yaml b/Documentation/devicetree/bindings/net/ti,dp83869.yaml index 5b69ef03bbf7..344015ab9081 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83869.yaml +++ b/Documentation/devicetree/bindings/net/ti,dp83869.yaml @@ -64,6 +64,20 @@ properties: Operational mode for the PHY. If this is not set then the operational mode is set by the straps. see dt-bindings/net/ti-dp83869.h for values + ti,rx-internal-delay: + $ref: /schemas/types.yaml#definitions/uint32 + description: | + RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83869.h + for applicable values. Required only if interface type is + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID. + + ti,tx-internal-delay: + $ref: /schemas/types.yaml#definitions/uint32 + description: | + RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83869.h + for applicable values. Required only if interface type is + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID. + required: - reg @@ -80,5 +94,7 @@ examples: ti,op-mode = ; ti,max-output-impedance = "true"; ti,clk-output-sel = ; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; }; }; diff --git a/include/dt-bindings/net/ti-dp83869.h b/include/dt-bindings/net/ti-dp83869.h index 218b1a64e975..77d104a40f1f 100644 --- a/include/dt-bindings/net/ti-dp83869.h +++ b/include/dt-bindings/net/ti-dp83869.h @@ -16,6 +16,24 @@ #define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 #define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 +/* RGMIIDCTL internal delay for rx and tx */ +#define DP83869_RGMIIDCTL_250_PS 0x0 +#define DP83869_RGMIIDCTL_500_PS 0x1 +#define DP83869_RGMIIDCTL_750_PS 0x2 +#define DP83869_RGMIIDCTL_1_NS 0x3 +#define DP83869_RGMIIDCTL_1_25_NS 0x4 +#define DP83869_RGMIIDCTL_1_50_NS 0x5 +#define DP83869_RGMIIDCTL_1_75_NS 0x6 +#define DP83869_RGMIIDCTL_2_00_NS 0x7 +#define DP83869_RGMIIDCTL_2_25_NS 0x8 +#define DP83869_RGMIIDCTL_2_50_NS 0x9 +#define DP83869_RGMIIDCTL_2_75_NS 0xa +#define DP83869_RGMIIDCTL_3_00_NS 0xb +#define DP83869_RGMIIDCTL_3_25_NS 0xc +#define DP83869_RGMIIDCTL_3_50_NS 0xd +#define DP83869_RGMIIDCTL_3_75_NS 0xe +#define DP83869_RGMIIDCTL_4_00_NS 0xf + /* IO_MUX_CFG - Clock output selection */ #define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0 #define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1