From patchwork Sun Aug 13 00:01:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 109946 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2677222qge; Sat, 12 Aug 2017 17:04:15 -0700 (PDT) X-Received: by 10.80.151.238 with SMTP id f43mr20053427edb.40.1502582655316; Sat, 12 Aug 2017 17:04:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502582655; cv=none; d=google.com; s=arc-20160816; b=ruWS1huhwMyKUoAzwEcHyYWizN2a2uN2cyj2xul9Vxt1reNClaluRmeIPqkeIwyKyr E4bd1RgPzuTqYGsk5rexsAHjb2s1WRe0tbMDR2Adaoi07JXrfCEOxU2hVDOBHySvMOMy coG533qYQiq3IFCD6x1df+aPqSUItOlKzeDLzZjr8RNsfpgw4Jif/qnmhUNqo2QtsMfI So3WtjjckqnBX26RpQCfrdlL17NTvB/7FHDGMxa1D+FVq8hJSNjmw2pd9HeJgjzIjc3V QlD6EjxkM01ilboI1aHYvMaJilVt3WojHsqTOzbnZVHyQhUafzsDdF2xtiq6b1h5KQRt TQnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:message-id:date:to:from :dkim-signature:dkim-filter:arc-authentication-results; bh=DnJooQONQPUee683qnDRUD9M3W7Uxk1us/Rk1vsAQKQ=; b=u4WajoXrOjOt7ywwQ9hbemR+PpqgGe8jsbc2AdaTixANfXmZesziSaLhqFyBtekVAb Ix7OrOSPWZu98TcUdEQafHv/bLImH8E1OR4YCfeaI/EF7Q5OdnHDja4iRyG/oIJNER6/ XDX3QR/0Bt4XrnotaA2f3bKxKYM0nPtCOu1JJJnuN0VYNUiZ0oKRtvkIP+9/ISoLsm7f 3yS5D4ZWDjXzd6BDSqJaTA72Vq2rDBcEyHohMp+PSFVk7N/Ka1H5E0BVSOd9gKrM8dfv 06E68Rxq+q9vIXCcGk25hw4cpBThrNy4J5fZLgApuGMv/JLlPpeIbiI3DSp+wSteSMHD 55oQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=Op9PGOJm; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id a23si3642099edj.166.2017.08.12.17.04.15; Sat, 12 Aug 2017 17:04:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=Op9PGOJm; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id DAFC7C21E2D; Sun, 13 Aug 2017 00:03:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 95E15C21E61; Sun, 13 Aug 2017 00:01:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DA366C21C6A; Sun, 13 Aug 2017 00:01:39 +0000 (UTC) Received: from conuserg-10.nifty.com (conuserg-10.nifty.com [210.131.2.77]) by lists.denx.de (Postfix) with ESMTPS id 6C1C6C21D8C for ; Sun, 13 Aug 2017 00:01:37 +0000 (UTC) Received: from grover.sesame (FL1-122-131-185-176.osk.mesh.ad.jp [122.131.185.176]) (authenticated) by conuserg-10.nifty.com with ESMTP id v7D01JJw005965; Sun, 13 Aug 2017 09:01:19 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v7D01JJw005965 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1502582479; bh=7vRx/L/pV7y3559FMN6Fmafq26qo30Iki2KHSKLZ4tY=; h=From:To:Cc:Subject:Date:From; b=Op9PGOJmKkBrmgWz1IhaO/SwYHofmtNDC++x81EfjtB8khsta0DngM+83lXNS2Mng 3ozC3nr2LBzZfZCY3r4uhzvI5ohmB3a9PVIR/a86u0YC3f1BJlCTqLCtKv/OzE0yfk yO31LN5W+tPcj8mNybVvu8AkPYLIaS1lTdC8cGQG8wlK34xtjP19SmmiDdOQfMGkk4 sSUXX2cRMbmgpMszpOP5Sf0v4BWA8VRMgcGkh6MrYRoy2+Pb3rmydgtBcfvhAimdO5 q3JlkHDD6w4hVEyXObNocky3/WajxtllWK6O/5RRSwDJsPhugLt+DfPzlRiVPiETqx ed13QPlCznOWg== X-Nifty-SrcIP: [122.131.185.176] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Sun, 13 Aug 2017 09:01:13 +0900 Message-Id: <1502582477-27948-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Cc: Albert Aribaud Subject: [U-Boot] [PATCH 1/5] ARM: uniphier: remove sLD3 SoC support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This SoC is too old. It is difficult to maintain any longer. Signed-off-by: Masahiro Yamada --- arch/arm/dts/Makefile | 2 - arch/arm/dts/uniphier-sld3-ref.dts | 100 ----- arch/arm/dts/uniphier-sld3.dtsi | 458 --------------------- arch/arm/mach-uniphier/Kconfig | 4 - arch/arm/mach-uniphier/arm32/cache-uniphier.c | 3 - arch/arm/mach-uniphier/arm32/debug_ll.S | 21 - arch/arm/mach-uniphier/arm32/lowlevel_init.S | 5 +- arch/arm/mach-uniphier/arm32/psci.c | 1 - arch/arm/mach-uniphier/bcu/Makefile | 1 - arch/arm/mach-uniphier/bcu/bcu-sld3.c | 39 -- arch/arm/mach-uniphier/board_init.c | 9 - arch/arm/mach-uniphier/boards.c | 22 - arch/arm/mach-uniphier/boot-device/Makefile | 1 - .../mach-uniphier/boot-device/boot-device-sld3.c | 84 ---- arch/arm/mach-uniphier/boot-device/boot-device.c | 9 - arch/arm/mach-uniphier/boot-device/boot-device.h | 2 - arch/arm/mach-uniphier/clk/Makefile | 14 +- .../clk/{clk-dram-sld3.c => clk-dram-ld4.c} | 2 +- .../clk/{clk-early-sld3.c => clk-early-ld4.c} | 2 +- arch/arm/mach-uniphier/clk/dpll-sld3.c | 13 - arch/arm/mach-uniphier/clk/pll-sld3.c | 14 - arch/arm/mach-uniphier/cpu-info.c | 4 - arch/arm/mach-uniphier/debug-uart/Makefile | 1 - .../arm/mach-uniphier/debug-uart/debug-uart-sld3.c | 31 -- arch/arm/mach-uniphier/debug-uart/debug-uart.c | 5 - arch/arm/mach-uniphier/debug-uart/debug-uart.h | 1 - arch/arm/mach-uniphier/dram/Makefile | 1 - arch/arm/mach-uniphier/dram/umc-sld3.c | 6 - arch/arm/mach-uniphier/dram_init.c | 9 - arch/arm/mach-uniphier/init.h | 10 +- arch/arm/mach-uniphier/memconf.c | 14 +- arch/arm/mach-uniphier/mmc-boot-mode.c | 2 +- arch/arm/mach-uniphier/sc-regs.h | 4 - arch/arm/mach-uniphier/soc-info.h | 1 - arch/arm/mach-uniphier/spl_board_init.c | 29 +- configs/uniphier_sld3_defconfig | 46 --- doc/README.uniphier | 1 - drivers/clk/uniphier/clk-uniphier-core.c | 4 - drivers/clk/uniphier/clk-uniphier-mio.c | 2 - drivers/pinctrl/uniphier/Kconfig | 6 - drivers/pinctrl/uniphier/Makefile | 1 - drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c | 129 ------ drivers/reset/reset-uniphier.c | 14 +- include/configs/uniphier.h | 8 +- 44 files changed, 30 insertions(+), 1105 deletions(-) delete mode 100644 arch/arm/dts/uniphier-sld3-ref.dts delete mode 100644 arch/arm/dts/uniphier-sld3.dtsi delete mode 100644 arch/arm/mach-uniphier/bcu/bcu-sld3.c delete mode 100644 arch/arm/mach-uniphier/boot-device/boot-device-sld3.c rename arch/arm/mach-uniphier/clk/{clk-dram-sld3.c => clk-dram-ld4.c} (93%) rename arch/arm/mach-uniphier/clk/{clk-early-sld3.c => clk-early-ld4.c} (93%) delete mode 100644 arch/arm/mach-uniphier/clk/dpll-sld3.c delete mode 100644 arch/arm/mach-uniphier/clk/pll-sld3.c delete mode 100644 arch/arm/mach-uniphier/debug-uart/debug-uart-sld3.c delete mode 100644 arch/arm/mach-uniphier/dram/umc-sld3.c delete mode 100644 configs/uniphier_sld3_defconfig delete mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c2dc240edf68..8f6b186df828 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -118,8 +118,6 @@ dtb-$(CONFIG_ARCH_UNIPHIER_PXS2) += \ uniphier-pxs2-vodka.dtb dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \ uniphier-pxs3-ref.dtb -dtb-$(CONFIG_ARCH_UNIPHIER_SLD3) += \ - uniphier-sld3-ref.dtb dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \ uniphier-sld8-ref.dtb diff --git a/arch/arm/dts/uniphier-sld3-ref.dts b/arch/arm/dts/uniphier-sld3-ref.dts deleted file mode 100644 index baf706976aca..000000000000 --- a/arch/arm/dts/uniphier-sld3-ref.dts +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Device Tree Source for UniPhier sLD3 Reference Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -/dts-v1/; -/include/ "uniphier-sld3.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier sLD3 Reference Board"; - compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - }; - - memory@8000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000 - 0xc0000000 0x20000000>; - }; -}; - -ðsc { - interrupts = <0 49 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&emmc { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_emmc { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-sld3.dtsi b/arch/arm/dts/uniphier-sld3.dtsi deleted file mode 100644 index 2bb2e029eeeb..000000000000 --- a/arch/arm/dts/uniphier-sld3.dtsi +++ /dev/null @@ -1,458 +0,0 @@ -/* - * Device Tree Source for UniPhier sLD3 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -/ { - compatible = "socionext,uniphier-sld3"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - clocks { - refclk: ref { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24576000>; - }; - - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - u-boot,dm-pre-reloc; - - timer@20000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20000200 0x20>; - interrupts = <1 11 0x304>; - clocks = <&arm_timer_clk>; - }; - - timer@20000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x20000600 0x20>; - interrupts = <1 13 0x304>; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@20001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x20001000 0x1000>, - <0x20000100 0x100>; - }; - - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, - <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(512 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&sys_clk 0>; - clock-frequency = <36864000>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&sys_clk 0>; - clock-frequency = <36864000>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&sys_clk 0>; - clock-frequency = <36864000>; - }; - - port0x: gpio@55000008 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000008 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port1x: gpio@55000010 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000010 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port2x: gpio@55000018 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000018 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port3x: gpio@55000020 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000020 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port4: gpio@55000028 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000028 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port5x: gpio@55000030 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000030 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port6x: gpio@55000038 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000038 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port7x: gpio@55000040 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000040 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port8x: gpio@55000048 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000048 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port9x: gpio@55000050 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000050 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port10x: gpio@55000058 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000058 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port11x: gpio@55000060 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000060 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port12x: gpio@55000068 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000068 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port13x: gpio@55000070 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000070 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port14x: gpio@55000078 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000078 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port16x: gpio@55000088 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000088 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&sys_clk 1>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - clocks = <&sys_clk 1>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - clocks = <&sys_clk 1>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - clocks = <&sys_clk 1>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c4: i2c@58600000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58600000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 1>; - clocks = <&sys_clk 1>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - mioctrl@59810000 { - compatible = "socionext,uniphier-sld3-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - u-boot,dm-pre-reloc; - - mio_clk: clock { - compatible = "socionext,uniphier-sld3-mio-clock"; - #clock-cells = <1>; - u-boot,dm-pre-reloc; - }; - - mio_rst: reset { - compatible = "socionext,uniphier-sld3-mio-reset"; - #reset-cells = <1>; - }; - }; - - emmc: sdhc@5a400000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - reg = <0x5a400000 0x200>; - interrupts = <0 78 4>; - pinctrl-names = "default", "1.8v"; - pinctrl-0 = <&pinctrl_emmc>; - pinctrl-1 = <&pinctrl_emmc_1v8>; - clocks = <&mio_clk 1>; - reset-names = "host", "bridge"; - resets = <&mio_rst 1>, <&mio_rst 4>; - bus-width = <8>; - non-removable; - cap-mmc-highspeed; - cap-mmc-hw-reset; - }; - - sd: sdhc@5a500000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - reg = <0x5a500000 0x200>; - interrupts = <0 76 4>; - pinctrl-names = "default", "1.8v"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio_clk 0>; - reset-names = "host", "bridge"; - resets = <&mio_rst 0>, <&mio_rst 3>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, - <&mio_rst 12>; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, - <&mio_rst 13>; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, - <&mio_rst 14>; - }; - - usb3: usb@5a830100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a830100 0x100>; - interrupts = <0 83 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>, - <&mio_rst 15>; - }; - - soc-glue@5f800000 { - compatible = "socionext,uniphier-sld3-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - u-boot,dm-pre-reloc; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-sld3-pinctrl"; - u-boot,dm-pre-reloc; - }; - }; - - aidet@f1830000 { - compatible = "simple-mfd", "syscon"; - reg = <0xf1830000 0x200>; - }; - - sysctrl@f1840000 { - compatible = "socionext,uniphier-sld3-sysctrl", - "simple-mfd", "syscon"; - reg = <0xf1840000 0x10000>; - - sys_clk: clock { - compatible = "socionext,uniphier-sld3-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset { - compatible = "socionext,uniphier-sld3-reset"; - #reset-cells = <1>; - }; - }; - - nand: nand@f8000000 { - compatible = "socionext,uniphier-denali-nand-v5a"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0xf8000000 0x20>, <0xf8100000 0x1000>; - interrupts = <0 65 4>; - clocks = <&sys_clk 2>; - nand-ecc-strength = <8>; - }; - }; -}; - -/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 3147db76cb68..6a7e239e0d28 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -15,10 +15,6 @@ choice prompt "UniPhier SoC select" default ARCH_UNIPHIER_PRO4 -config ARCH_UNIPHIER_SLD3 - bool "UniPhier sLD3 SoC" - select ARCH_UNIPHIER_32BIT - config ARCH_UNIPHIER_LD4_SLD8 bool "UniPhier LD4/sLD8 SoCs" select ARCH_UNIPHIER_32BIT diff --git a/arch/arm/mach-uniphier/arm32/cache-uniphier.c b/arch/arm/mach-uniphier/arm32/cache-uniphier.c index 658969b04911..3df82bfef008 100644 --- a/arch/arm/mach-uniphier/arm32/cache-uniphier.c +++ b/arch/arm/mach-uniphier/arm32/cache-uniphier.c @@ -197,9 +197,6 @@ void uniphier_cache_set_active_ways(int cpu, u32 active_ways) void __iomem *base = (void __iomem *)UNIPHIER_SSCC + 0xc00; switch (readl(UNIPHIER_SSCID)) { /* revision */ - case 0x11: /* sLD3 */ - base = (void __iomem *)UNIPHIER_SSCC + 0x870; - break; case 0x12: /* LD4 */ case 0x16: /* sld8 */ base = (void __iomem *)UNIPHIER_SSCC + 0x840; diff --git a/arch/arm/mach-uniphier/arm32/debug_ll.S b/arch/arm/mach-uniphier/arm32/debug_ll.S index 76631f2faa22..b39899e6231e 100644 --- a/arch/arm/mach-uniphier/arm32/debug_ll.S +++ b/arch/arm/mach-uniphier/arm32/debug_ll.S @@ -26,27 +26,6 @@ ENTRY(debug_ll_init) and r1, r1, #SG_REVISION_TYPE_MASK mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) -#define UNIPHIER_SLD3_UART_CLK 36864000 - cmp r1, #0x25 - bne sld3_end - - sg_set_pinsel 64, 1, 4, 4, r0, r1 @ TXD0 -> TXD0 - - ldr r0, =BCSCR5 - ldr r1, =0x24440000 - str r1, [r0] - - ldr r0, =SC_CLKCTRL - ldr r1, [r0] - orr r1, r1, #SC_CLKCTRL_CEN_PERI - str r1, [r0] - - ldr r3, =DIV_ROUND(UNIPHIER_SLD3_UART_CLK, 16 * BAUDRATE) - - b init_uart -sld3_end: -#endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) #define UNIPHIER_LD4_UART_CLK 36864000 cmp r1, #0x26 diff --git a/arch/arm/mach-uniphier/arm32/lowlevel_init.S b/arch/arm/mach-uniphier/arm32/lowlevel_init.S index af5ed1c050fe..89bb5a6355fd 100644 --- a/arch/arm/mach-uniphier/arm32/lowlevel_init.S +++ b/arch/arm/mach-uniphier/arm32/lowlevel_init.S @@ -29,9 +29,8 @@ ENTRY(lowlevel_init) /* * Now we are using the page table embedded in the Boot ROM. - * It is not handy since it is not a straight mapped table for sLD3. - * Also, the access to the external bus is prohibited. What we need - * to do next is to create a page table and switch over to it. + * What we need to do next is to create a page table and switch + * over to it. */ bl create_page_table bl __v7_flush_dcache_all diff --git a/arch/arm/mach-uniphier/arm32/psci.c b/arch/arm/mach-uniphier/arm32/psci.c index 65a468dec9f5..3ab101a9cfe8 100644 --- a/arch/arm/mach-uniphier/arm32/psci.c +++ b/arch/arm/mach-uniphier/arm32/psci.c @@ -29,7 +29,6 @@ u32 uniphier_smp_booted[CONFIG_ARMV7_PSCI_NR_CPUS]; static int uniphier_get_nr_cpus(void) { switch (uniphier_get_soc_id()) { - case UNIPHIER_SLD3_ID: case UNIPHIER_PRO4_ID: case UNIPHIER_PRO5_ID: return 2; diff --git a/arch/arm/mach-uniphier/bcu/Makefile b/arch/arm/mach-uniphier/bcu/Makefile index 02107b376ac8..5a9d8d72728b 100644 --- a/arch/arm/mach-uniphier/bcu/Makefile +++ b/arch/arm/mach-uniphier/bcu/Makefile @@ -2,6 +2,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += bcu-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_LD4) += bcu-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += bcu-ld4.o diff --git a/arch/arm/mach-uniphier/bcu/bcu-sld3.c b/arch/arm/mach-uniphier/bcu/bcu-sld3.c deleted file mode 100644 index 99b318fd8f74..000000000000 --- a/arch/arm/mach-uniphier/bcu/bcu-sld3.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2011-2014 Panasonic Corporation - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#include "../init.h" -#include "bcu-regs.h" - -#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) - -void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd) -{ - int shift; - - writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ - writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ - writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ - /* - * 0xe0000000-0xefffffff: Ex-bus - * 0xf0000000-0xfbffffff: ASM bus - * 0xfc000000-0xffffffff: OCM bus - */ - writel(0x24440000, BCSCR5); - - /* Specify DDR channel */ - shift = bd->dram_ch[0].size / 0x04000000 * 4; - writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ - - shift -= 32; - writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ - - shift -= 32; - writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ -} diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c index 884bc67654d4..ed58d07f7e50 100644 --- a/arch/arm/mach-uniphier/board_init.c +++ b/arch/arm/mach-uniphier/board_init.c @@ -86,15 +86,6 @@ struct uniphier_initdata { }; static const struct uniphier_initdata uniphier_initdata[] = { -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) - { - .soc_id = UNIPHIER_SLD3_ID, - .nand_2cs = true, - .sbc_init = uniphier_sbc_init_admulti, - .pll_init = uniphier_sld3_pll_init, - .clk_init = uniphier_ld4_clk_init, - }, -#endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) { .soc_id = UNIPHIER_LD4_ID, diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index 78de256a01e5..9bfc4c254196 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -13,25 +13,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) -static const struct uniphier_board_data uniphier_sld3_data = { - .dram_freq = 1600, - .dram_ch[0] = { - .size = 0x20000000, - .width = 32, - }, - .dram_ch[1] = { - .size = 0x20000000, - .width = 16, - }, - .dram_ch[2] = { - .size = 0x10000000, - .width = 16, - }, - .flags = UNIPHIER_BD_DRAM_SPARSE, -}; -#endif - #if defined(CONFIG_ARCH_UNIPHIER_LD4) static const struct uniphier_board_data uniphier_ld4_data = { .dram_freq = 1600, @@ -146,9 +127,6 @@ struct uniphier_board_id { }; static const struct uniphier_board_id uniphier_boards[] = { -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) - { "socionext,uniphier-sld3", &uniphier_sld3_data, }, -#endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) { "socionext,uniphier-ld4", &uniphier_ld4_data, }, #endif diff --git a/arch/arm/mach-uniphier/boot-device/Makefile b/arch/arm/mach-uniphier/boot-device/Makefile index b35729213032..6c8580ce791e 100644 --- a/arch/arm/mach-uniphier/boot-device/Makefile +++ b/arch/arm/mach-uniphier/boot-device/Makefile @@ -4,7 +4,6 @@ obj-y += boot-device.o -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += boot-device-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_LD4) += boot-device-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += boot-device-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += boot-device-ld4.o diff --git a/arch/arm/mach-uniphier/boot-device/boot-device-sld3.c b/arch/arm/mach-uniphier/boot-device/boot-device-sld3.c deleted file mode 100644 index 2b36494f7343..000000000000 --- a/arch/arm/mach-uniphier/boot-device/boot-device-sld3.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (C) 2014 Panasonic Corporation - * Copyright (C) 2015-2017 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#include "boot-device.h" - -const struct uniphier_boot_device uniphier_sld3_boot_device_table[] = { - {BOOT_DEVICE_NOR, "NOR (XECS0)"}, - {BOOT_DEVICE_NONE, "External Master"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, -}; - -const unsigned uniphier_sld3_boot_device_count = - ARRAY_SIZE(uniphier_sld3_boot_device_table); diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c index 094f77b4d10e..0f93926f28fa 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device.c @@ -26,15 +26,6 @@ struct uniphier_boot_device_info { }; static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) - { - .soc_id = UNIPHIER_SLD3_ID, - .boot_device_sel_shift = 0, - .boot_device_table = uniphier_sld3_boot_device_table, - .boot_device_count = &uniphier_sld3_boot_device_count, - .have_internal_stm = 0, - }, -#endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) { .soc_id = UNIPHIER_LD4_ID, diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.h b/arch/arm/mach-uniphier/boot-device/boot-device.h index c4ce3e50a378..f9631d682089 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.h +++ b/arch/arm/mach-uniphier/boot-device/boot-device.h @@ -13,14 +13,12 @@ struct uniphier_boot_device { const char *desc; }; -extern const struct uniphier_boot_device uniphier_sld3_boot_device_table[]; extern const struct uniphier_boot_device uniphier_ld4_boot_device_table[]; extern const struct uniphier_boot_device uniphier_pro5_boot_device_table[]; extern const struct uniphier_boot_device uniphier_pxs2_boot_device_table[]; extern const struct uniphier_boot_device uniphier_ld11_boot_device_table[]; extern const struct uniphier_boot_device uniphier_pxs3_boot_device_table[]; -extern const unsigned int uniphier_sld3_boot_device_count; extern const unsigned int uniphier_ld4_boot_device_count; extern const unsigned int uniphier_pro5_boot_device_count; extern const unsigned int uniphier_pxs2_boot_device_count; diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index 1680dddd6e68..76633bcd498a 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -4,17 +4,15 @@ ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-early-sld3.o clk-dram-sld3.o dpll-sld3.o -obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-sld3.o clk-dram-sld3.o dpll-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-sld3.o clk-dram-sld3.o dpll-pro4.o -obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-sld3.o clk-dram-sld3.o dpll-sld8.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-sld3.o clk-dram-pro5.o dpll-pro5.o -obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o +obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o +obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o else -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-ld4.o pll-sld3.o dpll-tail.o obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o diff --git a/arch/arm/mach-uniphier/clk/clk-dram-sld3.c b/arch/arm/mach-uniphier/clk/clk-dram-ld4.c similarity index 93% rename from arch/arm/mach-uniphier/clk/clk-dram-sld3.c rename to arch/arm/mach-uniphier/clk/clk-dram-ld4.c index 3430303f875a..407daf066425 100644 --- a/arch/arm/mach-uniphier/clk/clk-dram-sld3.c +++ b/arch/arm/mach-uniphier/clk/clk-dram-ld4.c @@ -12,7 +12,7 @@ #include "../init.h" #include "../sc-regs.h" -void uniphier_sld3_dram_clk_init(void) +void uniphier_ld4_dram_clk_init(void) { u32 tmp; diff --git a/arch/arm/mach-uniphier/clk/clk-early-sld3.c b/arch/arm/mach-uniphier/clk/clk-early-ld4.c similarity index 93% rename from arch/arm/mach-uniphier/clk/clk-early-sld3.c rename to arch/arm/mach-uniphier/clk/clk-early-ld4.c index 3235da20bcb9..07b916dc9a9c 100644 --- a/arch/arm/mach-uniphier/clk/clk-early-sld3.c +++ b/arch/arm/mach-uniphier/clk/clk-early-ld4.c @@ -12,7 +12,7 @@ #include "../init.h" #include "../sc-regs.h" -void uniphier_sld3_early_clk_init(void) +void uniphier_ld4_early_clk_init(void) { u32 tmp; diff --git a/arch/arm/mach-uniphier/clk/dpll-sld3.c b/arch/arm/mach-uniphier/clk/dpll-sld3.c deleted file mode 100644 index 0eb310ceb8f3..000000000000 --- a/arch/arm/mach-uniphier/clk/dpll-sld3.c +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include "../init.h" - -int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd) -{ - /* add pll init code here */ - return 0; -} diff --git a/arch/arm/mach-uniphier/clk/pll-sld3.c b/arch/arm/mach-uniphier/clk/pll-sld3.c deleted file mode 100644 index 37a7c1278251..000000000000 --- a/arch/arm/mach-uniphier/clk/pll-sld3.c +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include "../init.h" -#include "pll.h" - -void uniphier_sld3_pll_init(void) -{ - uniphier_ld4_dpll_ssc_en(); -} diff --git a/arch/arm/mach-uniphier/cpu-info.c b/arch/arm/mach-uniphier/cpu-info.c index 2ce73c5af888..90ef4110871f 100644 --- a/arch/arm/mach-uniphier/cpu-info.c +++ b/arch/arm/mach-uniphier/cpu-info.c @@ -23,10 +23,6 @@ int print_cpuinfo(void) puts("SoC: "); switch (id) { - case UNIPHIER_SLD3_ID: - puts("sLD3"); - required_model = 2; - break; case UNIPHIER_LD4_ID: puts("LD4"); required_rev = 2; diff --git a/arch/arm/mach-uniphier/debug-uart/Makefile b/arch/arm/mach-uniphier/debug-uart/Makefile index 0bad718de66b..3837ee7ec6db 100644 --- a/arch/arm/mach-uniphier/debug-uart/Makefile +++ b/arch/arm/mach-uniphier/debug-uart/Makefile @@ -3,7 +3,6 @@ # ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += debug-uart-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_LD4) += debug-uart-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += debug-uart-pro4.o obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += debug-uart-sld8.o diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-sld3.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-sld3.c deleted file mode 100644 index 508318a6820c..000000000000 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart-sld3.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (C) 2016 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "../bcu/bcu-regs.h" -#include "../sc-regs.h" -#include "../sg-regs.h" -#include "debug-uart.h" - -#define UNIPHIER_SLD3_UART_CLK 36864000 - -unsigned int uniphier_sld3_debug_uart_init(void) -{ - u32 tmp; - - sg_set_pinsel(64, 1, 4, 4); /* TXD0 -> TXD0 */ - - writel(0x24440000, BCSCR5); - - tmp = readl(SC_CLKCTRL); - tmp |= SC_CLKCTRL_CEN_PERI; - writel(tmp, SC_CLKCTRL); - - return DIV_ROUND_CLOSEST(UNIPHIER_SLD3_UART_CLK, 16 * CONFIG_BAUDRATE); -} diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.c b/arch/arm/mach-uniphier/debug-uart/debug-uart.c index 72a514dc0e81..94d05a8b9c01 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c @@ -33,11 +33,6 @@ void _debug_uart_init(void) unsigned int divisor; switch (uniphier_get_soc_id()) { -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) - case UNIPHIER_SLD3_ID: - divisor = uniphier_sld3_debug_uart_init(); - break; -#endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) case UNIPHIER_LD4_ID: divisor = uniphier_ld4_debug_uart_init(); diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.h b/arch/arm/mach-uniphier/debug-uart/debug-uart.h index 8de9124b02df..d57e5df3db17 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart.h +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.h @@ -7,7 +7,6 @@ #ifndef _MACH_DEBUG_UART_H #define _MACH_DEBUG_UART_H -unsigned int uniphier_sld3_debug_uart_init(void); unsigned int uniphier_ld4_debug_uart_init(void); unsigned int uniphier_pro4_debug_uart_init(void); unsigned int uniphier_sld8_debug_uart_init(void); diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile index 1da33f6d80a1..baf2a7b481bb 100644 --- a/arch/arm/mach-uniphier/dram/Makefile +++ b/arch/arm/mach-uniphier/dram/Makefile @@ -4,7 +4,6 @@ ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += umc-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_LD4) += umc-ld4.o \ ddrphy-training.o ddrphy-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += umc-pro4.o \ diff --git a/arch/arm/mach-uniphier/dram/umc-sld3.c b/arch/arm/mach-uniphier/dram/umc-sld3.c deleted file mode 100644 index 99249eb20168..000000000000 --- a/arch/arm/mach-uniphier/dram/umc-sld3.c +++ /dev/null @@ -1,6 +0,0 @@ -#include "../init.h" - -int uniphier_sld3_umc_init(const struct uniphier_board_data *bd) -{ - return 0; -} diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 6eb8d2650424..32d359321ae2 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -28,15 +28,6 @@ struct uniphier_memif_data { static const struct uniphier_memif_data uniphier_memif_data[] = { { - .soc_id = UNIPHIER_SLD3_ID, - .sparse_ch1_base = 0xc0000000, - /* - * In fact, SLD3 has DRAM ch2, but the memory regions for ch1 - * and ch2 overlap, and host cannot get access to them at the - * same time. Hide the ch2 from U-Boot. - */ - }, - { .soc_id = UNIPHIER_LD4_ID, .sparse_ch1_base = 0xc0000000, }, diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index b322628eedfa..29f638d94703 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -28,7 +28,6 @@ struct uniphier_board_data { const struct uniphier_board_data *uniphier_get_board_param(void); -int uniphier_sld3_init(const struct uniphier_board_data *bd); int uniphier_ld4_init(const struct uniphier_board_data *bd); int uniphier_pro4_init(const struct uniphier_board_data *bd); int uniphier_sld8_init(const struct uniphier_board_data *bd); @@ -63,34 +62,29 @@ static inline void uniphier_ld11_sbc_init(void) } #endif -void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd); void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd); int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd); -int uniphier_memconf_3ch_no_disbit_init(const struct uniphier_board_data *bd); int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd); -int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd); int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd); int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd); int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd); int uniphier_pro5_dpll_init(const struct uniphier_board_data *bd); int uniphier_pxs2_dpll_init(const struct uniphier_board_data *bd); -void uniphier_sld3_early_clk_init(void); +void uniphier_ld4_early_clk_init(void); -void uniphier_sld3_dram_clk_init(void); +void uniphier_ld4_dram_clk_init(void); void uniphier_pro5_dram_clk_init(void); void uniphier_pxs2_dram_clk_init(void); -int uniphier_sld3_umc_init(const struct uniphier_board_data *bd); int uniphier_ld4_umc_init(const struct uniphier_board_data *bd); int uniphier_pro4_umc_init(const struct uniphier_board_data *bd); int uniphier_sld8_umc_init(const struct uniphier_board_data *bd); int uniphier_pro5_umc_init(const struct uniphier_board_data *bd); int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd); -void uniphier_sld3_pll_init(void); void uniphier_ld4_pll_init(void); void uniphier_pro4_pll_init(void); void uniphier_ld11_pll_init(void); diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c index 4ced2cbace03..3b34e4d37294 100644 --- a/arch/arm/mach-uniphier/memconf.c +++ b/arch/arm/mach-uniphier/memconf.c @@ -15,7 +15,7 @@ #include "init.h" static int __uniphier_memconf_init(const struct uniphier_board_data *bd, - int have_ch2, int have_ch2_disable_bit) + int have_ch2) { u32 val = 0; unsigned long size_per_word; @@ -100,8 +100,7 @@ static int __uniphier_memconf_init(const struct uniphier_board_data *bd, goto out; if (!bd->dram_ch[2].size) { - if (have_ch2_disable_bit) - val |= SG_MEMCONF_CH2_DISABLE; + val |= SG_MEMCONF_CH2_DISABLE; goto out; } @@ -149,15 +148,10 @@ out: int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd) { - return __uniphier_memconf_init(bd, 0, 0); -} - -int uniphier_memconf_3ch_no_disbit_init(const struct uniphier_board_data *bd) -{ - return __uniphier_memconf_init(bd, 1, 0); + return __uniphier_memconf_init(bd, 0); } int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd) { - return __uniphier_memconf_init(bd, 1, 1); + return __uniphier_memconf_init(bd, 1); } diff --git a/arch/arm/mach-uniphier/mmc-boot-mode.c b/arch/arm/mach-uniphier/mmc-boot-mode.c index d60c578ce7fe..f40534eebb9f 100644 --- a/arch/arm/mach-uniphier/mmc-boot-mode.c +++ b/arch/arm/mach-uniphier/mmc-boot-mode.c @@ -14,7 +14,7 @@ u32 spl_boot_mode(const u32 boot_device) struct mmc *mmc; /* - * work around a bug in the Boot ROM of PH1-sLD3, LD4, Pro4, and sLD8: + * work around a bug in the Boot ROM of LD4, Pro4, and sLD8: * * The boot ROM in these SoCs breaks the PARTITION_CONFIG [179] of * Extended CSD register; when switching to the Boot Partition 1, the diff --git a/arch/arm/mach-uniphier/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h index ad58e10e23d0..54bbe43ebbad 100644 --- a/arch/arm/mach-uniphier/sc-regs.h +++ b/arch/arm/mach-uniphier/sc-regs.h @@ -11,11 +11,7 @@ #ifndef ARCH_SC_REGS_H #define ARCH_SC_REGS_H -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) -#define SC_BASE_ADDR 0xf1840000 -#else #define SC_BASE_ADDR 0x61840000 -#endif #define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110) #define SC_DPLLOSCCTRL_DPLLST (0x1 << 1) diff --git a/arch/arm/mach-uniphier/soc-info.h b/arch/arm/mach-uniphier/soc-info.h index 04732527a75e..9ba6a7ed6934 100644 --- a/arch/arm/mach-uniphier/soc-info.h +++ b/arch/arm/mach-uniphier/soc-info.h @@ -11,7 +11,6 @@ #include #include -#define UNIPHIER_SLD3_ID 0x25 #define UNIPHIER_LD4_ID 0x26 #define UNIPHIER_PRO4_ID 0x28 #define UNIPHIER_SLD8_ID 0x29 diff --git a/arch/arm/mach-uniphier/spl_board_init.c b/arch/arm/mach-uniphier/spl_board_init.c index 6da5631bcace..1272b4e25c08 100644 --- a/arch/arm/mach-uniphier/spl_board_init.c +++ b/arch/arm/mach-uniphier/spl_board_init.c @@ -24,35 +24,24 @@ struct uniphier_spl_initdata { }; static const struct uniphier_spl_initdata uniphier_spl_initdata[] = { -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) - { - .soc_id = UNIPHIER_SLD3_ID, - .bcu_init = uniphier_sld3_bcu_init, - .early_clk_init = uniphier_sld3_early_clk_init, - .dpll_init = uniphier_sld3_dpll_init, - .memconf_init = uniphier_memconf_3ch_no_disbit_init, - .dram_clk_init = uniphier_sld3_dram_clk_init, - .umc_init = uniphier_sld3_umc_init, - }, -#endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) { .soc_id = UNIPHIER_LD4_ID, .bcu_init = uniphier_ld4_bcu_init, - .early_clk_init = uniphier_sld3_early_clk_init, + .early_clk_init = uniphier_ld4_early_clk_init, .dpll_init = uniphier_ld4_dpll_init, .memconf_init = uniphier_memconf_2ch_init, - .dram_clk_init = uniphier_sld3_dram_clk_init, + .dram_clk_init = uniphier_ld4_dram_clk_init, .umc_init = uniphier_ld4_umc_init, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO4) { .soc_id = UNIPHIER_PRO4_ID, - .early_clk_init = uniphier_sld3_early_clk_init, + .early_clk_init = uniphier_ld4_early_clk_init, .dpll_init = uniphier_pro4_dpll_init, .memconf_init = uniphier_memconf_2ch_init, - .dram_clk_init = uniphier_sld3_dram_clk_init, + .dram_clk_init = uniphier_ld4_dram_clk_init, .umc_init = uniphier_pro4_umc_init, }, #endif @@ -60,17 +49,17 @@ static const struct uniphier_spl_initdata uniphier_spl_initdata[] = { { .soc_id = UNIPHIER_SLD8_ID, .bcu_init = uniphier_ld4_bcu_init, - .early_clk_init = uniphier_sld3_early_clk_init, + .early_clk_init = uniphier_ld4_early_clk_init, .dpll_init = uniphier_sld8_dpll_init, .memconf_init = uniphier_memconf_2ch_init, - .dram_clk_init = uniphier_sld3_dram_clk_init, + .dram_clk_init = uniphier_ld4_dram_clk_init, .umc_init = uniphier_sld8_umc_init, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO5) { .soc_id = UNIPHIER_PRO5_ID, - .early_clk_init = uniphier_sld3_early_clk_init, + .early_clk_init = uniphier_ld4_early_clk_init, .dpll_init = uniphier_pro5_dpll_init, .memconf_init = uniphier_memconf_2ch_init, .dram_clk_init = uniphier_pro5_dram_clk_init, @@ -80,7 +69,7 @@ static const struct uniphier_spl_initdata uniphier_spl_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_PXS2) { .soc_id = UNIPHIER_PXS2_ID, - .early_clk_init = uniphier_sld3_early_clk_init, + .early_clk_init = uniphier_ld4_early_clk_init, .dpll_init = uniphier_pxs2_dpll_init, .memconf_init = uniphier_memconf_3ch_init, .dram_clk_init = uniphier_pxs2_dram_clk_init, @@ -90,7 +79,7 @@ static const struct uniphier_spl_initdata uniphier_spl_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD6B) { .soc_id = UNIPHIER_LD6B_ID, - .early_clk_init = uniphier_sld3_early_clk_init, + .early_clk_init = uniphier_ld4_early_clk_init, .dpll_init = uniphier_pxs2_dpll_init, .memconf_init = uniphier_memconf_3ch_init, .dram_clk_init = uniphier_pxs2_dram_clk_init, diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig deleted file mode 100644 index 6340b6a40dc2..000000000000 --- a/configs/uniphier_sld3_defconfig +++ /dev/null @@ -1,46 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_UNIPHIER=y -CONFIG_SYS_TEXT_BASE=0x84000000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_ARCH_UNIPHIER_SLD3=y -CONFIG_MICRO_SUPPORT_CARD=y -CONFIG_DEFAULT_DEVICE_TREE="uniphier-sld3-ref" -# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -CONFIG_SPL=y -CONFIG_SPL_NOR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_CONFIG=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_ENV_EXISTS is not set -CONFIG_CMD_GPT=y -CONFIG_CMD_MMC=y -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -# CONFIG_CMD_FPGA is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -# CONFIG_CMD_MISC is not set -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_GPIO_UNIPHIER=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_MMC_UNIPHIER=y -CONFIG_NAND_DENALI=y -CONFIG_SYS_NAND_DENALI_64BIT=y -CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 -CONFIG_SPL_NAND_DENALI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_STORAGE=y diff --git a/doc/README.uniphier b/doc/README.uniphier index f21c9d09ce3e..fa1f9bcc9667 100644 --- a/doc/README.uniphier +++ b/doc/README.uniphier @@ -29,7 +29,6 @@ The following tables show and for each board. Board | | ---------------|------------------------------|------------------------------ -sLD3 reference | uniphier_sld3_defconfig | uniphier-sld3-ref (default) LD4 reference | uniphier_ld4_sld8_defconfig | uniphier-ld4-ref (default) sld8 reference | uniphier_ld4_sld8_defconfig | uniphier-sld8-def Pro4 reference | uniphier_pro4_defconfig | uniphier-pro4-ref (default) diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index 0fb48541b9b7..eed21b9a6871 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -147,10 +147,6 @@ static int uniphier_clk_probe(struct udevice *dev) static const struct udevice_id uniphier_clk_match[] = { { - .compatible = "socionext,uniphier-sld3-mio-clock", - .data = (ulong)&uniphier_mio_clk_data, - }, - { .compatible = "socionext,uniphier-ld4-mio-clock", .data = (ulong)&uniphier_mio_clk_data, }, diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c index 18e685670925..9c13dcd55518 100644 --- a/drivers/clk/uniphier/clk-uniphier-mio.c +++ b/drivers/clk/uniphier/clk-uniphier-mio.c @@ -64,11 +64,9 @@ static const struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = { UNIPHIER_MIO_CLK_USB2(8, 0), UNIPHIER_MIO_CLK_USB2(9, 1), UNIPHIER_MIO_CLK_USB2(10, 2), - UNIPHIER_MIO_CLK_USB2(11, 3), /* for PH1-sLD3 only */ UNIPHIER_MIO_CLK_USB2_PHY(12, 0), UNIPHIER_MIO_CLK_USB2_PHY(13, 1), UNIPHIER_MIO_CLK_USB2_PHY(14, 2), - UNIPHIER_MIO_CLK_USB2_PHY(15, 3), /* for PH1-sLD3 only */ UNIPHIER_CLK_END }; diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index a6e51caba5f5..b6abcd12ff3d 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -3,12 +3,6 @@ if ARCH_UNIPHIER config PINCTRL_UNIPHIER bool -config PINCTRL_UNIPHIER_SLD3 - bool "UniPhier sLD3 SoC pinctrl driver" - depends on ARCH_UNIPHIER_SLD3 - default y - select PINCTRL_UNIPHIER - config PINCTRL_UNIPHIER_LD4 bool "UniPhier LD4 SoC pinctrl driver" depends on ARCH_UNIPHIER_LD4 diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index b805765ed1ce..215104b61b49 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -4,7 +4,6 @@ obj-y += pinctrl-uniphier-core.o -obj-$(CONFIG_PINCTRL_UNIPHIER_SLD3) += pinctrl-uniphier-sld3.o obj-$(CONFIG_PINCTRL_UNIPHIER_LD4) += pinctrl-uniphier-ld4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PRO4) += pinctrl-uniphier-pro4.o obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8) += pinctrl-uniphier-sld8.o diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c deleted file mode 100644 index e9cc9d205d83..000000000000 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "pinctrl-uniphier.h" - -static const unsigned emmc_pins[] = {55, 56, 60}; -static const int emmc_muxvals[] = {1, 1, 1}; -static const unsigned emmc_dat8_pins[] = {57}; -static const int emmc_dat8_muxvals[] = {1}; -static const unsigned ether_mii_pins[] = {35, 107, 108, 109, 110, 111, 112, - 113}; -static const int ether_mii_muxvals[] = {1, 2, 2, 2, 2, 2, 2, 2}; -static const unsigned ether_rmii_pins[] = {35}; -static const int ether_rmii_muxvals[] = {1}; -static const unsigned i2c0_pins[] = {36}; -static const int i2c0_muxvals[] = {0}; -static const unsigned nand_pins[] = {38, 39, 40, 58, 59}; -static const int nand_muxvals[] = {1, 1, 1, 1, 1}; -static const unsigned nand_cs1_pins[] = {41}; -static const int nand_cs1_muxvals[] = {1}; -static const unsigned sd_pins[] = {42, 43, 44, 45}; -static const int sd_muxvals[] = {1, 1, 1, 1}; -static const unsigned system_bus_pins[] = {46, 50, 51, 53, 54, 73, 74, 75, 76, - 77, 78, 79, 80, 88, 89, 91, 92, 99}; -static const int system_bus_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1}; -static const unsigned system_bus_cs0_pins[] = {93}; -static const int system_bus_cs0_muxvals[] = {1}; -static const unsigned system_bus_cs1_pins[] = {94}; -static const int system_bus_cs1_muxvals[] = {1}; -static const unsigned system_bus_cs2_pins[] = {95}; -static const int system_bus_cs2_muxvals[] = {1}; -static const unsigned system_bus_cs3_pins[] = {96}; -static const int system_bus_cs3_muxvals[] = {1}; -static const unsigned system_bus_cs4_pins[] = {81}; -static const int system_bus_cs4_muxvals[] = {1}; -static const unsigned system_bus_cs5_pins[] = {82}; -static const int system_bus_cs5_muxvals[] = {1}; -static const unsigned uart0_pins[] = {63, 64}; -static const int uart0_muxvals[] = {0, 1}; -static const unsigned uart1_pins[] = {65, 66}; -static const int uart1_muxvals[] = {0, 1}; -static const unsigned uart2_pins[] = {96, 102}; -static const int uart2_muxvals[] = {2, 2}; -static const unsigned usb0_pins[] = {13, 14}; -static const int usb0_muxvals[] = {0, 1}; -static const unsigned usb1_pins[] = {15, 16}; -static const int usb1_muxvals[] = {0, 1}; -static const unsigned usb2_pins[] = {17, 18}; -static const int usb2_muxvals[] = {0, 1}; -static const unsigned usb3_pins[] = {19, 20}; -static const int usb3_muxvals[] = {0, 1}; - -static const struct uniphier_pinctrl_group uniphier_sld3_groups[] = { - UNIPHIER_PINCTRL_GROUP_SPL(emmc), - UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8), - UNIPHIER_PINCTRL_GROUP(ether_mii), - UNIPHIER_PINCTRL_GROUP(ether_rmii), - UNIPHIER_PINCTRL_GROUP(i2c0), - UNIPHIER_PINCTRL_GROUP(nand), - UNIPHIER_PINCTRL_GROUP(nand_cs1), - UNIPHIER_PINCTRL_GROUP(sd), - UNIPHIER_PINCTRL_GROUP(system_bus), - UNIPHIER_PINCTRL_GROUP(system_bus_cs0), - UNIPHIER_PINCTRL_GROUP(system_bus_cs1), - UNIPHIER_PINCTRL_GROUP(system_bus_cs2), - UNIPHIER_PINCTRL_GROUP(system_bus_cs3), - UNIPHIER_PINCTRL_GROUP(system_bus_cs4), - UNIPHIER_PINCTRL_GROUP(system_bus_cs5), - UNIPHIER_PINCTRL_GROUP_SPL(uart0), - UNIPHIER_PINCTRL_GROUP_SPL(uart1), - UNIPHIER_PINCTRL_GROUP_SPL(uart2), - UNIPHIER_PINCTRL_GROUP(usb0), - UNIPHIER_PINCTRL_GROUP(usb1), - UNIPHIER_PINCTRL_GROUP(usb2), - UNIPHIER_PINCTRL_GROUP(usb3) -}; - -static const char * const uniphier_sld3_functions[] = { - UNIPHIER_PINMUX_FUNCTION_SPL(emmc), - UNIPHIER_PINMUX_FUNCTION(ether_mii), - UNIPHIER_PINMUX_FUNCTION(ether_rmii), - UNIPHIER_PINMUX_FUNCTION(i2c0), - UNIPHIER_PINMUX_FUNCTION(nand), - UNIPHIER_PINMUX_FUNCTION(sd), - UNIPHIER_PINMUX_FUNCTION(system_bus), - UNIPHIER_PINMUX_FUNCTION_SPL(uart0), - UNIPHIER_PINMUX_FUNCTION_SPL(uart1), - UNIPHIER_PINMUX_FUNCTION_SPL(uart2), - UNIPHIER_PINMUX_FUNCTION(usb0), - UNIPHIER_PINMUX_FUNCTION(usb1), - UNIPHIER_PINMUX_FUNCTION(usb2), - UNIPHIER_PINMUX_FUNCTION(usb3), -}; - -static struct uniphier_pinctrl_socdata uniphier_sld3_pinctrl_socdata = { - .groups = uniphier_sld3_groups, - .groups_count = ARRAY_SIZE(uniphier_sld3_groups), - .functions = uniphier_sld3_functions, - .functions_count = ARRAY_SIZE(uniphier_sld3_functions), - .caps = UNIPHIER_PINCTRL_CAPS_MUX_4BIT, -}; - -static int uniphier_sld3_pinctrl_probe(struct udevice *dev) -{ - return uniphier_pinctrl_probe(dev, &uniphier_sld3_pinctrl_socdata); -} - -static const struct udevice_id uniphier_sld3_pinctrl_match[] = { - { .compatible = "socionext,uniphier-sld3-pinctrl" }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(uniphier_sld3_pinctrl) = { - .name = "uniphier-sld3-pinctrl", - .id = UCLASS_PINCTRL, - .of_match = of_match_ptr(uniphier_sld3_pinctrl_match), - .probe = uniphier_sld3_pinctrl_probe, - .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), - .ops = &uniphier_pinctrl_ops, -}; diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index 17e971a427f9..df7fa267d13c 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -56,7 +56,7 @@ struct uniphier_reset_data { #define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \ UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17) -static const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = { +static const struct uniphier_reset_data uniphier_ld4_sys_reset_data[] = { UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */ UNIPHIER_RESET_END, }; @@ -270,12 +270,8 @@ static int uniphier_reset_probe(struct udevice *dev) static const struct udevice_id uniphier_reset_match[] = { /* System reset */ { - .compatible = "socionext,uniphier-sld3-reset", - .data = (ulong)uniphier_sld3_sys_reset_data, - }, - { .compatible = "socionext,uniphier-ld4-reset", - .data = (ulong)uniphier_sld3_sys_reset_data, + .data = (ulong)uniphier_ld4_sys_reset_data, }, { .compatible = "socionext,uniphier-pro4-reset", @@ -283,7 +279,7 @@ static const struct udevice_id uniphier_reset_match[] = { }, { .compatible = "socionext,uniphier-sld8-reset", - .data = (ulong)uniphier_sld3_sys_reset_data, + .data = (ulong)uniphier_ld4_sys_reset_data, }, { .compatible = "socionext,uniphier-pro5-reset", @@ -303,10 +299,6 @@ static const struct udevice_id uniphier_reset_match[] = { }, /* Media I/O reset */ { - .compatible = "socionext,uniphier-sld3-mio-clock", - .data = (ulong)uniphier_mio_reset_data, - }, - { .compatible = "socionext,uniphier-ld4-mio-reset", .data = (ulong)uniphier_mio_reset_data, }, diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 6f5313931ab9..9a64063c3ee6 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -88,13 +88,8 @@ #define CONFIG_NAND_DENALI_ECC_SIZE 1024 -#ifdef CONFIG_ARCH_UNIPHIER_SLD3 -#define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 -#define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 -#else #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 -#endif #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) @@ -249,8 +244,7 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) /* only for SPL */ -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ - defined(CONFIG_ARCH_UNIPHIER_LD4) || \ +#if defined(CONFIG_ARCH_UNIPHIER_LD4) || \ defined(CONFIG_ARCH_UNIPHIER_SLD8) #define CONFIG_SPL_TEXT_BASE 0x00040000 #else From patchwork Sun Aug 13 00:01:14 2017 Content-Type: text/plain; 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[81.169.180.215]) by mx.google.com with ESMTP id l18si3325142edj.524.2017.08.12.17.03.20; Sat, 12 Aug 2017 17:03:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=LxLdph2y; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 41DE2C21E1E; Sun, 13 Aug 2017 00:02:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D55E4C21DFB; Sun, 13 Aug 2017 00:01:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BA042C21C6A; Sun, 13 Aug 2017 00:01:38 +0000 (UTC) Received: from conuserg-10.nifty.com (conuserg-10.nifty.com [210.131.2.77]) by lists.denx.de (Postfix) with ESMTPS id 6B8E4C21D76 for ; Sun, 13 Aug 2017 00:01:37 +0000 (UTC) Received: from grover.sesame (FL1-122-131-185-176.osk.mesh.ad.jp [122.131.185.176]) (authenticated) by conuserg-10.nifty.com with ESMTP id v7D01JJx005965; Sun, 13 Aug 2017 09:01:19 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v7D01JJx005965 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1502582480; bh=omV0ik08xyiQQsvzRqPmyikEnV/XFu4suhrPHiAsntQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LxLdph2yt6oVqLLr6Xac1+j4k/pEo+MZpTWCJEnEMRiDrCByk3AgQ8rllthX9t3cT Cr84tljV1iPVsS4eUd8S4JMvLBXMn+rMzhflp/WP9JMPqWb9ycBSn7NBBSPMd3qE2Y WofNP6e4vtatW202RxnWBFivsyaGO1dPiXT1bj4OMY6W+a25C9QK/0AaeKXyyOkeSP 9giHTJyUWZwNMwor2fIgRVom93oVVHrHz+mVfDpS7dspgG1o1hIuDVws2qjeNb38dO 3Vecz3MAqhkParjQeDBwTBOydM7LiUzatwO5p4FcSxheKHuS/7B5O3foDFyqLy2vs7 gi7uxI3JQ/K4Q== X-Nifty-SrcIP: [122.131.185.176] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Sun, 13 Aug 2017 09:01:14 +0900 Message-Id: <1502582477-27948-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1502582477-27948-1-git-send-email-yamada.masahiro@socionext.com> References: <1502582477-27948-1-git-send-email-yamada.masahiro@socionext.com> Cc: Albert Aribaud Subject: [U-Boot] [PATCH 2/5] Revert "ARM: uniphier: move lowlevel debug init code after page table switch" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This reverts commit bcc51c1512a3deb6a9fdd37362c6dde32ad3da23. Commit bcc51c1512a3 ("ARM: uniphier: move lowlevel debug init code after page table switch") was intended to support lowlevel debug for sLD3. Now the sLD3 SoC support has been removed. Revert it to allow to enable lowlevel debug earlier. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/arm32/lowlevel_init.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-uniphier/arm32/lowlevel_init.S b/arch/arm/mach-uniphier/arm32/lowlevel_init.S index 89bb5a6355fd..3c7c6502793c 100644 --- a/arch/arm/mach-uniphier/arm32/lowlevel_init.S +++ b/arch/arm/mach-uniphier/arm32/lowlevel_init.S @@ -25,6 +25,10 @@ ENTRY(lowlevel_init) orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache mcr p15, 0, r0, c1, c0, 0 +#ifdef CONFIG_DEBUG_LL + bl debug_ll_init +#endif + bl setup_init_ram @ RAM area for stack and page table /* @@ -42,10 +46,6 @@ ENTRY(lowlevel_init) bl enable_mmu -#ifdef CONFIG_DEBUG_LL - bl debug_ll_init -#endif - mov lr, r8 @ restore link mov pc, lr @ back to my caller ENDPROC(lowlevel_init) From patchwork Sun Aug 13 00:01:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 109945 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2676605qge; Sat, 12 Aug 2017 17:03:25 -0700 (PDT) X-Received: by 10.80.155.30 with SMTP id o30mr19408656edi.27.1502582605361; Sat, 12 Aug 2017 17:03:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502582605; cv=none; d=google.com; s=arc-20160816; b=BIt64XVcdZjopuyHuz9vx0Buqf/Jf90caHPZ0TZNUXn130QkaFg0eCgXif9kNDsNjW NJEesy2zm9BGo4Q2Ba028sdPfnouPvz7md9ax8k7/KZoykEKLOlHNiimiL77AizH955j C07ZyihOT2XgHuUEJSkK0JMjwnwWFU6PhIPdRlgNsCuqyxOgmhdolIxv2kKnaZxlg5DB wysPBWDxvK5TVwQWeJzjBkR1BtsSZ2SKdSUPXir2HRbqmTVvJQietSyLU4B47cIrnPW8 9CFOo1H/p45dYRTP8LaNQEngGvU2RPR45khdRuKKKq9C2oZk+cFGTEvYvVVcylg/7iqc vlRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=xlDeiGQ5BbxTcEeRbx/+/lLR9NFSU6UtXsM9ezLclIY=; b=iJOvhnCkG/gOEK96P2idFusg5emCQlW4G05T2qwitFwU1FrtsCoqB5WcV95sdvmWNQ BWdBKk/KEN3OkA4kvlp7ekR1xFZ3yl9mjHcp877neNXZuPGDyeDwVWYt3B84sm/9eFFT +b3MWUrGkZ9/5bQZR28K7yzA1yQSzLXL29tUJGLqJZVRsX3c3Ygf0QTeAZw8VljwKHFH 6GGLofdX1/A2sAYusYomBDalpIH40x/mM25VnrMtIxrBR0yvUSx5/jj9KqyxznrbWGS8 TErfRFP0I1goliP/rTGNDtO6ir+MGehI4WrA8xVBYieIDoZtLDVr49lT5S661SU7FFLx tFxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=EY/aSwUG; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. 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Commit 82d075e79fa5 ("ARM: uniphier: fix ROM boot mode for PH1-sLD3") was a workaround for sLD3. Now the sLD3 SoC support has been removed. Revert it to allow to simplify the init code. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/arm32/lowlevel_init.S | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/mach-uniphier/arm32/lowlevel_init.S b/arch/arm/mach-uniphier/arm32/lowlevel_init.S index 3c7c6502793c..a399a169a9da 100644 --- a/arch/arm/mach-uniphier/arm32/lowlevel_init.S +++ b/arch/arm/mach-uniphier/arm32/lowlevel_init.S @@ -98,11 +98,6 @@ ENDPROC(enable_mmu) ENTRY(setup_init_ram) ldr r1, = SSCO_BASE - mrc p15, 0, r0, c2, c0, 0 @ TTBR0 - ldr r0, [r0, #0x400] @ entry for virtual address 0x100***** - bfc r0, #0, #20 - cmp r0, #0x50000000 @ is sLD3 page table? - biceq r1, r1, #0xc0000000 @ sLD3 ROM maps 0x5******* to 0x1******* /* Touch to zero for the boot way */ 0: ldr r0, = 0x00408006 @ touch to zero with address range From patchwork Sun Aug 13 00:01:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 109943 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2675889qge; Sat, 12 Aug 2017 17:02:28 -0700 (PDT) X-Received: by 10.80.151.238 with SMTP id f43mr20050191edb.40.1502582548727; Sat, 12 Aug 2017 17:02:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502582548; cv=none; d=google.com; s=arc-20160816; b=eEdGIoQ9hjHAs1WOoaUIKcVVX823VZ4aWEW2Dtd2FrE37zxb9Tt+T9Po+zuxVVLgps WB9bHf008X2nFyCe1+tzedOUqCy75hhPE8XTbi3DXEZADBrn49AjJYAKtTIDNkATUUaO dH0dxE9l8yYyPbZH6pbTvEODPOl0BwApG13CPacBY/0pHqPyvHSUZllkeztcCPz9E5ks DTPiUPJsXcjdv/lxw8kq27BJwWhGXsZWa/diHzcohTC0kJNv9dKb0r588nJqaAZiSOv3 LQIv6P0HwWBpqB2AFGQesIoYle+BxW2T6j5i1uPHkiWGSCn/kFFUY27JiUl0MkUPzwPM vovg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=eraHg+VCZ+gJ9TVQ62pe1dnXTf8Qbya2qGqMcgI9D9k=; b=Y5IHqBsVIjUAB6EC2LYRxBaFwB2MmjTwYO9ktzdylzMWStZm89hCzAOIEAJvv3LlXn tCTCoX6K5DlUffokFDH6QdIcc+7fUIO19S2UyItGyBoO/o8GbcQdZDSNRz2YLCPmpkWm VYbnthiMFVZjHGfWYjrYD9vcGiF8kkXiaUwUD4Df14L8NBoAStQGGHqs0R0tKN2k/8wJ 7MZ8p7ChzDfKNHeRkkhNnWg6Kg+AZodqqTCT3QHVGV9qOV2pxKaymhYO1iw7t5ysJUWG 0cyM04XWEHDI+5cCKzqmToMqh58RaDQDmuglDToXibHA8tXSKq4MXfhyR2v/p490fkQI adJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=uItx//E/; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. 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Sun, 13 Aug 2017 00:01:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A999DC21C26; Sun, 13 Aug 2017 00:01:38 +0000 (UTC) Received: from conuserg-10.nifty.com (conuserg-10.nifty.com [210.131.2.77]) by lists.denx.de (Postfix) with ESMTPS id 2C05DC21C26 for ; Sun, 13 Aug 2017 00:01:36 +0000 (UTC) Received: from grover.sesame (FL1-122-131-185-176.osk.mesh.ad.jp [122.131.185.176]) (authenticated) by conuserg-10.nifty.com with ESMTP id v7D01JK1005965; Sun, 13 Aug 2017 09:01:20 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v7D01JK1005965 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1502582480; bh=/KOH9E3m8iM6DBTIA9KRlcPh00mzLFnreoUMrgv9S9U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uItx//E/kbvRjoziwNaRVlAYEPIQ+33iJvDKkh8bMQc7cjgntTS7Mlgs+Pb4EYvkr 3LCBkcl+dZViOcRDV92VzJ+7Mlb920nuePUYNbypOKX1dXD+OAcvtHyE2ROshubSS4 gv4gSoAkxKa4Azs9Yc37yFwKHX4rM/vdKv01PIJtmOEe0+HAp9dIt8yIH/oFfz8BYb Z+JzXHiiYr7AMfONBuhTldSZAN0M/oLU0aNIG/pLIkVCAnR0xtbSBdXLAdApRkqFhc 9cepTdUVqk57PkzLH9IbZwVwl7gBJRcvVVTT3WgQ9g77RO9DTKEhd8n0qirceXuCDL Iz68d2mOhMvFw== X-Nifty-SrcIP: [122.131.185.176] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Sun, 13 Aug 2017 09:01:16 +0900 Message-Id: <1502582477-27948-4-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1502582477-27948-1-git-send-email-yamada.masahiro@socionext.com> References: <1502582477-27948-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 4/5] reset: uniphier: refactor reset data and add NAND/eMMC reset lines X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" - Merge sys_reset data of LD4, Pro4, sLD8 and Pro5 - Merge sys_reset data of LD11 and LD20 - Use primitive UNIPHIER_RESETX() macro because bit assignments for system reset will be changed for every SoC in the future - Add NAND and eMMC resets Signed-off-by: Masahiro Yamada --- drivers/reset/reset-uniphier.c | 63 ++++++++++++------------------------------ 1 file changed, 17 insertions(+), 46 deletions(-) diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index df7fa267d13c..ebb2cae5eb33 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -41,46 +41,20 @@ struct uniphier_reset_data { } /* System reset data */ -#define UNIPHIER_SLD3_SYS_RESET_STDMAC(id) \ - UNIPHIER_RESETX((id), 0x2000, 10) - -#define UNIPHIER_LD11_SYS_RESET_STDMAC(id) \ - UNIPHIER_RESETX((id), 0x200c, 8) - -#define UNIPHIER_PRO4_SYS_RESET_GIO(id) \ - UNIPHIER_RESETX((id), 0x2000, 6) - -#define UNIPHIER_LD20_SYS_RESET_GIO(id) \ - UNIPHIER_RESETX((id), 0x200c, 5) - -#define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \ - UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17) - -static const struct uniphier_reset_data uniphier_ld4_sys_reset_data[] = { - UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */ - UNIPHIER_RESET_END, -}; - static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { - UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, MIO, RLE */ - UNIPHIER_PRO4_SYS_RESET_GIO(12), /* Ether, SATA, USB3 */ - UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), - UNIPHIER_PRO4_SYS_RESET_USB3(15, 1), - UNIPHIER_RESET_END, -}; - -static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = { - UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC */ - UNIPHIER_PRO4_SYS_RESET_GIO(12), /* PCIe, USB3 */ - UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), - UNIPHIER_PRO4_SYS_RESET_USB3(15, 1), + UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */ + UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */ + UNIPHIER_RESETX(12, 0x2000, 6), /* GIO */ + UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ + UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */ UNIPHIER_RESET_END, }; static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { - UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, RLE */ - UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), - UNIPHIER_PRO4_SYS_RESET_USB3(15, 1), + UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */ + UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */ + UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ + UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */ UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */ UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */ UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */ @@ -91,14 +65,11 @@ static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { UNIPHIER_RESET_END, }; -static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = { - UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC, MIO */ - UNIPHIER_RESET_END, -}; - static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { - UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC */ - UNIPHIER_LD20_SYS_RESET_GIO(12), /* PCIe, USB3 */ + UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */ + UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */ + UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC */ + UNIPHIER_RESETX(12, 0x200c, 5), /* GIO */ UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */ UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */ UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */ @@ -271,7 +242,7 @@ static const struct udevice_id uniphier_reset_match[] = { /* System reset */ { .compatible = "socionext,uniphier-ld4-reset", - .data = (ulong)uniphier_ld4_sys_reset_data, + .data = (ulong)uniphier_pro4_sys_reset_data, }, { .compatible = "socionext,uniphier-pro4-reset", @@ -279,11 +250,11 @@ static const struct udevice_id uniphier_reset_match[] = { }, { .compatible = "socionext,uniphier-sld8-reset", - .data = (ulong)uniphier_ld4_sys_reset_data, + .data = (ulong)uniphier_pro4_sys_reset_data, }, { .compatible = "socionext,uniphier-pro5-reset", - .data = (ulong)uniphier_pro5_sys_reset_data, + .data = (ulong)uniphier_pro4_sys_reset_data, }, { .compatible = "socionext,uniphier-pxs2-reset", @@ -291,7 +262,7 @@ static const struct udevice_id uniphier_reset_match[] = { }, { .compatible = "socionext,uniphier-ld11-reset", - .data = (ulong)uniphier_ld11_sys_reset_data, + .data = (ulong)uniphier_ld20_sys_reset_data, }, { .compatible = "socionext,uniphier-ld20-reset", From patchwork Sun Aug 13 00:01:17 2017 Content-Type: text/plain; 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[81.169.180.215]) by mx.google.com with ESMTP id 6si3742099edj.446.2017.08.12.17.01.43; Sat, 12 Aug 2017 17:01:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=cAJOzv1a; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id EA604C21E4B; Sun, 13 Aug 2017 00:01:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id DA77CC21D76; Sun, 13 Aug 2017 00:01:39 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9734BC21D9E; Sun, 13 Aug 2017 00:01:38 +0000 (UTC) Received: from conuserg-10.nifty.com (conuserg-10.nifty.com [210.131.2.77]) by lists.denx.de (Postfix) with ESMTPS id 300AEC21C6A for ; Sun, 13 Aug 2017 00:01:36 +0000 (UTC) Received: from grover.sesame (FL1-122-131-185-176.osk.mesh.ad.jp [122.131.185.176]) (authenticated) by conuserg-10.nifty.com with ESMTP id v7D01JK2005965; Sun, 13 Aug 2017 09:01:21 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v7D01JK2005965 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1502582481; bh=DyRRfkm695kbM2ipMNeYXPRXX4sjeZT0S/gJxkXHhEI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cAJOzv1auQHs4S9qFRpkyJkKnxkADk5IZZHXM6vrPYS9wap4FRV9OGx7jluCFltey UyEPYtuuYBDKslcw97ZZ5c6TAtAGUf9Y5zBFf5lyl/wD9g1CW4Hhn5l2Vk8kU7zcCU bWLgSbqLxI73fkYvZ8RaPF6Rnan7lSWvQVKu3aq2Wy3CKjksRViqPmNykIwfKsij0l G/vkYN4fKsOJTx2+jZtMS2I7DhCCTvDd3EjrV9yYLlml+cLNr412CFv/j3xk6JWah2 flDhnpLLTvTdpuzr90BwgQu1XYliouG81RS/HvW8VjF/REU8TCkKPcqR3sdFjkQIJK mhYr0W2mNWPew== X-Nifty-SrcIP: [122.131.185.176] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Sun, 13 Aug 2017 09:01:17 +0900 Message-Id: <1502582477-27948-5-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1502582477-27948-1-git-send-email-yamada.masahiro@socionext.com> References: <1502582477-27948-1-git-send-email-yamada.masahiro@socionext.com> Cc: Albert Aribaud Subject: [U-Boot] [PATCH 5/5] ARM: dts: uniphier: add dr_mode property to dwc3 node X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Since commit 576e3cc700c5 ("usb: host: xhci-dwc3: Add dual role mode support from DT"), warning is displayed. Signed-off-by: Masahiro Yamada --- arch/arm/dts/uniphier-ld20.dtsi | 1 + arch/arm/dts/uniphier-pro4.dtsi | 2 ++ arch/arm/dts/uniphier-pro5.dtsi | 2 ++ arch/arm/dts/uniphier-pxs2.dtsi | 2 ++ 4 files changed, 7 insertions(+) diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index 927340fa48d2..44257aff35b9 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -426,6 +426,7 @@ compatible = "snps,dwc3"; reg = <0x65a00000 0x10000>; interrupts = <0 134 4>; + dr_mode = "host"; tx-fifo-resize; }; }; diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi index 60287c478f25..cbb848207cc1 100644 --- a/arch/arm/dts/uniphier-pro4.dtsi +++ b/arch/arm/dts/uniphier-pro4.dtsi @@ -587,6 +587,7 @@ compatible = "snps,dwc3"; reg = <0x65a00000 0x10000>; interrupts = <0 134 4>; + dr_mode = "host"; tx-fifo-resize; }; }; @@ -604,6 +605,7 @@ compatible = "snps,dwc3"; reg = <0x65c00000 0x10000>; interrupts = <0 137 4>; + dr_mode = "host"; tx-fifo-resize; }; }; diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi index a29597ae88e0..498354c45f90 100644 --- a/arch/arm/dts/uniphier-pro5.dtsi +++ b/arch/arm/dts/uniphier-pro5.dtsi @@ -598,6 +598,7 @@ compatible = "snps,dwc3"; reg = <0x65a00000 0x10000>; interrupts = <0 134 4>; + dr_mode = "host"; tx-fifo-resize; }; }; @@ -615,6 +616,7 @@ compatible = "snps,dwc3"; reg = <0x65c00000 0x10000>; interrupts = <0 137 4>; + dr_mode = "host"; tx-fifo-resize; }; }; diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index 2962cb5ae7be..32844f781f5a 100644 --- a/arch/arm/dts/uniphier-pxs2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -610,6 +610,7 @@ compatible = "snps,dwc3"; reg = <0x65a00000 0x10000>; interrupts = <0 134 4>; + dr_mode = "host"; tx-fifo-resize; }; }; @@ -627,6 +628,7 @@ compatible = "snps,dwc3"; reg = <0x65c00000 0x10000>; interrupts = <0 137 4>; + dr_mode = "host"; tx-fifo-resize; }; };