From patchwork Thu May 21 00:53:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 200232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C94D4C433E0 for ; Thu, 21 May 2020 00:53:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AD13F20758 for ; Thu, 21 May 2020 00:53:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727770AbgEUAxx (ORCPT ); Wed, 20 May 2020 20:53:53 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:33416 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726819AbgEUAxw (ORCPT ); Wed, 20 May 2020 20:53:52 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id E3B34803078D; Thu, 21 May 2020 00:53:47 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lMhWD8BUGu9b; Thu, 21 May 2020 03:53:46 +0300 (MSK) From: Serge Semin To: Thomas Gleixner , Thomas Bogendoerfer , Daniel Lezcano , Alessandro Zummo , Alexandre Belloni , Rob Herring CC: Serge Semin , Serge Semin , Rob Herring , Alexey Malahov , Paul Burton , Ralf Baechle , Arnd Bergmann , , , , Subject: [PATCH v4 1/7] dt-bindings: rtc: Convert snps, dw-apb-timer to DT schema Date: Thu, 21 May 2020 03:53:14 +0300 Message-ID: <20200521005321.12129-2-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20200521005321.12129-1-Sergey.Semin@baikalelectronics.ru> References: <20200521005321.12129-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Modern device tree bindings are supposed to be created as YAML-files in accordance with DT schema. This commit replaces Synopsys DW Timer legacy bare text binding with YAML file. As before the binding file states that the corresponding dts node is supposed to be compatible with generic DW APB Timer indicated by the "snps,dw-apb-timer" compatible string and to provide a mandatory registers memory range, one timer interrupt, either reference clock source or a fixed clock rate value. It may also have an optional APB bus reference clock phandle specified. Signed-off-by: Serge Semin Reviewed-by: Rob Herring Cc: Alexey Malahov Cc: Thomas Bogendoerfer Cc: Paul Burton Cc: Ralf Baechle Cc: Thomas Gleixner Cc: Daniel Lezcano Cc: Arnd Bergmann Cc: linux-mips@vger.kernel.org --- This binding file doesn't belong to the bindings/rtc seeing it's a pure timer with no rtc facilities like days/months/years counting and alarms. The binding file will be moved to the "Documentation/devicetree/bindings/timer/" directory in the next patch. I also don't know who is the corresponding driver maintainer, so I added Daniel Lezcano to the maintainers schema. Any idea what email should be specified there instead? Changelog v3: - Since it's a conversion patch use GPL-2.0-only SPDX header. - Replace "additionalProperties: false" property with "unevaluatedProperties: false". --- .../devicetree/bindings/rtc/dw-apb.txt | 32 ------- .../bindings/rtc/snps,dw-apb-timer.yaml | 88 +++++++++++++++++++ 2 files changed, 88 insertions(+), 32 deletions(-) delete mode 100644 Documentation/devicetree/bindings/rtc/dw-apb.txt create mode 100644 Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml diff --git a/Documentation/devicetree/bindings/rtc/dw-apb.txt b/Documentation/devicetree/bindings/rtc/dw-apb.txt deleted file mode 100644 index c703d51abb6c..000000000000 --- a/Documentation/devicetree/bindings/rtc/dw-apb.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Designware APB timer - -Required properties: -- compatible: One of: - "snps,dw-apb-timer" - "snps,dw-apb-timer-sp" - "snps,dw-apb-timer-osc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: IRQ line for the timer. -- either clocks+clock-names or clock-frequency properties - -Optional properties: -- clocks : list of clock specifiers, corresponding to entries in - the clock-names property; -- clock-names : should contain "timer" and "pclk" entries, matching entries - in the clocks property. -- clock-frequency: The frequency in HZ of the timer. -- clock-freq: For backwards compatibility with picoxcell - -If using the clock specifiers, the pclk clock is optional, as not all -systems may use one. - - -Example: - timer@ffe00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 170 4>; - reg = <0xffe00000 0x1000>; - clocks = <&timer_clk>, <&timer_pclk>; - clock-names = "timer", "pclk"; - }; diff --git a/Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml new file mode 100644 index 000000000000..002fe1ee709b --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/snps,dw-apb-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare APB Timer + +maintainers: + - Daniel Lezcano + +properties: + compatible: + oneOf: + - const: snps,dw-apb-timer + - enum: + - snps,dw-apb-timer-sp + - snps,dw-apb-timer-osc + deprecated: true + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: Timer ticks reference clock source + - description: APB interface clock source + + clock-names: + minItems: 1 + items: + - const: timer + - const: pclk + + clock-frequency: true + + clock-freq: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: | + Has the same meaning as the 'clock-frequency' property - timer clock + frequency in HZ, but is defined only for the backwards compatibility + with the picoxcell platform. + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + +oneOf: + - required: + - clocks + - clock-names + - required: + - clock-frequency + - required: + - clock-freq + +examples: + - | + timer@ffe00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 170 4>; + reg = <0xffe00000 0x1000>; + clocks = <&timer_clk>, <&timer_pclk>; + clock-names = "timer", "pclk"; + }; + - | + timer@ffe00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 170 4>; + reg = <0xffe00000 0x1000>; + clocks = <&timer_clk>; + clock-names = "timer"; + }; + - | + timer@ffe00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 170 4>; + reg = <0xffe00000 0x1000>; + clock-frequency = <25000000>; + }; +... From patchwork Thu May 21 00:53:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 200231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC8FCC433DF for ; Thu, 21 May 2020 00:54:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D4B9220756 for ; Thu, 21 May 2020 00:54:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727113AbgEUAyG (ORCPT ); Wed, 20 May 2020 20:54:06 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:33466 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726819AbgEUAyG (ORCPT ); Wed, 20 May 2020 20:54:06 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 717998030779; Thu, 21 May 2020 00:54:01 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wPC4TaviKpRM; Thu, 21 May 2020 03:54:00 +0300 (MSK) From: Serge Semin To: Thomas Gleixner , Thomas Bogendoerfer , Daniel Lezcano , Jason Cooper , Marc Zyngier , Rob Herring CC: Serge Semin , Serge Semin , Rob Herring , Alexey Malahov , Paul Burton , Ralf Baechle , Alessandro Zummo , Alexandre Belloni , Arnd Bergmann , , , , Subject: [PATCH v4 3/7] dt-bindings: interrupt-controller: Convert mti, gic to DT schema Date: Thu, 21 May 2020 03:53:16 +0300 Message-ID: <20200521005321.12129-4-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20200521005321.12129-1-Sergey.Semin@baikalelectronics.ru> References: <20200521005321.12129-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Modern device tree bindings are supposed to be created as YAML-files in accordance with DT schema. This commit replaces MIPS GIC legacy bare text binding with YAML file. As before the binding file states that the corresponding dts node is supposed to be compatible with MIPS Global Interrupt Controller indicated by the "mti,gic" compatible string and to provide a mandatory interrupt-controller and '#interrupt-cells' properties. There might be optional registers memory range, "mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties specified. MIPS GIC also includes a free-running global timer, per-CPU count/compare timers, and a watchdog. Since currently the GIC Timer is only supported the DT schema expects an IRQ and clock-phandler charged timer sub-node with "mti,mips-gic-timer" compatible string. Signed-off-by: Serge Semin Reviewed-by: Rob Herring Cc: Alexey Malahov Cc: Thomas Bogendoerfer Cc: Paul Burton Cc: Ralf Baechle Cc: Alessandro Zummo Cc: Alexandre Belloni Cc: Daniel Lezcano Cc: Arnd Bergmann Cc: linux-mips@vger.kernel.org Cc: linux-rtc@vger.kernel.org --- I don't really know who is the corresponding driver maintainer, so I added Paul to the maintainers property since he used to be looking for the MIPS arch and Thomas looking after it now. Any idea what email should be specified there instead? Changelog v3: - Since timer sub-node has no unit-address, the node shouldn't be named with one. So alter the MIPS GIC bindings to have a pure "timer" sub-node. - Discard allOf: [ $ref: /schemas/interrupt-controller.yaml# ]. - Since it's a conversion patch use GPL-2.0-only SPDX header. --- .../interrupt-controller/mips-gic.txt | 67 -------- .../interrupt-controller/mti,gic.yaml | 148 ++++++++++++++++++ 2 files changed, 148 insertions(+), 67 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt deleted file mode 100644 index 173595305e26..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt +++ /dev/null @@ -1,67 +0,0 @@ -MIPS Global Interrupt Controller (GIC) - -The MIPS GIC routes external interrupts to individual VPEs and IRQ pins. -It also supports local (per-processor) interrupts and software-generated -interrupts which can be used as IPIs. The GIC also includes a free-running -global timer, per-CPU count/compare timers, and a watchdog. - -Required properties: -- compatible : Should be "mti,gic". -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt specifier. Should be 3. - - The first cell is the type of interrupt, local or shared. - See . - - The second cell is the GIC interrupt number. - - The third cell encodes the interrupt flags. - See for a list of valid - flags. - -Optional properties: -- reg : Base address and length of the GIC registers. If not present, - the base address reported by the hardware GCR_GIC_BASE will be used. -- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors - to which the GIC may not route interrupts. Valid values are 2 - 7. - This property is ignored if the CPU is started in EIC mode. -- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are - reserved for IPIs. - It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size - of the reserved range. - If not specified, the driver will allocate the last 2 * number of VPEs in the - system. - -Required properties for timer sub-node: -- compatible : Should be "mti,gic-timer". -- interrupts : Interrupt for the GIC local timer. - -Optional properties for timer sub-node: -- clocks : GIC timer operating clock. -- clock-frequency : Clock frequency at which the GIC timers operate. - -Note that one of clocks or clock-frequency must be specified. - -Example: - - gic: interrupt-controller@1bdc0000 { - compatible = "mti,gic"; - reg = <0x1bdc0000 0x20000>; - - interrupt-controller; - #interrupt-cells = <3>; - - mti,reserved-cpu-vectors = <7>; - mti,reserved-ipi-vectors = <40 8>; - - timer { - compatible = "mti,gic-timer"; - interrupts = ; - clock-frequency = <50000000>; - }; - }; - - uart@18101400 { - ... - interrupt-parent = <&gic>; - interrupts = ; - ... - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml new file mode 100644 index 000000000000..9f0eb3addac4 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS Global Interrupt Controller + +maintainers: + - Paul Burton + - Thomas Bogendoerfer + +description: | + The MIPS GIC routes external interrupts to individual VPEs and IRQ pins. + It also supports local (per-processor) interrupts and software-generated + interrupts which can be used as IPIs. The GIC also includes a free-running + global timer, per-CPU count/compare timers, and a watchdog. + +properties: + compatible: + const: mti,gic + + "#interrupt-cells": + const: 3 + description: | + The 1st cell is the type of interrupt: local or shared defined in the + file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the + GIC interrupt number. The 3d cell encodes the interrupt flags setting up + the IRQ trigger modes, which are defined in the file + 'dt-bindings/interrupt-controller/irq.h'. + + reg: + description: | + Base address and length of the GIC registers space. If not present, + the base address reported by the hardware GCR_GIC_BASE will be used. + maxItems: 1 + + interrupt-controller: true + + mti,reserved-cpu-vectors: + description: | + Specifies the list of CPU interrupt vectors to which the GIC may not + route interrupts. This property is ignored if the CPU is started in EIC + mode. + allOf: + - $ref: /schemas/types.yaml#definitions/uint32-array + - minItems: 1 + maxItems: 6 + uniqueItems: true + items: + minimum: 2 + maximum: 7 + + mti,reserved-ipi-vectors: + description: | + Specifies the range of GIC interrupts that are reserved for IPIs. + It accepts two values: the 1st is the starting interrupt and the 2nd is + the size of the reserved range. If not specified, the driver will + allocate the last (2 * number of VPEs in the system). + allOf: + - $ref: /schemas/types.yaml#definitions/uint32-array + - items: + - minimum: 0 + maximum: 254 + - minimum: 2 + maximum: 254 + + timer: + type: object + description: | + MIPS GIC includes a free-running global timer, per-CPU count/compare + timers, and a watchdog. Currently only the GIC Timer is supported. + properties: + compatible: + const: mti,gic-timer + + interrupts: + description: | + Interrupt for the GIC local timer, so normally it's suppose to be of + format. + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: true + + required: + - compatible + - interrupts + + oneOf: + - required: + - clocks + - required: + - clock-frequency + + additionalProperties: false + +unevaluatedProperties: false + +required: + - compatible + - "#interrupt-cells" + - interrupt-controller + +examples: + - | + #include + #include + + interrupt-controller@1bdc0000 { + compatible = "mti,gic"; + reg = <0x1bdc0000 0x20000>; + interrupt-controller; + #interrupt-cells = <3>; + mti,reserved-cpu-vectors = <7>; + mti,reserved-ipi-vectors = <40 8>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clock-frequency = <50000000>; + }; + }; + - | + #include + #include + + interrupt-controller@1bdc0000 { + compatible = "mti,gic"; + reg = <0x1bdc0000 0x20000>; + interrupt-controller; + #interrupt-cells = <3>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clocks = <&cpu_pll>; + }; + }; + - | + interrupt-controller { + compatible = "mti,gic"; + interrupt-controller; + #interrupt-cells = <3>; + }; +... From patchwork Thu May 21 00:53:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 200230 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EBCEC433E3 for ; Thu, 21 May 2020 00:54:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1891020756 for ; Thu, 21 May 2020 00:54:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727951AbgEUAyO (ORCPT ); Wed, 20 May 2020 20:54:14 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:33554 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726819AbgEUAyL (ORCPT ); Wed, 20 May 2020 20:54:11 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id E24848030790; Thu, 21 May 2020 00:54:06 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vfue8pGIqaHD; Thu, 21 May 2020 03:54:06 +0300 (MSK) From: Serge Semin To: Thomas Gleixner , Thomas Bogendoerfer , Daniel Lezcano , Jamie Iles , Rob Herring , Dinh Nguyen , Heiko Stuebner , Arnd Bergmann CC: Serge Semin , Serge Semin , Alexey Malahov , Paul Burton , Ralf Baechle , Alessandro Zummo , Alexandre Belloni , Rob Herring , , , , Allison Randal , Greg Kroah-Hartman , Alexios Zavras , Subject: [PATCH v4 5/7] clocksource: dw_apb_timer_of: Fix missing clockevent timers Date: Thu, 21 May 2020 03:53:18 +0300 Message-ID: <20200521005321.12129-6-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20200521005321.12129-1-Sergey.Semin@baikalelectronics.ru> References: <20200521005321.12129-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Commit 100214889973 ("clocksource: dw_apb_timer_of: use clocksource_of_init") replaced a publicly available driver initialization method with one called by the timer_probe() method available after CLKSRC_OF. In current implementation it traverses all the timers available in the system and calls their initialization methods if corresponding devices were either in dtb or in acpi. But if before the commit any number of available timers would be installed as clockevent and clocksource devices, after that there would be at most two. The rest are just ignored since default case branch doesn't do anything. I don't see a reason of such behaviour, neither the commit message explains it. Moreover this might be wrong if on some platforms these timers might be used for different purpose, as virtually CPU-local clockevent timers and as an independent broadcast timer. So in order to keep the compatibility with the platforms where the order of the timers detection has some meaning, lets add the secondly discovered timer to be of clocksource/sched_clock type, while the very first and the others would provide the clockevents service. Fixes: 100214889973 ("clocksource: dw_apb_timer_of: use clocksource_of_init") Signed-off-by: Serge Semin Cc: Alexey Malahov Cc: Thomas Bogendoerfer Cc: Paul Burton Cc: Ralf Baechle Cc: Alessandro Zummo Cc: Alexandre Belloni Cc: Arnd Bergmann Cc: Rob Herring Cc: linux-mips@vger.kernel.org Cc: linux-rtc@vger.kernel.org Cc: devicetree@vger.kernel.org --- drivers/clocksource/dw_apb_timer_of.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c index 0a2505b323d7..0b61b90a525e 100644 --- a/drivers/clocksource/dw_apb_timer_of.c +++ b/drivers/clocksource/dw_apb_timer_of.c @@ -146,10 +146,6 @@ static int num_called; static int __init dw_apb_timer_init(struct device_node *timer) { switch (num_called) { - case 0: - pr_debug("%s: found clockevent timer\n", __func__); - add_clockevent(timer); - break; case 1: pr_debug("%s: found clocksource timer\n", __func__); add_clocksource(timer); @@ -160,6 +156,8 @@ static int __init dw_apb_timer_init(struct device_node *timer) #endif break; default: + pr_debug("%s: found clockevent timer\n", __func__); + add_clockevent(timer); break; } From patchwork Thu May 21 00:53:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 200229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0B7AC433E2 for ; Thu, 21 May 2020 00:54:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9D45E207E8 for ; Thu, 21 May 2020 00:54:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727991AbgEUAyV (ORCPT ); Wed, 20 May 2020 20:54:21 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:33612 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727936AbgEUAyQ (ORCPT ); Wed, 20 May 2020 20:54:16 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 2E08C80005E8; Thu, 21 May 2020 00:54:11 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id B5585joA7vdh; Thu, 21 May 2020 03:54:10 +0300 (MSK) From: Serge Semin To: Thomas Gleixner , Thomas Bogendoerfer , Daniel Lezcano CC: Serge Semin , Serge Semin , Alexey Malahov , Paul Burton , Ralf Baechle , Alessandro Zummo , Alexandre Belloni , Arnd Bergmann , Rob Herring , , , , Paul Cercueil , Krzysztof Kozlowski , Geert Uytterhoeven , Randy Dunlap , Claudiu Beznea , Maarten ter Huurne , Vincenzo Frascino , Subject: [PATCH v4 7/7] clocksource: mips-gic-timer: Mark GIC timer as unstable if ref clock changes Date: Thu, 21 May 2020 03:53:20 +0300 Message-ID: <20200521005321.12129-8-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20200521005321.12129-1-Sergey.Semin@baikalelectronics.ru> References: <20200521005321.12129-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Currently clocksource framework doesn't support the clocks with variable frequency. Since MIPS GIC timer ticks rate might be unstable on some platforms, we must make sure that it justifies the clocksource requirements. MIPS GIC timer is incremented with the CPU cluster reference clocks rate. So in case if CPU frequency changes, the MIPS GIC tick rate changes synchronously. Due to this the clocksource subsystem can't rely on the timer to measure system clocks anymore. This commit marks the MIPS GIC based clocksource as unstable if reference clock (normally it's a CPU reference clocks) rate changes. The clocksource will execute a watchdog thread, which lowers the MIPS GIC timer rating to zero and fallbacks to a new stable one. Note we don't need to set the CLOCK_SOURCE_MUST_VERIFY flag to the MIPS GIC clocksource since normally the timer is stable. The only reason why it gets unstable is due to the ref clock rate change, which event we detect here in the driver by means of the clocks event notifier. Signed-off-by: Serge Semin Cc: Alexey Malahov Cc: Thomas Bogendoerfer Cc: Paul Burton Cc: Ralf Baechle Cc: Alessandro Zummo Cc: Alexandre Belloni Cc: Arnd Bergmann Cc: Rob Herring Cc: linux-mips@vger.kernel.org Cc: linux-rtc@vger.kernel.org Cc: devicetree@vger.kernel.org --- Changelog v3: - Mark clocksource as unstable instead of lowering its rating. --- drivers/clocksource/Kconfig | 1 + drivers/clocksource/mips-gic-timer.c | 19 ++++++++++++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index f2142e6bbea3..37a745f3ca91 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -572,6 +572,7 @@ config CLKSRC_VERSATILE config CLKSRC_MIPS_GIC bool depends on MIPS_GIC + select CLOCKSOURCE_WATCHDOG select TIMER_OF config CLKSRC_TANGO_XTAL diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index ef12c12c2432..d78ad7b60cdc 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -24,6 +24,9 @@ static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device); static int gic_timer_irq; static unsigned int gic_frequency; +static bool __read_mostly gic_clock_unstable; + +static void git_clocksource_unstable(char *reason); static u64 notrace gic_read_count_2x32(void) { @@ -125,8 +128,10 @@ static int gic_clk_notifier(struct notifier_block *nb, unsigned long action, { struct clk_notifier_data *cnd = data; - if (action == POST_RATE_CHANGE) + if (action == POST_RATE_CHANGE) { + git_clocksource_unstable("ref clock rate change"); on_each_cpu(gic_update_frequency, (void *)cnd->new_rate, 1); + } return NOTIFY_OK; } @@ -172,6 +177,18 @@ static struct clocksource gic_clocksource = { .vdso_clock_mode = VDSO_CLOCKMODE_GIC, }; +static void git_clocksource_unstable(char *reason) +{ + if (gic_clock_unstable) + return; + + gic_clock_unstable = true; + + pr_info("GIC timer is unstable due to %s\n", reason); + + clocksource_mark_unstable(&gic_clocksource); +} + static int __init __gic_clocksource_init(void) { unsigned int count_width;