From patchwork Thu May 21 13:45:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 200185 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B832AC433E0 for ; Thu, 21 May 2020 13:46:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8D3CC2078B for ; Thu, 21 May 2020 13:46:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="F5qFZM2g"; dkim=pass (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="jIlHBsi9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729578AbgEUNqr (ORCPT ); Thu, 21 May 2020 09:46:47 -0400 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:63046 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729566AbgEUNqq (ORCPT ); Thu, 21 May 2020 09:46:46 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1590068806; x=1621604806; h=from:to:cc:subject:date:message-id:in-reply-to: references:content-transfer-encoding:mime-version; bh=B1YCa9WtevsIneyMYRHZQO7mK/ptLy+6bCQ1v8wy5FY=; b=F5qFZM2gWSmvstBDGXoagwXWbuvYumdfgjJrtuG7hajmYOSgOJLT6P9U /xnxypMF5f9DuXOl27eocouK1Bq8Ho5TZj+6HsGQ9YtLi5bAo8o3YJAc0 qSGrqB5IQsfpKLZtb8I34jIpLLXgiZBoi8HDYyCj8Idl2mnanc1lPeYpG 5hqd9wfgq2/QRXtvrR2TgvOI5nD2bvE9tdS0ZXTe9RChcIpvJvw+XZrxU Mx4OAwu84i6Tys+RhtzmrNoAqhULjBlP17UQTNYCmwk5ZaEEpVBwDMBMH NZT5bs95Sqx1zDcpxPL+CVnUMgJ3uu8xR/FZADBGbGK7Vxgt6b+laZW2v g==; IronPort-SDR: HnXVoC0Ds7Mwiropk0/S4i7o5f3U2uJCNUHLK0n98urYrDOTTXSiKk9nYArENCRxEePET3jE1A kVhndAcVqTd7sdkiEDdP9bTjKtaUcPw0y9VoRvPbCqfISTEsgHVzbJjGJhp0yT0Pil3t9E+IYP XTmOKmxRWQDCOdxapPNiPISdg5dbP3C4NtoBlH3+YocHbtYs7UnEAelY1K06wBwtgc2S1B3dZw CV5yDlMgtlce+tNV7buUk7h5oknDO+AFo6FXZzrIm7kkCQzMpaBXIQMK5Y5Ql2wmjzIRAQiBCi IOA= X-IronPort-AV: E=Sophos;i="5.73,417,1583164800"; d="scan'208";a="139661593" Received: from mail-mw2nam12lp2045.outbound.protection.outlook.com (HELO NAM12-MW2-obe.outbound.protection.outlook.com) ([104.47.66.45]) by ob1.hgst.iphmx.com with ESMTP; 21 May 2020 21:46:45 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=SN8RsuvcV0eZY49LMW5LKkyetxXNiF/IcjIBsvdQrSmknLNFaCg7pKFHSiC9X3a1JD2x5MKsiT0jA61d9MQ8gH5qRhC6dbvn/3owlr1JsNrpZy8dBgAjMA59DpK9zs5Uw9PVyPhiIbgjrnPyYdHa45PK2AkRIU5cz41f+lDNH4zGjQoNVHChyjuKcuoP8VjIry004AFCs2YR3o8HXxIzO8U73VLCxXNRs+CWNx68/VFGgbHjiorwvIx7IaaEGvEPm4OsLZW9ALP7XPOTHWijp2NTYV4q6tGYtCiQRF4YtweUd6iHY3XuJmBhIGDdPe8n/1Qtn5vC7MVXZl3zqttthg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+VVQ3ZS6TEI9sRWrb27Z77jx1KtOiPHyGgst/7QXjiU=; b=exr44c5DU+m+AvtSjCAKGoFLIaF3ymVgoce6sVk1r+ZCHI6eaoPrj8aVQvfMicoxQja7qxF1mNC+IwIKWMuflIUrVNLCHDi3fKqNL81BgX7Q1XQNFl9/or9Z1CM26g2lr/O19xdViqNNg5Ry8I1t7X4I+DOY1n141YoRcEG6se17qsd1NnNxkjLMxmQTtR9h2TEzYQ6kB07nSmimkLivT3gL8vxKaSa/TpDFctBoC33eB/zbbRzH3b8/1SluzVBOaTr/snniSK1osXtXpWq9gTtsO9JZQlNX54BSGVW3MmLk7QQROWMXURo5lI6OqIObKU1PUCyXNzzprkFZu+hfvw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+VVQ3ZS6TEI9sRWrb27Z77jx1KtOiPHyGgst/7QXjiU=; b=jIlHBsi9u5VeK0FAwLorTpP8U6x/tiyFfBuEuSIGB3o1d5qUIMgF65NG83g6TFlUpgJV2DFSKnQkur5P2BZY1NzlFz0GuXq0dlaDDy2HKIAPJ7UCqvZ1/bL1QQuqnnv9LoTfUn/wVfS2qxEKRDrq7d0Hdq7/QdICB/vh799ql2g= Authentication-Results: dabbelt.com; dkim=none (message not signed) header.d=none; dabbelt.com; dmarc=none action=none header.from=wdc.com; Received: from DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) by DM6PR04MB4380.namprd04.prod.outlook.com (2603:10b6:5:a2::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3021.23; Thu, 21 May 2020 13:46:43 +0000 Received: from DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::f8b3:c124:482b:52e0]) by DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::f8b3:c124:482b:52e0%5]) with mapi id 15.20.3000.034; Thu, 21 May 2020 13:46:43 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Rob Herring , Daniel Lezcano , Thomas Gleixner Cc: Damien Le Moal , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH 3/5] clocksource/drivers/timer-riscv: Remove MMIO related stuff Date: Thu, 21 May 2020 19:15:42 +0530 Message-Id: <20200521134544.816918-4-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200521134544.816918-1-anup.patel@wdc.com> References: <20200521134544.816918-1-anup.patel@wdc.com> X-ClientProxiedBy: MAXPR01CA0073.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:49::15) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (106.51.30.72) by MAXPR01CA0073.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:49::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3021.23 via Frontend Transport; Thu, 21 May 2020 13:46:36 +0000 X-Mailer: git-send-email 2.25.1 X-Originating-IP: [106.51.30.72] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 767b1d03-cfc0-47bc-d38f-08d7fd8d6554 X-MS-TrafficTypeDiagnostic: DM6PR04MB4380: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-Forefront-PRVS: 041032FF37 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /7sd8ZykpUHErpSqX8/7/NswR2RXRbS2uKPADZZ2CuXW9FTbEHaLUstxSagn3DIZKIKSNDBMT2Giex3ptjwPeyusaM4WnJ87bqHGf1g9NB3XlKp91s4reGCLXQ3NG1PwtOKmf5uX2puYIM1f/3zYaDfBBtD+Hb4m5KJi5oKzKMKQvJyEyWOM3LDyrUqL8bCAy/KkMBbHEFbG2I4n67I1cJPJi4zYHC5lg9K3WmUTFo/dTya85lFizu8V6CJu0dLz4ouVrScnMILrsVj09uhIopyD9kVleejVCxEZOzhN8JQHjPQjM9SvTOIYfnuwDXLlSQwPKbJ/ramTFl19AqKhWQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR04MB6201.namprd04.prod.outlook.com; PTR:; CAT:NONE; SFTY:; SFS:(4636009)(136003)(39860400002)(366004)(376002)(396003)(346002)(16526019)(55016002)(86362001)(316002)(6666004)(26005)(1006002)(52116002)(1076003)(186003)(8886007)(54906003)(478600001)(66476007)(66946007)(55236004)(7696005)(66556008)(5660300002)(110136005)(36756003)(8676002)(2906002)(956004)(2616005)(4326008)(7416002)(8936002)(44832011); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: t2L9pURKhAKd6394cjPQSvuz13vL+zA4TYHI4GnM1j4ZZLZc+F2B0zJMhRY2NSiDLL06GsuZJ0F8JVT2cTf2C4WJ4dRNLKx5YssMRFYhdUiWzXwHb+D5JIS/KNJHVpfAEGMMlxFeZYiGLAkFNrMKFcWihDi6OkYtuGsjl5CcJjQ0sqj31uuUAXEsBTyi4YYz8hlRzwrw+6MGAtAGKMQztFiaVGzps9JTdga76WfM3asALOPLiN6FAToU3rcOVV7sCzB7PmYk9wALmBpy0XoCCrBoyJg+v8x1WFNdyU6SMhmMkov8J2789vVn9gIMbQWRUFT3abnFsGsB5n6izm4K9ajTfKN+6/+FwHcLmcp/Rbbz9oYmgU3X0SAhDm1IckdK7iBNERkA93AC9OwpY7OHcuHDsPQZIeth9uP0cmPi62GQns6/Knl50szjRAdYr5WzpXZmPuNWodoxacJE6dAlmrJj51zZyM6SGKtWWKDCerM= X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 767b1d03-cfc0-47bc-d38f-08d7fd8d6554 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2020 13:46:43.4194 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: YDBEYuPnEjHyjK2G4S7mJre5+mCCBLKFEw0yOmbGndgpMOFgilApI58SIs+Ab9OtAaBn2GMLjWxHRW43j5Qi5Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR04MB4380 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Right now the RISC-V timer is convoluted to support: 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for clocksource and SBI timer calls for clockevent device. 2. Linux RISC-V M-mode (without MMU) where it will use CLINT MMIO counter register for clocksource and CLINT MMIO compare register for clockevent device. This patch removes MMIO related stuff from RISC-V timer driver so that we can have a separate CLINT timer driver. Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 2 +- arch/riscv/include/asm/timex.h | 28 +++++++--------------------- drivers/clocksource/Kconfig | 2 +- drivers/clocksource/timer-riscv.c | 17 ++--------------- 4 files changed, 11 insertions(+), 38 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 2cf0c83c1a47..bbdc37a78f7b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -52,7 +52,7 @@ config RISCV select PCI_DOMAINS_GENERIC if PCI select PCI_MSI if PCI select RISCV_INTC - select RISCV_TIMER + select RISCV_TIMER if RISCV_SBI select GENERIC_IRQ_MULTI_HANDLER select GENERIC_ARCH_TOPOLOGY if SMP select ARCH_HAS_PTE_SPECIAL diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h index bad2a7c2cda5..a3fb85d505d4 100644 --- a/arch/riscv/include/asm/timex.h +++ b/arch/riscv/include/asm/timex.h @@ -7,41 +7,27 @@ #define _ASM_RISCV_TIMEX_H #include -#include typedef unsigned long cycles_t; -extern u64 __iomem *riscv_time_val; -extern u64 __iomem *riscv_time_cmp; - -#ifdef CONFIG_64BIT -#define mmio_get_cycles() readq_relaxed(riscv_time_val) -#else -#define mmio_get_cycles() readl_relaxed(riscv_time_val) -#define mmio_get_cycles_hi() readl_relaxed(((u32 *)riscv_time_val) + 1) -#endif - static inline cycles_t get_cycles(void) { - if (IS_ENABLED(CONFIG_RISCV_SBI)) - return csr_read(CSR_TIME); - return mmio_get_cycles(); + return csr_read(CSR_TIME); } #define get_cycles get_cycles +static inline u32 get_cycles_hi(void) +{ + return csr_read(CSR_TIMEH); +} +#define get_cycles_hi get_cycles_hi + #ifdef CONFIG_64BIT static inline u64 get_cycles64(void) { return get_cycles(); } #else /* CONFIG_64BIT */ -static inline u32 get_cycles_hi(void) -{ - if (IS_ENABLED(CONFIG_RISCV_SBI)) - return csr_read(CSR_TIMEH); - return mmio_get_cycles_hi(); -} - static inline u64 get_cycles64(void) { u32 hi, lo; diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index f2142e6bbea3..21950d9e3e9d 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -650,7 +650,7 @@ config ATCPIT100_TIMER config RISCV_TIMER bool "Timer for the RISC-V platform" - depends on GENERIC_SCHED_CLOCK && RISCV + depends on GENERIC_SCHED_CLOCK && RISCV_SBI default y select TIMER_PROBE select TIMER_OF diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 5fb7c5ba5c91..3e7e0cf5b899 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -19,26 +19,13 @@ #include #include #include - -u64 __iomem *riscv_time_cmp; -u64 __iomem *riscv_time_val; - -static inline void mmio_set_timer(u64 val) -{ - void __iomem *r; - - r = riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id()); - writeq_relaxed(val, r); -} +#include static int riscv_clock_next_event(unsigned long delta, struct clock_event_device *ce) { csr_set(CSR_IE, IE_TIE); - if (IS_ENABLED(CONFIG_RISCV_SBI)) - sbi_set_timer(get_cycles64() + delta); - else - mmio_set_timer(get_cycles64() + delta); + sbi_set_timer(get_cycles64() + delta); return 0; } From patchwork Thu May 21 13:45:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 200184 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDCE0C433DF for ; Thu, 21 May 2020 13:47:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 974802078B for ; Thu, 21 May 2020 13:47:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="SIrMWdHm"; dkim=pass (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="nuhyQJj6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729511AbgEUNrH (ORCPT ); Thu, 21 May 2020 09:47:07 -0400 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:48615 "EHLO esa4.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729431AbgEUNrG (ORCPT ); Thu, 21 May 2020 09:47:06 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1590068825; x=1621604825; h=from:to:cc:subject:date:message-id:in-reply-to: references:content-transfer-encoding:mime-version; bh=+fVCosLVNVzYa9DEV+DdvD5UNh9H7AyIvdRwFBPCXsk=; b=SIrMWdHmbW9pLrdGwDXwdbS2H53X545PDwrL+6ciwAcxjCAX5yooShot xJK4QB6BgM8a/2f4k3F1KorwqOLMevirRqqMfgqFQNwp1PqtNbMeW+9l3 75COkEkG8ZxTVxUHDFcBBcDWkB7S+d8iqGh+tsLByJzpRZcj4Ozc55l0x sCDQZ2i+Ec6Ty3exvyzS61wZWBVg5oxjrOpFuEdcCKyJXvOdAMF/u4auC giCKScMWPx//FvKY9UncBqnVfB5ZADUb3qUx3qxYvRZCn7b2BdN2qjHZI xNVmFOrdr7/ktC39iUDqy1IEUqftWEyRCxgUJyACvHXNBtTivFJKsCwyw Q==; IronPort-SDR: GwcrF5gb19oC8wCsRO6iAHUmSypYDlrWTw0n4/a7mgQHAyBF59G3XEO/wZZuIHnWy/nW4OctgA xtxs4rYTTzqN2/y3qP5JrAgNwMIE7gXoUQLsQZB+L2r8/Sy8HmYK0f0tB0srV1LnAJztayZe7F bMVGCd/f7FlG7DfmaoTLwE7fBqZFJZGsSU/oVNU76i+eTXckJjHK4GjbxHMhIVeGLR3VM000L/ uq5PRXglKIcBSms48tYxRv9oj4FQXcTAnj3vuI2sLbFN3jMoIiKdPHGMIE/+N7SeHCzy5DYhIl i7c= X-IronPort-AV: E=Sophos;i="5.73,417,1583164800"; d="scan'208";a="138224562" Received: from mail-dm6nam12lp2174.outbound.protection.outlook.com (HELO NAM12-DM6-obe.outbound.protection.outlook.com) ([104.47.59.174]) by ob1.hgst.iphmx.com with ESMTP; 21 May 2020 21:47:04 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=S/lRpk2V8fciUvmJfTba7dmhd89MYo2KjrXAmxbpHRf0OuOZQqTDWrSB2R0l962bjP+YIMsYMHuyLWFPAgzQwemFpRLhR7mlvk+gjoAKyiRQ2rnjcusJOGUpxt/gDKtKGsR5wV97VTs3/GYfJCcfwiwD5VM26/zhxjXUIz4nUWcRUpzxwq/EZlTcXFI3qMNK23c84NtTcMQEd24369BR+cJPK0QaOQ+1fVAp5cfpmGikfEeDpvbQvosHmFqp4F1z5BiSxM1Q7HboDrByujDD4wtSwZDVu4/BZMHKuOaa4Bapdvm6djGCL5lrPWYICQecxeAu1B+phLeSvkhkMarq8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ob6uXxeCegrtxqCXvOpGyy8bYomEH+RQ1UdvLcaVtXY=; b=LlB/QcbR9Y0YBcVk7V51BOZV380YaygiFji94szr5665y69a6t1nzOnJt8uosib69V5Pc7D2YxNXzafGwkhqvUmvHPiCkCggYgloFplhAktvKRN1v8wwRagiL3ZQGncnQxk1MDUSJguNDGqRVuw4Kc+XlEzYQih4ebARNFlsIoFss5wOSohH9GloEecoYlqENCMx8qAEN9tq1t4Stt+gJ7iHybXNaGOyICDMiwj5CEsTTkRl/pB0C3a8L2eYSclPEi9V6lszQY+IgfiRcQUAN2k5Gskli17RCX7/DNeIE3eR/aH7ROM/jNsXsAonEdGCTDI9uK00TfunxktD02q//Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ob6uXxeCegrtxqCXvOpGyy8bYomEH+RQ1UdvLcaVtXY=; b=nuhyQJj6Fn3ukYQoSICb4oWu9lokJmR1y7LSjhOcz5inN55Q4eQAtNclJe96w17sfO6TFUx6z37Y0TlRgRvl/nlfZNWrSYUcQDjSJlCdWRSSkH6XA2CQ6iJP1t3tRYEp+ETypAa8gMu6v0BoA0rrfCvkupKTM3xFGHV/FCg1wk8= Authentication-Results: dabbelt.com; dkim=none (message not signed) header.d=none; dabbelt.com; dmarc=none action=none header.from=wdc.com; Received: from DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) by DM6PR04MB4380.namprd04.prod.outlook.com (2603:10b6:5:a2::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3021.23; Thu, 21 May 2020 13:47:03 +0000 Received: from DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::f8b3:c124:482b:52e0]) by DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::f8b3:c124:482b:52e0%5]) with mapi id 15.20.3000.034; Thu, 21 May 2020 13:47:03 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Rob Herring , Daniel Lezcano , Thomas Gleixner Cc: Damien Le Moal , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH 5/5] dt-bindings: timer: Add CLINT bindings Date: Thu, 21 May 2020 19:15:44 +0530 Message-Id: <20200521134544.816918-6-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200521134544.816918-1-anup.patel@wdc.com> References: <20200521134544.816918-1-anup.patel@wdc.com> X-ClientProxiedBy: MAXPR01CA0073.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:49::15) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (106.51.30.72) by MAXPR01CA0073.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:49::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3021.23 via Frontend Transport; Thu, 21 May 2020 13:46:49 +0000 X-Mailer: git-send-email 2.25.1 X-Originating-IP: [106.51.30.72] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 98386d5a-ee42-4782-b152-08d7fd8d6d53 X-MS-TrafficTypeDiagnostic: DM6PR04MB4380: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-Forefront-PRVS: 041032FF37 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4Lg2fExpGHB6x6MZnVlNsqUXGph8i2rWbqTIcAeE5hN6n3ySFK+27g0TALpR2XEyxcUV29Qj5/syfzbFej+5ZnNIVWRyMbRWtqTJ7Z86gom+qWqMsfqvDCdFg/WLoxH3f+KtwIT03wCQiWvDn4lLqjQX4OQIDg7fHB2zjIIvBWl0Mw1fsYMWhOvKNvDgk6NUns9KC5yRC1dwOXxWtAert5zmJ750g3X74O09CM+tbAWd/otC3/2+9Kp2zph6hpAdTMLTCbr4r/Po/xgsrFyie0l3NGtpDBJyCkcN9fGxpZUvcwtFXKSFR1mymTj4988H/A8eGztAcEnXcl6vkmvxhw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR04MB6201.namprd04.prod.outlook.com; PTR:; CAT:NONE; SFTY:; SFS:(4636009)(136003)(39860400002)(366004)(376002)(396003)(346002)(16526019)(55016002)(86362001)(316002)(6666004)(26005)(1006002)(52116002)(1076003)(186003)(8886007)(54906003)(478600001)(66476007)(66946007)(55236004)(7696005)(66556008)(5660300002)(110136005)(36756003)(8676002)(2906002)(956004)(2616005)(4326008)(7416002)(8936002)(44832011); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: 4o/RxkjniQv+PVj3a/mU8yTIubtVYBIF4Z5H0JqjTfxYoikOgdtZyR4ZHmRhB5cyHCq+t4xrXrPuJ9KfHESLP8khtnOZ7Zn7R12RhUpQ5ZioooQSsXYqkY5DexFZ1He6ZOJp0ZdzLyl4Mr09CB1sWDSZnYsZEQ54ZOSh9gjBA5NkadoO8LsttffLXSdEXiu6UmGFhZlJlnrtwlYRL16FVUSeTeioIx9xdUAdkWLDKk6vgMo/0Pnc/T+jcFC/MokWQropa1Xd3sFJQ3q8MUJsSO65+eC+DlLLHBzCzr1jeBVxvRYZrUpNl/ptzi2pjdlotAG3nZO+esZ3R9oJA3F1NNNoZfZBUndJyDHzyqVHhqC9vizo5Wr6UswvTqhpiUpG3HzAVquzJa51Ge+PCo8et+iMUTFuVbM/sxdAUY1ixlRhqkD04cBFYr+4tVpgseACm4dosgLlA07Bfngm+UJuUqOWzKvutIgVApBBS9vXKH4= X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 98386d5a-ee42-4782-b152-08d7fd8d6d53 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2020 13:47:03.2367 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: X/X1jPd3ZlSdyzWOnT1kclSpeALm6NkF0kU4mRjVBeALnj+PcmN4nUaPN9DRUocF8vxhMI8Y0k6D1SwGnTuSzQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR04MB4380 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We add DT bindings documentation for CLINT device. Signed-off-by: Anup Patel --- .../bindings/timer/sifive,clint.txt | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt new file mode 100644 index 000000000000..cae2dad1223a --- /dev/null +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt @@ -0,0 +1,33 @@ +SiFive Core Local Interruptor (CLINT) +------------------------------------- + +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts. + +It directly connects to the timer and inter-processor interrupt lines of +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt +controller is the parent interrupt controller for CLINT device. + +The clock frequency of CLINT is specified via "timebase-frequency" DT +property of "/cpus" DT node. The "timebase-frequency" DT property is +described in: Documentation/devicetree/bindings/riscv/cpus.yaml + +Required properties: +- compatible : "sifive,clint-1.0.0" and a string identifying the actual + detailed implementation in case that specific bugs need to be worked around. +- reg : Should contain 1 register range (address and length). +- interrupts-extended : Specifies which HARTs (or CPUs) are connected to + the CLINT. Each node pointed to should be a riscv,cpu-intc node, which + has a riscv node as parent. + +Example: + + clint@2000000 { + compatible = "sifive,clint-1.0.0", "sifive,fu540-c000-clint"; + interrupts-extended = < + &cpu1-intc 3 &cpu1-intc 7 + &cpu2-intc 3 &cpu2-intc 7 + &cpu3-intc 3 &cpu3-intc 7 + &cpu4-intc 3 &cpu4-intc 7>; + reg = <0x2000000 0x4000000>; + };