From patchwork Sun May 24 21:06:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 200097 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65886C433E1 for ; Sun, 24 May 2020 21:06:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 41C4C207D8 for ; Sun, 24 May 2020 21:06:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=marek-ca.20150623.gappssmtp.com header.i=@marek-ca.20150623.gappssmtp.com header.b="afegZJP7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388362AbgEXVGw (ORCPT ); Sun, 24 May 2020 17:06:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388212AbgEXVG1 (ORCPT ); Sun, 24 May 2020 17:06:27 -0400 Received: from mail-qt1-x843.google.com (mail-qt1-x843.google.com [IPv6:2607:f8b0:4864:20::843]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E1C47C061A0E for ; Sun, 24 May 2020 14:06:26 -0700 (PDT) Received: by mail-qt1-x843.google.com with SMTP id m44so12543790qtm.8 for ; Sun, 24 May 2020 14:06:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IB735CxnLdulpWhY5dVCVlHnjZEUj+47Z7loFw0bHLc=; b=afegZJP77KSu+LmrLUf+eCMqlJypfVqSkrH8f3euV1CGZ5WuywPBReDBbp8/2MWEMb +zJjuFPf9RVzCMg0angUKn9U6lupAsSIQm92WTYRB1n9ozOHtRzjeNzTtuxds5vLHB2h IN0qSVLKeNm/owbAHgx71qST9loLJnWv2uXDKWuBfI7AvRkgSKWoDzRH90Hwow8J2uoK pAeC0zK0410Qpmj9qrSh6UIv0NGt0eLCXzmQ9bsBDr/YatarefYesBPmLGmlooBi9Gsc YZma+3XVp9QEbT47iLGeSNLsDulP8tLMtf+XHLnkYBvoa6fHvYUi/qt/juIybvDbti7y EBzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IB735CxnLdulpWhY5dVCVlHnjZEUj+47Z7loFw0bHLc=; b=m5l9rPPH49QYvaoGoTLE1Gzi+j3h7uH1ERe4QElZpZyNjWCc6PprA2Tg+7ra1CJc04 D3S8laSvNYI8l/F5P0/DmCMRLUgaJlwaNAsoUttTX/CKaPh49fJwowrJNoEEPjosjSbp FCZd/jD1FPKOHB5piQfo01DBiJHNzZjvWdTBur2pqShcX856eCbtIUZqdzloMbWCIAay f1vcKFqEHcDbmqPj3V+QsTV7I20vLOFqMqsT+Qdb0wsePYFcNQSOlw3bmuJOnCrI3hCH KSLq2Am4bGW0yR7A+tvF3GdBluBNfi5bjr68vSk8b9bxhTvYLNmc0vdkbl41BHVkjhUv 5dsg== X-Gm-Message-State: AOAM532Mz20FJpukp5b1Zyz0DPcZKGB5BDTAWCxXPM3CDDh0OqWc8Mm2 LkPIr2aB3svqVTl4CJL7LfAk9Q== X-Google-Smtp-Source: ABdhPJzm337i7AHVG8c2KaAAOBpmSSoD0D+hRZRsAXhyZSd7oibA7DcfFbEF4y8GebXWmC6GpxbGaQ== X-Received: by 2002:ac8:3529:: with SMTP id y38mr11483010qtb.315.1590354386108; Sun, 24 May 2020 14:06:26 -0700 (PDT) Received: from localhost.localdomain ([147.253.86.153]) by smtp.gmail.com with ESMTPSA id g51sm4401769qtb.69.2020.05.24.14.06.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 May 2020 14:06:25 -0700 (PDT) From: Jonathan Marek To: linux-arm-msm@vger.kernel.org Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-kernel@vger.kernel.org (open list), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 05/10] dt-bindings: clock: Introduce SM8150 QCOM Graphics clock bindings Date: Sun, 24 May 2020 17:06:06 -0400 Message-Id: <20200524210615.17035-6-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20200524210615.17035-1-jonathan@marek.ca> References: <20200524210615.17035-1-jonathan@marek.ca> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8150 SoCs. Signed-off-by: Jonathan Marek --- include/dt-bindings/clock/qcom,gpucc-sm8150.h | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8150.h diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8150.h b/include/dt-bindings/clock/qcom,gpucc-sm8150.h new file mode 100644 index 000000000000..e7cac7fe9739 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm8150.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H + +/* GPU_CC clock registers */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_APB_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CX_QDSS_AT_CLK 4 +#define GPU_CC_CX_QDSS_TRIG_CLK 5 +#define GPU_CC_CX_QDSS_TSCTR_CLK 6 +#define GPU_CC_CX_SNOC_DVM_CLK 7 +#define GPU_CC_CXO_AON_CLK 8 +#define GPU_CC_CXO_CLK 9 +#define GPU_CC_GMU_CLK_SRC 10 +#define GPU_CC_GX_GMU_CLK 11 +#define GPU_CC_GX_QDSS_TSCTR_CLK 12 +#define GPU_CC_GX_VSENSE_CLK 13 +#define GPU_CC_PLL1 14 +#define GPU_CC_PLL_TEST_CLK 15 +#define GPU_CC_SLEEP_CLK 16 + +/* GPU_CC Resets */ +#define GPUCC_GPU_CC_CX_BCR 0 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 1 +#define GPUCC_GPU_CC_GMU_BCR 2 +#define GPUCC_GPU_CC_GX_BCR 3 +#define GPUCC_GPU_CC_SPDM_BCR 4 +#define GPUCC_GPU_CC_XO_BCR 5 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From patchwork Sun May 24 21:06:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 200098 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D45DC433E4 for ; Sun, 24 May 2020 21:06:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6CE10207D8 for ; Sun, 24 May 2020 21:06:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=marek-ca.20150623.gappssmtp.com header.i=@marek-ca.20150623.gappssmtp.com header.b="SaeTcgNn" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388298AbgEXVGn (ORCPT ); Sun, 24 May 2020 17:06:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388265AbgEXVGd (ORCPT ); Sun, 24 May 2020 17:06:33 -0400 Received: from mail-qk1-x742.google.com (mail-qk1-x742.google.com [IPv6:2607:f8b0:4864:20::742]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11287C05BD43 for ; Sun, 24 May 2020 14:06:33 -0700 (PDT) Received: by mail-qk1-x742.google.com with SMTP id z80so16046376qka.0 for ; Sun, 24 May 2020 14:06:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c4VnJkkNORcnXVsefViOavxGbWlTLu5kwrmQ6DrqkvQ=; b=SaeTcgNnIrdJ8m5uLR3jhp+c9gJSwdrSG3yfaHKqk7QafEBO3e3oUSaIMJnOiH1s+N kCHAR1JIFUlnbKxbHoRtemu1mTOnDvxBdQ3/Cz1a/Xda42SroQ8exlp3X9HDOINBkK5K AmFHDca+jvBvI5CxzLsE1/R5YFNPUYG+hwytGos1dDYyYZkpX/Lbg+9Qzsz405pzwfH8 D1E0av4TSh3BO9B1dK2l6xuAF0g/Kbwj9OUoi2tvpF7q+QnD4pl8fl5yPj4LaU+ZLS3Y 8wj0YFlDCnesl78WiuSSk07Kvu7x7sbXBwqE5a/vvqUwBLRJEaE+fvdjUO4/TqnWiQ4R 5amA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c4VnJkkNORcnXVsefViOavxGbWlTLu5kwrmQ6DrqkvQ=; b=XkKuEnKPDd6GWT7jsT3kL1Fc+7dhNQG3uNmzycfOEOQzC1Warmun7jpMlNmQJTKjuL f5+2O3MfranV//xTAqsyX4ZuyBWuAq1Ed9KjhicJyg3/+uBhrlnV4jD7K3WjMpAmrOk4 lJ0IQkZw0ER5Ab57yScF8SkuxOlrlBj1w+rfIVzgXTkaHJU6fb4gAQZq3jQiwCkqZjWF qhcOBxzAFA0Cb3o/nwPiF8XZ1554JJq+TRDULncwhG6kLrMUgcIeKbgPot2D7R7Sogpc XKEo75eGRw+BQ0eMZQ3WbAGLle2KWbCcUpdmr3DZ0wPoNC5e7GW637B9ek3LQHntyY13 HCxA== X-Gm-Message-State: AOAM531yem8ORw96GGCLGU+S8qFSERKU+OcRC7YCVBcGB1nABglW9Jfj nCb28yL+C+KXRKM0KqMYIh+fSQ== X-Google-Smtp-Source: ABdhPJzto33NRO761giF2rceigWsUm197eO6eWMTp5L9x4kbF/xyxA7Cg7V4rIriKBtHuluzQeByJA== X-Received: by 2002:a05:620a:a53:: with SMTP id j19mr24846414qka.183.1590354392272; Sun, 24 May 2020 14:06:32 -0700 (PDT) Received: from localhost.localdomain ([147.253.86.153]) by smtp.gmail.com with ESMTPSA id g51sm4401769qtb.69.2020.05.24.14.06.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 May 2020 14:06:31 -0700 (PDT) From: Jonathan Marek To: linux-arm-msm@vger.kernel.org Cc: Andy Gross , Bjorn Andersson , Rob Herring , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 09/10] arm64: dts: qcom: add sm8150 GPU nodes Date: Sun, 24 May 2020 17:06:10 -0400 Message-Id: <20200524210615.17035-10-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20200524210615.17035-1-jonathan@marek.ca> References: <20200524210615.17035-1-jonathan@marek.ca> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This brings up the GPU. Tested on HDK855 by running vulkan CTS. Signed-off-by: Jonathan Marek --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 132 +++++++++++++++++++++++++++ 1 file changed, 132 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 903514fc299f..1996e42ccb28 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -540,6 +541,137 @@ glink-edge { }; }; + gpu: gpu@2c00000 { + /* + * note: the amd,imageon compatible makes it possible + * to use the drm/msm driver without the display node, + * make sure to remove it when display node is added + */ + compatible = "qcom,adreno-640.1", + "qcom,adreno", + "amd,imageon"; + #stream-id-cells = <16>; + + reg = <0 0x2c00000 0 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x401>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + zap-shader { + memory-region = <&gpu_mem>; + }; + + /* note: downstream checks gpu binning for 675 Mhz */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + opp-level = ; + }; + + opp-585000000 { + opp-hz = /bits/ 64 <585000000>; + opp-level = ; + }; + + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-level = ; + }; + + opp-427000000 { + opp-hz = /bits/ 64 <427000000>; + opp-level = ; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + opp-level = ; + }; + + opp-257000000 { + opp-hz = /bits/ 64 <257000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@2c6a000 { + compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; + + reg = <0 0x2c6a000 0 0x30000>, + <0 0xb290000 0 0x10000>, + <0 0xb490000 0 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + + iommus = <&adreno_smmu 5 0x400>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@2c90000 { + compatible = "qcom,sm8150-gpucc"; + reg = <0 0x2c90000 0 0x9000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + adreno_smmu: iommu@2ca0000 { + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; + reg = <0 0x2ca0000 0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "ahb", "bus", "iface"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + tlmm: pinctrl@3100000 { compatible = "qcom,sm8150-pinctrl"; reg = <0x0 0x03100000 0x0 0x300000>,