From patchwork Tue Jun 9 17:49:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Ratiu X-Patchwork-Id: 199286 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 829CBC433DF for ; Tue, 9 Jun 2020 18:21:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 690532068D for ; Tue, 9 Jun 2020 18:21:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388065AbgFISVj (ORCPT ); Tue, 9 Jun 2020 14:21:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41168 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732338AbgFIRsg (ORCPT ); Tue, 9 Jun 2020 13:48:36 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D44E2C05BD1E; Tue, 9 Jun 2020 10:48:35 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id EE60D2A09BC From: Adrian Ratiu To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Laurent Pinchart Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Heiko Stuebner , Philippe CORNU , Yannick FERTRE , Jernej Skrabec , Andrzej Hajda , Jonas Karlman , linux-imx@nxp.com, kernel@collabora.com, linux-stm32@st-md-mailman.stormreply.com, Adrian Pop , Arnaud Ferraris Subject: [PATCH v9 03/11] drm: bridge: dw_mipi_dsi: add dsi v1.01 support Date: Tue, 9 Jun 2020 20:49:51 +0300 Message-Id: <20200609174959.955926-4-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200609174959.955926-1-adrian.ratiu@collabora.com> References: <20200609174959.955926-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Synopsis MIPI DSI v1.01 host controller is quite widely used on platforms like i.mx6 and is not very different from the other versions like the 1.31/1.30 used on rockchip/stm. The protocols appear to be the same, only the register layout is different and the newer versions have new features symbolized by new registers so adding support for it is just a matter of defining the new layout and adding a couple of dsi version checks. Tested-by: Adrian Pop Tested-by: Arnaud Ferraris Signed-off-by: Adrian Ratiu --- Changes since v7: - Minor commit msg rewording for consistency Changes since v5: - Fixed cfg_phy_status range from [0,0] to [0,2] New in v5. --- drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 125 +++++++++++++++++- 1 file changed, 119 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index f453df4eb5072..16fd87055e7b7 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -32,6 +32,7 @@ #define HWVER_131 0x31333100 /* IP version 1.31 */ #define HWVER_130 0x31333000 /* IP version 1.30 */ +#define HWVER_101 0x31303000 /* IP version 1.01 */ #define DSI_VERSION 0x00 #define VERSION GENMASK(31, 8) @@ -100,6 +101,25 @@ #define DSI_EDPI_CMD_SIZE 0x64 #define DSI_CMD_MODE_CFG 0x68 + +#define DSI_DPI_CFG 0x0c +#define DSI_TMR_LINE_CFG 0x28 +#define DSI_VTIMING_CFG 0x2c +#define DSI_PHY_TMR_CFG_V101 0x30 +#define DSI_PHY_IF_CFG_V101 0x58 +#define DSI_PHY_IF_CTRL 0x5c +#define DSI_PHY_RSTZ_V101 0x54 +#define DSI_PHY_STATUS_V101 0x60 +#define DSI_PHY_TST_CTRL0_V101 0x64 +#define DSI_GEN_HDR_V101 0x34 +#define DSI_GEN_PLD_DATA_V101 0x38 +#define DSI_CMD_MODE_CFG_V101 0x24 +#define DSI_CMD_PKT_STATUS_V101 0x3c +#define DSI_VID_PKT_CFG 0x20 +#define DSI_VID_MODE_CFG_V101 0x1c +#define DSI_TO_CNT_CFG_V101 0x40 +#define DSI_PCKHDL_CFG_V101 0x18 + #define MAX_RD_PKT_SIZE_LP BIT(24) #define DCS_LW_TX_LP BIT(19) #define DCS_SR_0P_TX_LP BIT(18) @@ -127,6 +147,33 @@ GEN_SW_1P_TX_LP | \ GEN_SW_0P_TX_LP) +#define EN_TEAR_FX_V101 BIT(14) +#define DCS_LW_TX_LP_V101 BIT(12) +#define GEN_LW_TX_LP_V101 BIT(11) +#define MAX_RD_PKT_SIZE_LP_V101 BIT(10) +#define DCS_SW_2P_TX_LP_V101 BIT(9) +#define DCS_SW_1P_TX_LP_V101 BIT(8) +#define DCS_SW_0P_TX_LP_V101 BIT(7) +#define GEN_SR_2P_TX_LP_V101 BIT(6) +#define GEN_SR_1P_TX_LP_V101 BIT(5) +#define GEN_SR_0P_TX_LP_V101 BIT(4) +#define GEN_SW_2P_TX_LP_V101 BIT(3) +#define GEN_SW_1P_TX_LP_V101 BIT(2) +#define GEN_SW_0P_TX_LP_V101 BIT(1) + +#define CMD_MODE_ALL_LP_V101 (DCS_LW_TX_LP_V101 | \ + GEN_LW_TX_LP_V101 | \ + MAX_RD_PKT_SIZE_LP_V101 | \ + DCS_SW_2P_TX_LP_V101 | \ + DCS_SW_1P_TX_LP_V101 | \ + DCS_SW_0P_TX_LP_V101 | \ + GEN_SR_2P_TX_LP_V101 | \ + GEN_SR_1P_TX_LP_V101 | \ + GEN_SR_0P_TX_LP_V101 | \ + GEN_SW_2P_TX_LP_V101 | \ + GEN_SW_1P_TX_LP_V101 | \ + GEN_SW_0P_TX_LP_V101) + #define DSI_GEN_HDR 0x6c #define DSI_GEN_PLD_DATA 0x70 @@ -165,6 +212,11 @@ #define DSI_INT_MSK0 0xc4 #define DSI_INT_MSK1 0xc8 +#define DSI_ERROR_ST0_V101 0x44 +#define DSI_ERROR_ST1_V101 0x48 +#define DSI_ERROR_MSK0_V101 0x4c +#define DSI_ERROR_MSK1_V101 0x50 + #define DSI_PHY_TMR_RD_CFG 0xf4 #define PHY_STATUS_TIMEOUT_US 10000 @@ -359,6 +411,49 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = { .cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA, 0, 31), }; +static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = { + .cfg_dpi_vid = REG_FIELD(DSI_DPI_CFG, 0, 1), + .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_CFG, 2, 4), + .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_CFG, 10, 10), + .cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG, 6, 6), + .cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG, 7, 7), + .cfg_cmd_mode_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 0, 0), + .cfg_cmd_mode_all_lp_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 1, 12), + .cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 13, 13), + .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS_V101, 0, 14), + .cfg_vid_mode_en = REG_FIELD(DSI_VID_MODE_CFG_V101, 0, 0), + .cfg_vid_mode_type = REG_FIELD(DSI_VID_MODE_CFG_V101, 1, 2), + .cfg_vid_mode_low_power = REG_FIELD(DSI_VID_MODE_CFG_V101, 3, 8), + .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_CFG, 0, 10), + .cfg_vid_hsa_time = REG_FIELD(DSI_TMR_LINE_CFG, 0, 8), + .cfg_vid_hbp_time = REG_FIELD(DSI_TMR_LINE_CFG, 9, 17), + .cfg_vid_hline_time = REG_FIELD(DSI_TMR_LINE_CFG, 18, 31), + .cfg_vid_vsa_time = REG_FIELD(DSI_VTIMING_CFG, 0, 3), + .cfg_vid_vbp_time = REG_FIELD(DSI_VTIMING_CFG, 4, 9), + .cfg_vid_vfp_time = REG_FIELD(DSI_VTIMING_CFG, 10, 15), + .cfg_vid_vactive_time = REG_FIELD(DSI_VTIMING_CFG, 16, 26), + .cfg_phy_txrequestclkhs = REG_FIELD(DSI_PHY_IF_CTRL, 0, 0), + .cfg_phy_bta_time = REG_FIELD(DSI_PHY_TMR_CFG_V101, 0, 11), + .cfg_phy_lp2hs_time = REG_FIELD(DSI_PHY_TMR_CFG_V101, 12, 19), + .cfg_phy_hs2lp_time = REG_FIELD(DSI_PHY_TMR_CFG_V101, 20, 27), + .cfg_phy_testclr = REG_FIELD(DSI_PHY_TST_CTRL0_V101, 0, 0), + .cfg_phy_unshutdownz = REG_FIELD(DSI_PHY_RSTZ_V101, 0, 0), + .cfg_phy_unrstz = REG_FIELD(DSI_PHY_RSTZ_V101, 1, 1), + .cfg_phy_enableclk = REG_FIELD(DSI_PHY_RSTZ_V101, 2, 2), + .cfg_phy_nlanes = REG_FIELD(DSI_PHY_IF_CFG_V101, 0, 1), + .cfg_phy_stop_wait_time = REG_FIELD(DSI_PHY_IF_CFG_V101, 2, 9), + .cfg_phy_status = REG_FIELD(DSI_PHY_STATUS_V101, 0, 2), + .cfg_pckhdl_cfg = REG_FIELD(DSI_PCKHDL_CFG_V101, 0, 4), + .cfg_hstx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG_V101, 0, 15), + .cfg_lprx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG_V101, 16, 31), + .cfg_int_stat0 = REG_FIELD(DSI_ERROR_ST0_V101, 0, 20), + .cfg_int_stat1 = REG_FIELD(DSI_ERROR_ST1_V101, 0, 17), + .cfg_int_mask0 = REG_FIELD(DSI_ERROR_MSK0_V101, 0, 20), + .cfg_int_mask1 = REG_FIELD(DSI_ERROR_MSK1_V101, 0, 17), + .cfg_gen_hdr = REG_FIELD(DSI_GEN_HDR_V101, 0, 31), + .cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA_V101, 0, 31), +}; + /* * Check if either a link to a master or slave is present */ @@ -466,6 +561,9 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, case HWVER_131: cmd_mode_lp = CMD_MODE_ALL_LP; break; + case HWVER_101: + cmd_mode_lp = CMD_MODE_ALL_LP_V101; + break; } if (msg->flags & MIPI_DSI_MSG_REQ_ACK) @@ -644,7 +742,7 @@ static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) VID_MODE_TYPE_NON_BURST_SYNC_EVENTS); #ifdef CONFIG_DEBUG_FS - if (dsi->vpg) { + if (dsi->hw_version > HWVER_101 && dsi->vpg) { regmap_field_write(dsi->field_vid_mode_vpg_en, 1); regmap_field_write(dsi->field_vid_mode_vpg_horiz, dsi->vpg_horizontal ? 1 : 0); @@ -662,9 +760,15 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, dw_mipi_dsi_video_mode_config(dsi); + if (dsi->hw_version == HWVER_101) + regmap_field_write(dsi->field_vid_mode_en, 1); + regmap_field_write(dsi->field_phy_txrequestclkhs, 1); } else { regmap_field_write(dsi->field_cmd_mode_en, 1); + + if (dsi->hw_version == HWVER_101) + regmap_field_write(dsi->field_vid_mode_en, 0); } regmap_write(dsi->regs, DSI_PWR_UP, POWERUP); @@ -856,9 +960,13 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) regmap_field_write(dsi->field_phy_lp2hs_time, timing.data_lp2hs); regmap_field_write(dsi->field_phy_hs2lp_time, timing.data_hs2lp); - regmap_field_write(dsi->field_phy_max_rd_time, 10000); - regmap_field_write(dsi->field_phy_clkhs2lp_time, timing.clk_hs2lp); - regmap_field_write(dsi->field_phy_clklp2hs_time, timing.clk_lp2hs); + if (dsi->hw_version > HWVER_101) { + regmap_field_write(dsi->field_phy_max_rd_time, 10000); + regmap_field_write(dsi->field_phy_clkhs2lp_time, + timing.clk_hs2lp); + regmap_field_write(dsi->field_phy_clklp2hs_time, + timing.clk_lp2hs); + } } static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) @@ -879,7 +987,8 @@ static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi) regmap_field_write(dsi->field_phy_unrstz, 0); regmap_field_write(dsi->field_phy_unshutdownz, 0); - regmap_field_write(dsi->field_phy_forcepll, 0); + if (dsi->hw_version > HWVER_101) + regmap_field_write(dsi->field_phy_forcepll, 0); regmap_field_write(dsi->field_phy_testclr, 0); regmap_field_write(dsi->field_phy_testclr, 1); @@ -895,7 +1004,8 @@ static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) regmap_field_write(dsi->field_phy_unrstz, 1); regmap_field_write(dsi->field_phy_unshutdownz, 1); - regmap_field_write(dsi->field_phy_forcepll, 1); + if (dsi->hw_version > HWVER_101) + regmap_field_write(dsi->field_phy_forcepll, 1); ret = regmap_field_read_poll_timeout(dsi->field_phy_status, val, val & PHY_LOCK, @@ -1132,6 +1242,9 @@ static int dw_mipi_dsi_regmap_fields_init(struct dw_mipi_dsi *dsi) case HWVER_131: variant = &dw_mipi_dsi_v130_v131_layout; break; + case HWVER_101: + variant = &dw_mipi_dsi_v101_layout; + break; default: DRM_ERROR("Unrecognized DSI host controller HW revision\n"); return -ENODEV; From patchwork Tue Jun 9 17:49:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Ratiu X-Patchwork-Id: 199293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF0C0C433DF for ; Tue, 9 Jun 2020 17:48:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D462320823 for ; Tue, 9 Jun 2020 17:48:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730644AbgFIRsk (ORCPT ); Tue, 9 Jun 2020 13:48:40 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:51766 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732342AbgFIRsi (ORCPT ); Tue, 9 Jun 2020 13:48:38 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id BD25F2A3BE2 From: Adrian Ratiu To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Laurent Pinchart Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Heiko Stuebner , Philippe CORNU , Yannick FERTRE , Jernej Skrabec , Andrzej Hajda , Jonas Karlman , linux-imx@nxp.com, kernel@collabora.com, linux-stm32@st-md-mailman.stormreply.com, Rob Herring , Neil Armstrong , Fabio Estevam , Laurent Pinchart , Adrian Pop , Arnaud Ferraris , Sjoerd Simons , Martyn Welch Subject: [PATCH v9 05/11] dt-bindings: display: add i.MX6 MIPI DSI host controller doc Date: Tue, 9 Jun 2020 20:49:53 +0300 Message-Id: <20200609174959.955926-6-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200609174959.955926-1-adrian.ratiu@collabora.com> References: <20200609174959.955926-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This provides an example DT binding for the MIPI DSI host controller present on the i.MX6 SoC based on Synopsis DesignWare v1.01 IP. Cc: Rob Herring Cc: Neil Armstrong Cc: Fabio Estevam Cc: Laurent Pinchart Cc: devicetree@vger.kernel.org Tested-by: Adrian Pop Tested-by: Arnaud Ferraris Signed-off-by: Sjoerd Simons Signed-off-by: Martyn Welch Signed-off-by: Adrian Ratiu --- Changes since v8: - Fixed small compatible string typo caught by checkpatch - Added custom select for 'fsl,imx6-mipi-dsi' (Rob) - Replaced additionalProperties -> unevaluatedProperties (Rob) - Dropped all nodes not adding any new constraints apart from the recently upstreamed snps,dw-mipi-dsi.yaml (Rob) Changes since v7: - Clarified port@0,1 descriptions, marked them as required and added missing port@0 in example (Laurent) Changes since v6: - Added ref to the newly created snps,dw-mipi-dsi.yaml (Laurent) - Moved *-cells properties outside patternProperties (Laurent) - Removed the panel port documentation (Laurent) - Wrapped lines at 80 chars, typo fixes, sort includes (Laurent) Changes since v5: - Fixed missing reg warning (Fabio) - Updated dt-schema and fixed warnings (Rob) Changes since v4: - Fixed yaml binding to pass `make dt_binding_check dtbs_check` and addressed received binding feedback (Rob) Changes since v3: - Added commit message (Neil) - Converted to yaml format (Neil) - Minor dt node + driver fixes (Rob) - Added small panel example to the host controller binding Changes since v2: - Fixed commit tags (Emil) --- .../display/imx/fsl,mipi-dsi-imx6.yaml | 112 ++++++++++++++++++ 1 file changed, 112 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml diff --git a/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml new file mode 100644 index 0000000000000..86093729fd5f9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,mipi-dsi-imx6.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX6 DW MIPI DSI Host Controller + +maintainers: + - Adrian Ratiu + +description: | + The i.MX6 DSI host controller is a Synopsys DesignWare MIPI DSI v1.01 + IP block with a companion PHY IP. + + These DT bindings follow the Synopsys DW MIPI DSI bindings defined in + Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with + the following device-specific properties. + +allOf: + - $ref: ../bridge/snps,dw-mipi-dsi.yaml# + +# Need a custom select here or 'snps,dw-mipi-dsi' will match lots of nodes +select: + properties: + compatible: + contains: + enum: + - fsl,imx6-mipi-dsi + required: + - compatible + +properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + compatible: + items: + - const: fsl,imx6-mipi-dsi + - const: snps,dw-mipi-dsi + + interrupts: + maxItems: 1 + + fsl,gpr: + description: + Phandle to the iomuxc-gpr region containing the multiplexer ctrl register. + $ref: /schemas/types.yaml#/definitions/phandle + +unevaluatedProperties: false + +required: + - "#address-cells" + - "#size-cells" + - compatible + - interrupts + +examples: + - |+ + #include + #include + #include + + dsi: dsi@21e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x021e0000 0x4000>; + interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; + fsl,gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>, + <&clks IMX6QDL_CLK_MIPI_IPG>; + clock-names = "ref", "pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + mipi_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_mipi>; + }; + }; + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel@0 { + compatible = "sharp,ls032b3sx01"; + reg = <0>; + reset-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; + }; + +... From patchwork Tue Jun 9 17:49:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Ratiu X-Patchwork-Id: 199288 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2724CC433E4 for ; Tue, 9 Jun 2020 18:21:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 142EB2067B for ; Tue, 9 Jun 2020 18:21:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388962AbgFISVL (ORCPT ); Tue, 9 Jun 2020 14:21:11 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:51740 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732358AbgFIRsl (ORCPT ); Tue, 9 Jun 2020 13:48:41 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id E95962A0752 From: Adrian Ratiu To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Laurent Pinchart Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Heiko Stuebner , Philippe CORNU , Yannick FERTRE , Jernej Skrabec , Andrzej Hajda , Jonas Karlman , linux-imx@nxp.com, kernel@collabora.com, linux-stm32@st-md-mailman.stormreply.com, Emil Velikov , Adrian Pop , Arnaud Ferraris Subject: [PATCH v9 08/11] drm: stm: dw-mipi-dsi: let the bridge handle the HW version check Date: Tue, 9 Jun 2020 20:49:56 +0300 Message-Id: <20200609174959.955926-9-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200609174959.955926-1-adrian.ratiu@collabora.com> References: <20200609174959.955926-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The stm mipi-dsi platform driver added a version test in commit fa6251a747b7 ("drm/stm: dsi: check hardware version") so that HW revisions other than v1.3x get rejected. The rockchip driver had no such check and just assumed register layouts are v1.3x compatible. Having such tests was a good idea because only v130/v131 layouts were supported at the time, however since adding multiple layout support in the bridge, the version is automatically checked for all drivers, compatible layouts get picked and unsupported HW is automatically rejected by the bridge, so there's no use keeping the test in the stm driver. The main reason prompting this change is that the stm driver test immediately disabled the peripheral clock after reading the version, making the bridge read version 0x0 immediately after in its own probe(), so we move the clock disabling after the bridge does the version test. Tested on STM32F769 and STM32MP1. Cc: linux-stm32@st-md-mailman.stormreply.com Cc: Emil Velikov Reported-by: Adrian Pop Tested-by: Adrian Pop Tested-by: Arnaud Ferraris Signed-off-by: Adrian Ratiu --- New in v6. --- drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c index 2e1f2664495d0..45f67f8a5f6c8 100644 --- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c +++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c @@ -396,26 +396,19 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev) goto err_dsi_probe; } + /* enable pclk so MMIO register values can be read, else reads == 0x0 */ ret = clk_prepare_enable(pclk); if (ret) { DRM_ERROR("%s: Failed to enable peripheral clk\n", __func__); goto err_dsi_probe; } - dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; - clk_disable_unprepare(pclk); - - if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) { - ret = -ENODEV; - DRM_ERROR("bad dsi hardware version\n"); - goto err_dsi_probe; - } - dw_mipi_dsi_stm_plat_data.base = dsi->base; dw_mipi_dsi_stm_plat_data.priv_data = dsi; platform_set_drvdata(pdev, dsi); + /* setup the bridge, this will also access MMIO registers via regmap */ dsi->dsi = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data); if (IS_ERR(dsi->dsi)) { ret = PTR_ERR(dsi->dsi); @@ -423,6 +416,11 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev) goto err_dsi_probe; } + dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; + + /* initial MMIO config done, disable clk to save power */ + clk_disable_unprepare(pclk); + return 0; err_dsi_probe: From patchwork Tue Jun 9 17:49:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Ratiu X-Patchwork-Id: 199287 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D5CCC433DF for ; Tue, 9 Jun 2020 18:21:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7A1652067B for ; Tue, 9 Jun 2020 18:21:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388966AbgFISVL (ORCPT ); Tue, 9 Jun 2020 14:21:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732369AbgFIRsm (ORCPT ); Tue, 9 Jun 2020 13:48:42 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4043C05BD1E; Tue, 9 Jun 2020 10:48:42 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id C6E2A2A3B96 From: Adrian Ratiu To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Laurent Pinchart Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Heiko Stuebner , Philippe CORNU , Yannick FERTRE , Jernej Skrabec , Andrzej Hajda , Jonas Karlman , linux-imx@nxp.com, kernel@collabora.com, linux-stm32@st-md-mailman.stormreply.com, Adrian Pop , Arnaud Ferraris Subject: [PATCH v9 10/11] drm: bridge: dw-mipi-dsi: fix bad register field offsets Date: Tue, 9 Jun 2020 20:49:58 +0300 Message-Id: <20200609174959.955926-11-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200609174959.955926-1-adrian.ratiu@collabora.com> References: <20200609174959.955926-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org According to the DSI Host Registers sections available in the IMX, STM and RK ref manuals for 1.01, 1.30 and 1.31, the register fields are smaller or bigger than what's coded in the driver, leading to r/w in reserved spaces which might cause undefined behaviours. Tested-by: Adrian Pop Tested-by: Arnaud Ferraris Signed-off-by: Adrian Ratiu --- New in v6. --- drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 46 +++++++++---------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 1e47d40b5becb..d274216c5a7c2 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -316,7 +316,7 @@ struct dw_mipi_dsi_variant { static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = { .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_COLOR_CODING, 0, 3), .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_COLOR_CODING, 8, 8), - .cfg_dpi_vid = REG_FIELD(DSI_DPI_VCID, 0, 2), + .cfg_dpi_vid = REG_FIELD(DSI_DPI_VCID, 0, 1), .cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 1, 1), .cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 2, 2), .cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG, 1, 1), @@ -325,29 +325,29 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = { .cfg_cmd_mode_dcs_sw_sr_en = REG_FIELD(DSI_CMD_MODE_CFG, 16, 18), .cfg_cmd_mode_dcs_lw_en = REG_FIELD(DSI_CMD_MODE_CFG, 19, 19), .cfg_cmd_mode_max_rd_pkt_size = REG_FIELD(DSI_CMD_MODE_CFG, 24, 24), - .cfg_cmd_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 31), - .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS, 0, 31), - .cfg_vid_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 31), + .cfg_cmd_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 0), + .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS, 0, 6), + .cfg_vid_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 0), .cfg_vid_mode_type = REG_FIELD(DSI_VID_MODE_CFG, 0, 1), .cfg_vid_mode_low_power = REG_FIELD(DSI_VID_MODE_CFG, 8, 13), .cfg_vid_mode_vpg_en = REG_FIELD(DSI_VID_MODE_CFG, 16, 16), .cfg_vid_mode_vpg_horiz = REG_FIELD(DSI_VID_MODE_CFG, 24, 24), - .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 10), - .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 31), - .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 31), - .cfg_vid_hline_time = REG_FIELD(DSI_VID_HLINE_TIME, 0, 31), - .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 31), - .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 31), - .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 31), - .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 31), + .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 13), + .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 11), + .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 11), + .cfg_vid_hline_time = REG_FIELD(DSI_VID_HLINE_TIME, 0, 14), + .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 9), + .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 9), + .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 9), + .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 13), .cfg_phy_txrequestclkhs = REG_FIELD(DSI_LPCLK_CTRL, 0, 0), - .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 31), - .cfg_phy_max_rd_time = REG_FIELD(DSI_PHY_TMR_CFG, 0, 15), + .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 15), + .cfg_phy_max_rd_time = REG_FIELD(DSI_PHY_TMR_CFG, 0, 14), .cfg_phy_lp2hs_time = REG_FIELD(DSI_PHY_TMR_CFG, 16, 23), .cfg_phy_hs2lp_time = REG_FIELD(DSI_PHY_TMR_CFG, 24, 31), - .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 15), - .cfg_phy_lp2hs_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 0, 15), - .cfg_phy_hs2lp_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 16, 31), + .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 14), + .cfg_phy_lp2hs_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 0, 9), + .cfg_phy_hs2lp_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 16, 25), .cfg_phy_clklp2hs_time = REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 0, 15), .cfg_phy_clkhs2lp_time = REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 16, 31), .cfg_phy_testclr = REG_FIELD(DSI_PHY_TST_CTRL0, 0, 0), @@ -361,11 +361,11 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = { .cfg_pckhdl_cfg = REG_FIELD(DSI_PCKHDL_CFG, 0, 4), .cfg_hstx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG, 16, 31), .cfg_lprx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG, 0, 15), - .cfg_int_stat0 = REG_FIELD(DSI_INT_ST0, 0, 31), - .cfg_int_stat1 = REG_FIELD(DSI_INT_ST1, 0, 31), - .cfg_int_mask0 = REG_FIELD(DSI_INT_MSK0, 0, 31), - .cfg_int_mask1 = REG_FIELD(DSI_INT_MSK1, 0, 31), - .cfg_gen_hdr = REG_FIELD(DSI_GEN_HDR, 0, 31), + .cfg_int_stat0 = REG_FIELD(DSI_INT_ST0, 0, 20), + .cfg_int_stat1 = REG_FIELD(DSI_INT_ST1, 0, 12), + .cfg_int_mask0 = REG_FIELD(DSI_INT_MSK0, 0, 20), + .cfg_int_mask1 = REG_FIELD(DSI_INT_MSK1, 0, 12), + .cfg_gen_hdr = REG_FIELD(DSI_GEN_HDR, 0, 23), .cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA, 0, 31), }; @@ -382,7 +382,7 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = { .cfg_cmd_mode_gen_lw_en = REG_FIELD(DSI_CMD_MODE_CFG, 11, 11), .cfg_cmd_mode_dcs_lw_en = REG_FIELD(DSI_CMD_MODE_CFG, 12, 12), .cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 13, 13), - .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS_V101, 0, 14), + .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS_V101, 0, 6), .cfg_vid_mode_en = REG_FIELD(DSI_VID_MODE_CFG_V101, 0, 0), .cfg_vid_mode_type = REG_FIELD(DSI_VID_MODE_CFG_V101, 1, 2), .cfg_vid_mode_low_power = REG_FIELD(DSI_VID_MODE_CFG_V101, 3, 8), From patchwork Tue Jun 9 17:49:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Ratiu X-Patchwork-Id: 199289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D20E2C433E1 for ; Tue, 9 Jun 2020 18:20:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B1E732067B for ; Tue, 9 Jun 2020 18:20:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388936AbgFISUz (ORCPT ); Tue, 9 Jun 2020 14:20:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730905AbgFIRso (ORCPT ); Tue, 9 Jun 2020 13:48:44 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4E12C03E97C; Tue, 9 Jun 2020 10:48:43 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id B100A2A3B92 From: Adrian Ratiu To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Laurent Pinchart Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Heiko Stuebner , Philippe CORNU , Yannick FERTRE , Jernej Skrabec , Andrzej Hajda , Jonas Karlman , linux-imx@nxp.com, kernel@collabora.com, linux-stm32@st-md-mailman.stormreply.com, Boris Brezillon , Sam Ravnborg , Daniel Vetter Subject: [PATCH v9 11/11] Documentation: gpu: todo: Add dw-mipi-dsi consolidation plan Date: Tue, 9 Jun 2020 20:49:59 +0300 Message-Id: <20200609174959.955926-12-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200609174959.955926-1-adrian.ratiu@collabora.com> References: <20200609174959.955926-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This documents the longer-term plan to cleanup the dw-mipi-dsi bridge based drivers after the regmap refactor and i.MX6 driver have landed. The goal is to get the entire bridge logic in one place and continue the refactorings under the drm/bridge tree. Cc: Laurent Pinchart Cc: Boris Brezillon Cc: Sam Ravnborg Cc: Daniel Vetter Signed-off-by: Adrian Ratiu --- Documentation/gpu/todo.rst | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst index 658b52f7ffc6c..2b142980a4b16 100644 --- a/Documentation/gpu/todo.rst +++ b/Documentation/gpu/todo.rst @@ -548,6 +548,31 @@ See drivers/gpu/drm/amd/display/TODO for tasks. Contact: Harry Wentland, Alex Deucher +Reorganize dw-mipi-dsi bridge-based host-controller drivers +----------------------------------------------------------- + +The Synopsys DW MIPI DSI bridge is used by a number of SoC platform drivers +(STM, Rockchip, i.MX) which don't cleanly encapsulate their bridge logic which +gets split between the Synopsys bridge (drm/bridge/synopsys/dw-mipi-dsi.c) and +platform drivers like drm/imx/dw_mipi_dsi-imx6.c by passing around the bridge +configuration regmap, creating new bridges / daisy chaining in platform drivers, +duplicating encoder creation, having too much encoder logic instead of using the +simple encoder interface and so on. + +The goal of this rework is to make the dw-mipi-dsi driver a better encapsulated +bridge by moving all bridge-related logic under drm/bridge, including the SoC +bindings which chain to the core Synopsys code under drm/bridge/dw-mipi-dsi/ +from which they can be further consolidated and cleaned up. + +If this goal proves to be impossible then drm_bridge might not be the correct +abstraction for these host controllers and unifying their logic into a helper +library encapsulating a drm_encoder might be more desirable, in other words to +move away from drm_bridge entirely. + +Contact: Adrian Ratiu, Daniel Vetter, Laurent Pinchart + +Level: Intermediate + Bootsplash ==========