From patchwork Fri Jun 19 08:04:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: EastL Lee X-Patchwork-Id: 198830 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E23AC433E0 for ; Fri, 19 Jun 2020 08:06:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DE5B4207FC for ; Fri, 19 Jun 2020 08:06:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="jW5Z9Bx2" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731182AbgFSIGc (ORCPT ); Fri, 19 Jun 2020 04:06:32 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:20115 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1731184AbgFSIGM (ORCPT ); Fri, 19 Jun 2020 04:06:12 -0400 X-UUID: 62735648027b42f5a0a5a67ccf2d4aa7-20200619 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=UtXQMNPiKcI1teux/iFeLY1Gk2pKVYDIwGiIqNOtybw=; b=jW5Z9Bx2K6HqBA/v9tHRhB2z80MJaXfvJG2L3I2TYpcXKA1I2gEIxYSVkYeBA6VDkIly2sPh5qsdDYmBpsJ9KtiMwPONUlL7CfrVHSDOF8J6WuQd9l/Oe8p2NL07e6PdzgFeLq4TJ6+9k5FRyvjyRS6i2c4dM4k0dZPRq5KVx8M=; X-UUID: 62735648027b42f5a0a5a67ccf2d4aa7-20200619 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 972338632; Fri, 19 Jun 2020 16:06:06 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 19 Jun 2020 16:05:06 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 19 Jun 2020 16:05:06 +0800 From: EastL To: Sean Wang CC: , , , , , , , , , , EastL Subject: [PATCH v5 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings Date: Fri, 19 Jun 2020 16:04:59 +0800 Message-ID: <1592553902-30592-2-git-send-email-EastL.Lee@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1592553902-30592-1-git-send-email-EastL.Lee@mediatek.com> References: <1592553902-30592-1-git-send-email-EastL.Lee@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 03BA4C7E34FC566C1EE83D711BB1655A4B129E4C11B45DF4651B520F2DD073182000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the devicetree bindings for MediaTek Command-Queue DMA controller which could be found on MT6779 SoC or other similar Mediatek SoCs. Signed-off-by: EastL --- .../devicetree/bindings/dma/mtk-cqdma.yaml | 114 +++++++++++++++++++++ 1 file changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml -- 1.9.1 diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml new file mode 100644 index 0000000..e6fdf05 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Command-Queue DMA controller Device Tree Binding + +maintainers: + - EastL Lee + +description: + MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC + is dedicated to memory-to-memory transfer through queue based + descriptor management. + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + "#dma-cells": + minimum: 1 + maximum: 255 + description: + Used to provide DMA controller specific information. + + compatible: + oneOf: + - const: mediatek,common-cqdma + - const: mediatek,mt6765-cqdma + - const: mediatek,mt6779-cqdma + + reg: + minItems: 1 + maxItems: 5 + description: + A base address of MediaTek Command-Queue DMA controller, + a channel will have a set of base address. + + interrupts: + minItems: 1 + maxItems: 5 + description: + A interrupt number of MediaTek Command-Queue DMA controller, + one interrupt number per dma-channels. + + clocks: + maxItems: 1 + + clock-names: + const: cqdma + + dma-channel-mask: + $ref: /schemas/types.yaml#definitions/uint32 + description: + For DMA capability, We will know the addressing capability of + MediaTek Command-Queue DMA controller through dma-channel-mask. + items: + minItems: 1 + maxItems: 63 + + dma-channels: + $ref: /schemas/types.yaml#definitions/uint32 + description: + Number of DMA channels supported by MediaTek Command-Queue DMA + controller, support up to five. + items: + minItems: 1 + maxItems: 5 + + dma-requests: + $ref: /schemas/types.yaml#definitions/uint32 + description: + Number of DMA request (virtual channel) supported by MediaTek + Command-Queue DMA controller, support up to 32. + items: + minItems: 1 + maxItems: 32 + +required: + - "#dma-cells" + - compatible + - reg + - interrupts + - clocks + - clock-names + - dma-channel-mask + - dma-channels + - dma-requests + +additionalProperties: false + +examples: + - | + #include + #include + #include + cqdma: dma-controller@10212000 { + compatible = "mediatek,mt6779-cqdma"; + reg = <0x10212000 0x80>, + <0x10212080 0x80>, + <0x10212100 0x80>; + interrupts = , + , + ; + clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>; + clock-names = "cqdma"; + dma-channel-mask = <63>; + dma-channels = <3>; + dma-requests = <32>; + #dma-cells = <1>; + }; + +... From patchwork Fri Jun 19 08:05:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: EastL Lee X-Patchwork-Id: 198831 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3427DC433E0 for ; Fri, 19 Jun 2020 08:05:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 151802080C for ; Fri, 19 Jun 2020 08:05:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="ClaWGkPI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731130AbgFSIFU (ORCPT ); Fri, 19 Jun 2020 04:05:20 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:61126 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1731014AbgFSIFR (ORCPT ); Fri, 19 Jun 2020 04:05:17 -0400 X-UUID: b26bcc8d838d418f9f82ad9c66d0b376-20200619 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ySEtHTH57bxejrMtxUW7baRYR2KhL0kU2xryPA6GWeY=; b=ClaWGkPI9RpLVoRnBZifvdim+xIqrjdZPjEAOWfc3U9cAl8zghRfsiYu7/cOHk0NzeSE5JglQJOYwOjQY9ssN4NVngve7nT4mBTFGv7NMBvrXlzmqEtF8E3laAwL3eL1CRQ6mScKDdleuysXyDNqn25QnTHepArv5ZSIYpKdYpk=; X-UUID: b26bcc8d838d418f9f82ad9c66d0b376-20200619 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 344117436; Fri, 19 Jun 2020 16:05:13 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 19 Jun 2020 16:05:06 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 19 Jun 2020 16:05:08 +0800 From: EastL To: Sean Wang CC: , , , , , , , , , , EastL Subject: [PATCH v5 3/4] dmaengine: mediatek-cqdma: add dma mask for capability Date: Fri, 19 Jun 2020 16:05:01 +0800 Message-ID: <1592553902-30592-4-git-send-email-EastL.Lee@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1592553902-30592-1-git-send-email-EastL.Lee@mediatek.com> References: <1592553902-30592-1-git-send-email-EastL.Lee@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 5F99345FA7F246BBF9849BD1CEB69989773CB4DE139E4BBB3040F4B2C603A3392000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch add dma mask for capability. Signed-off-by: EastL --- drivers/dma/mediatek/mtk-cqdma.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 1.9.1 diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c index 905bbcb..ed33c64 100644 --- a/drivers/dma/mediatek/mtk-cqdma.c +++ b/drivers/dma/mediatek/mtk-cqdma.c @@ -117,6 +117,7 @@ struct mtk_cqdma_vchan { * @clk: The clock that device internal is using * @dma_requests: The number of VCs the device supports to * @dma_channels: The number of PCs the device supports to + * @dma_mask: A mask for DMA capability * @vc: The pointer to all available VCs * @pc: The pointer to all the underlying PCs */ @@ -126,6 +127,7 @@ struct mtk_cqdma_device { u32 dma_requests; u32 dma_channels; + u32 dma_mask; struct mtk_cqdma_vchan *vc; struct mtk_cqdma_pchan **pc; }; @@ -607,6 +609,21 @@ static int mtk_cqdma_probe(struct platform_device *pdev) cqdma->dma_channels = MTK_CQDMA_NR_PCHANS; } + if (pdev->dev.of_node) + err = of_property_read_u32(pdev->dev.of_node, + "dma-channel-mask", + &cqdma->dma_mask); + if (err) { + dev_warn(&pdev->dev, + "Using 0 as missing dma-channel-mask property\n"); + cqdma->dma_mask = 0; + } + + if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(cqdma->dma_mask))) { + dev_warn(&pdev->dev, "DMA set mask fail\n"); + return -EINVAL; + } + cqdma->pc = devm_kcalloc(&pdev->dev, cqdma->dma_channels, sizeof(*cqdma->pc), GFP_KERNEL); if (!cqdma->pc)