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dkim=none (message not signed) header.d=none; dabbelt.com; dmarc=none action=none header.from=wdc.com; Received: from MN2PR04MB6207.namprd04.prod.outlook.com (2603:10b6:208:de::32) by MN2PR04MB5599.namprd04.prod.outlook.com (2603:10b6:208:fe::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3131.21; Sat, 27 Jun 2020 16:20:47 +0000 Received: from MN2PR04MB6207.namprd04.prod.outlook.com ([fe80::e0ef:7fce:ff0d:f580]) by MN2PR04MB6207.namprd04.prod.outlook.com ([fe80::e0ef:7fce:ff0d:f580%7]) with mapi id 15.20.3131.026; Sat, 27 Jun 2020 16:20:47 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Rob Herring , Daniel Lezcano , Thomas Gleixner Cc: Damien Le Moal , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v2 1/5] RISC-V: Add mechanism to provide custom IPI operations Date: Sat, 27 Jun 2020 21:49:53 +0530 Message-Id: <20200627161957.134376-2-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200627161957.134376-1-anup.patel@wdc.com> References: <20200627161957.134376-1-anup.patel@wdc.com> X-ClientProxiedBy: MAXPR0101CA0029.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:d::15) To MN2PR04MB6207.namprd04.prod.outlook.com (2603:10b6:208:de::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (42.109.128.251) by MAXPR0101CA0029.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:d::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3131.21 via Frontend Transport; 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PTR:; CAT:NONE; SFTY:; SFS:(4636009)(39860400002)(376002)(366004)(346002)(396003)(136003)(5660300002)(8936002)(86362001)(186003)(16526019)(7416002)(1076003)(8676002)(956004)(2616005)(8886007)(110136005)(36756003)(54906003)(83380400001)(26005)(55016002)(316002)(44832011)(66946007)(52116002)(1006002)(478600001)(2906002)(7696005)(66556008)(6666004)(66476007)(4326008); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: bxS8QswaBlw+aoRioS/WiPILQ1ghR3Y0qy58PE5sompHnq0EeZtfybi6wWBRQX6r6rAZfmcKfn7j+t5ZRhFUOjEeR9ALeKUh8L3tVYzHvEZPF0Kygxo4bMH8V16dmN3Rorl/A5FVXHTuzzoeSGip7JjB/cByXUVh7TIuvFkOtffV1JJHKafPKBmUT6OIa4CzOIkFbBufV/1MT3r+QO4GRwDxnArOw4nSUJcvnce4VTIJ/XbKy1rnTcYoOH28hdXxsS7jFpx+IPMFl6CujPBGirTPVsKodRoWYKuPM0ECNtnD5PekbKnXuRqVRKVNScNU2hfKk4siWsUHV3AVip2mcCqh1cIjSsbRl2DQKx42VrdRHanWyiBUToyoplVC0MyfBt+YMf+nLmGxo+g/I8jo2/A3qYKiHPPdwPBBMRnwp0KC7uq1XfPh8M75x+7E84psMlWvVYIeMrzFzvRbbW8YxBowRbdYvlj8CqgDsNBueoHTbMwZq+kiyGOQ9fSCeUhT X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: bfe2680b-c558-4188-42b6-08d81ab60c3d X-MS-Exchange-CrossTenant-AuthSource: MN2PR04MB6207.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2020 16:20:47.3481 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: IlQ8W6ksLG3Jp7byXtLF04gX3uNKE2FegYYYAU5H9u0+SvUV8FrSPAlgGCm+YrdfgLkmtuL7QPFlUDtgjEeftg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5599 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We add mechanism to set custom IPI operations so that CLINT driver from drivers directory can provide custom IPI operations. Signed-off-by: Anup Patel --- arch/riscv/include/asm/smp.h | 11 +++++++++ arch/riscv/kernel/sbi.c | 14 ++++++++++++ arch/riscv/kernel/smp.c | 43 ++++++++++++++++++++---------------- arch/riscv/kernel/smpboot.c | 3 +-- 4 files changed, 50 insertions(+), 21 deletions(-) diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 40bb1c15a731..c6acd44767c1 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -40,6 +40,17 @@ void arch_send_call_function_single_ipi(int cpu); int riscv_hartid_to_cpuid(int hartid); void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out); +struct riscv_ipi_ops { + void (*ipi_inject)(const struct cpumask *target); + void (*ipi_clear)(void); +}; + +/* Set custom IPI operations */ +void riscv_set_ipi_ops(struct riscv_ipi_ops *ops); + +/* Clear IPI for current CPU */ +void riscv_clear_ipi(void); + /* * Obtains the hart ID of the currently executing task. This relies on * THREAD_INFO_IN_TASK, but we define that unconditionally. diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index f383ef5672b2..226ccce0f9e0 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -547,6 +547,18 @@ static inline long sbi_get_firmware_version(void) return __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_VERSION); } +static void sbi_send_cpumask_ipi(const struct cpumask *target) +{ + struct cpumask hartid_mask; + + riscv_cpuid_to_hartid_mask(target, &hartid_mask); + + sbi_send_ipi(cpumask_bits(&hartid_mask)); +} + +static struct riscv_ipi_ops sbi_ipi_ops = { + .ipi_inject = sbi_send_cpumask_ipi +}; int __init sbi_init(void) { @@ -587,5 +599,7 @@ int __init sbi_init(void) __sbi_rfence = __sbi_rfence_v01; } + riscv_set_ipi_ops(&sbi_ipi_ops); + return 0; } diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index b1d4f452f843..8b85683ce203 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -84,9 +84,25 @@ static void ipi_stop(void) wait_for_interrupt(); } +static struct riscv_ipi_ops *ipi_ops; + +void riscv_set_ipi_ops(struct riscv_ipi_ops *ops) +{ + ipi_ops = ops; +} +EXPORT_SYMBOL_GPL(riscv_set_ipi_ops); + +void riscv_clear_ipi(void) +{ + if (ipi_ops && ipi_ops->ipi_clear) + ipi_ops->ipi_clear(); + + csr_clear(CSR_IP, IE_SIE); +} +EXPORT_SYMBOL_GPL(riscv_clear_ipi); + static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op) { - struct cpumask hartid_mask; int cpu; smp_mb__before_atomic(); @@ -94,33 +110,22 @@ static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op) set_bit(op, &ipi_data[cpu].bits); smp_mb__after_atomic(); - riscv_cpuid_to_hartid_mask(mask, &hartid_mask); - if (IS_ENABLED(CONFIG_RISCV_SBI)) - sbi_send_ipi(cpumask_bits(&hartid_mask)); + if (ipi_ops && ipi_ops->ipi_inject) + ipi_ops->ipi_inject(mask); else - clint_send_ipi_mask(mask); + pr_warn("SMP: IPI inject method not available\n"); } static void send_ipi_single(int cpu, enum ipi_message_type op) { - int hartid = cpuid_to_hartid_map(cpu); - smp_mb__before_atomic(); set_bit(op, &ipi_data[cpu].bits); smp_mb__after_atomic(); - if (IS_ENABLED(CONFIG_RISCV_SBI)) - sbi_send_ipi(cpumask_bits(cpumask_of(hartid))); - else - clint_send_ipi_single(hartid); -} - -static inline void clear_ipi(void) -{ - if (IS_ENABLED(CONFIG_RISCV_SBI)) - csr_clear(CSR_IP, IE_SIE); + if (ipi_ops && ipi_ops->ipi_inject) + ipi_ops->ipi_inject(cpumask_of(cpu)); else - clint_clear_ipi(cpuid_to_hartid_map(smp_processor_id())); + pr_warn("SMP: IPI inject method not available\n"); } void handle_IPI(struct pt_regs *regs) @@ -131,7 +136,7 @@ void handle_IPI(struct pt_regs *regs) irq_enter(); - clear_ipi(); + riscv_clear_ipi(); while (true) { unsigned long ops; diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 4e9922790f6e..5fe849791bf0 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -147,8 +147,7 @@ asmlinkage __visible void smp_callin(void) { struct mm_struct *mm = &init_mm; - if (!IS_ENABLED(CONFIG_RISCV_SBI)) - clint_clear_ipi(cpuid_to_hartid_map(smp_processor_id())); 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dkim=none (message not signed) header.d=none; dabbelt.com; dmarc=none action=none header.from=wdc.com; Received: from MN2PR04MB6207.namprd04.prod.outlook.com (2603:10b6:208:de::32) by MN2PR04MB5725.namprd04.prod.outlook.com (2603:10b6:208:a2::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3131.24; Sat, 27 Jun 2020 16:21:07 +0000 Received: from MN2PR04MB6207.namprd04.prod.outlook.com ([fe80::e0ef:7fce:ff0d:f580]) by MN2PR04MB6207.namprd04.prod.outlook.com ([fe80::e0ef:7fce:ff0d:f580%7]) with mapi id 15.20.3131.026; Sat, 27 Jun 2020 16:21:07 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Rob Herring , Daniel Lezcano , Thomas Gleixner Cc: Damien Le Moal , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v2 3/5] clocksource/drivers/timer-riscv: Remove MMIO related stuff Date: Sat, 27 Jun 2020 21:49:55 +0530 Message-Id: <20200627161957.134376-4-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200627161957.134376-1-anup.patel@wdc.com> References: <20200627161957.134376-1-anup.patel@wdc.com> X-ClientProxiedBy: MAXPR0101CA0029.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:d::15) To MN2PR04MB6207.namprd04.prod.outlook.com (2603:10b6:208:de::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (42.109.128.251) by MAXPR0101CA0029.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:d::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3131.21 via Frontend Transport; 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PTR:; CAT:NONE; SFTY:; SFS:(4636009)(39860400002)(136003)(346002)(376002)(396003)(366004)(1076003)(8886007)(186003)(16526019)(52116002)(86362001)(55016002)(1006002)(36756003)(7696005)(66946007)(5660300002)(83380400001)(26005)(66556008)(66476007)(110136005)(2616005)(4326008)(54906003)(478600001)(44832011)(8676002)(8936002)(2906002)(316002)(7416002)(956004); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: AM9EEtQIlCEs4sZVB2a1vSrnOYEzvvBXY+s/TMPn4M46IPlj5y3IfI+JiYBAD/lfsFV6u+xpCNoSWCW/QAjHjlEulFnJtzW8Z7uuFfplcg/wz3yTipbrLrNknoLpNVtvpfzcRakKkfYy8dVC9jfYk3V+Mal5FO5QvHO8wCiZqypsTIAQlbIeueV7NqMC/bKIyv964kSgCGBjmxUtRWmxfrX7TR18fdEVL3kf8UeHEidusiuxjyVi4HOs0TNdJwQdVk3tUUt8BxP0qxE6qeaTiVxpxZHUL5Zf/mZfizDBUHrYr9pJVwOs1Owh5uS7q6Vx/wGl6vibWdZxXi2riY3nubD3gyz3GFMP6mlxmFIjCqveQLqWhcybQxjGkAPpBdgyyF+hKyDY9GwBHRVtAXJsGRVaxpqHh+dMljK2iCaki+o5H32wEH+RVX+rek1coQhj6xoaXI2RMWL7m3oRvnC9yia9ocqkrLtXAtpFMHa23JA= X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9bdf45d5-1e4e-46a3-dad1-08d81ab61836 X-MS-Exchange-CrossTenant-AuthSource: MN2PR04MB6207.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2020 16:21:07.1080 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PNtdOg2aaAMmXrPgQl2TZqimtENARRoR0qOD60bS4rdYehovGKz3+/WhoC3w4YuD/QS6Enl0e2q3wo1GYTel2Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5725 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Right now the RISC-V timer is convoluted to support: 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for clocksource and SBI timer calls for clockevent device. 2. Linux RISC-V M-mode (without MMU) where it will use CLINT MMIO counter register for clocksource and CLINT MMIO compare register for clockevent device. This patch removes MMIO related stuff from RISC-V timer driver so that we can have a separate CLINT timer driver. Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 2 +- arch/riscv/include/asm/timex.h | 28 +++++++--------------------- drivers/clocksource/Kconfig | 2 +- drivers/clocksource/timer-riscv.c | 17 ++--------------- 4 files changed, 11 insertions(+), 38 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 448a9952aa2f..868bbc4d0803 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -72,7 +72,7 @@ config RISCV select PCI_DOMAINS_GENERIC if PCI select PCI_MSI if PCI select RISCV_INTC - select RISCV_TIMER + select RISCV_TIMER if RISCV_SBI select SPARSEMEM_STATIC if 32BIT select SPARSE_IRQ select SYSCTL_EXCEPTION_TRACE diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h index bad2a7c2cda5..a3fb85d505d4 100644 --- a/arch/riscv/include/asm/timex.h +++ b/arch/riscv/include/asm/timex.h @@ -7,41 +7,27 @@ #define _ASM_RISCV_TIMEX_H #include -#include typedef unsigned long cycles_t; -extern u64 __iomem *riscv_time_val; -extern u64 __iomem *riscv_time_cmp; - -#ifdef CONFIG_64BIT -#define mmio_get_cycles() readq_relaxed(riscv_time_val) -#else -#define mmio_get_cycles() readl_relaxed(riscv_time_val) -#define mmio_get_cycles_hi() readl_relaxed(((u32 *)riscv_time_val) + 1) -#endif - static inline cycles_t get_cycles(void) { - if (IS_ENABLED(CONFIG_RISCV_SBI)) - return csr_read(CSR_TIME); - return mmio_get_cycles(); + return csr_read(CSR_TIME); } #define get_cycles get_cycles +static inline u32 get_cycles_hi(void) +{ + return csr_read(CSR_TIMEH); +} +#define get_cycles_hi get_cycles_hi + #ifdef CONFIG_64BIT static inline u64 get_cycles64(void) { return get_cycles(); } #else /* CONFIG_64BIT */ -static inline u32 get_cycles_hi(void) -{ - if (IS_ENABLED(CONFIG_RISCV_SBI)) - return csr_read(CSR_TIMEH); - return mmio_get_cycles_hi(); -} - static inline u64 get_cycles64(void) { u32 hi, lo; diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 91418381fcd4..8c6a0f1274af 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -649,7 +649,7 @@ config ATCPIT100_TIMER config RISCV_TIMER bool "Timer for the RISC-V platform" - depends on GENERIC_SCHED_CLOCK && RISCV + depends on GENERIC_SCHED_CLOCK && RISCV_SBI default y select TIMER_PROBE select TIMER_OF diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 9de1dabfb126..c51c5ed15aa7 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -19,26 +19,13 @@ #include #include #include - -u64 __iomem *riscv_time_cmp; -u64 __iomem *riscv_time_val; - -static inline void mmio_set_timer(u64 val) -{ - void __iomem *r; - - r = riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id()); - writeq_relaxed(val, r); -} +#include static int riscv_clock_next_event(unsigned long delta, struct clock_event_device *ce) { csr_set(CSR_IE, IE_TIE); - if (IS_ENABLED(CONFIG_RISCV_SBI)) - sbi_set_timer(get_cycles64() + delta); - else - mmio_set_timer(get_cycles64() + delta); + sbi_set_timer(get_cycles64() + delta); return 0; } From patchwork Sat Jun 27 16:19:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 198414 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE58FC433E2 for ; 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Sat, 27 Jun 2020 16:21:27 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Rob Herring , Daniel Lezcano , Thomas Gleixner Cc: Damien Le Moal , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel , Palmer Dabbelt Subject: [PATCH v2 5/5] dt-bindings: timer: Add CLINT bindings Date: Sat, 27 Jun 2020 21:49:57 +0530 Message-Id: <20200627161957.134376-6-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200627161957.134376-1-anup.patel@wdc.com> References: <20200627161957.134376-1-anup.patel@wdc.com> X-ClientProxiedBy: MAXPR0101CA0029.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:d::15) To MN2PR04MB6207.namprd04.prod.outlook.com (2603:10b6:208:de::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (42.109.128.251) by MAXPR0101CA0029.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:d::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3131.21 via Frontend Transport; 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PTR:; CAT:NONE; SFTY:; SFS:(4636009)(39860400002)(136003)(346002)(376002)(396003)(366004)(1076003)(8886007)(186003)(16526019)(52116002)(86362001)(55016002)(6666004)(1006002)(36756003)(7696005)(66946007)(5660300002)(83380400001)(26005)(66556008)(66476007)(110136005)(2616005)(4326008)(54906003)(478600001)(44832011)(8676002)(8936002)(2906002)(316002)(7416002)(956004); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: ClsdVQeWFQiIoND4lcyRS9EIYo5UmBPICf/63C/6SFzwC0E36X91GGQEl0bjIGKPh1SWs4MslYv5vzec/eO5RN5E5znHmQZ0UvrMUdqlSA/bZhmw4tbmVda48bFEB+uUcTo4/8Mr0RSUvxLYy3xeUudDUFS07gxcHFd0zdetMUQVZH2+wzGwWpV4tp2WpmON2mT2f87jr8dSrfu3lfuXEYJJnPYEqyRWQig7mj+MWDBV8M1QRidDH+SyQUsjb+yTBLJ1PL1lVlju3HaZfFgnJ67dKiD/9i+0IHd5Xy54mb5LZutO2IIS26mexWrENedPN675OoujuFJdxXzUpjk5fUYeOWya02Y4qxY9R+TEv237i8KggFTig97zntESsPd2plMqoz6/2pZBgBm8t+V/2GNwVLJ9JbJ43DrIf97yAFf1l0H/Sn2+uS/R+LgL0jIhPBxewS+kvcHy5MA3EJVxGy3XtPlGC0c7yw9Sye3Ouyg= X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: f83c4ecf-4e6a-423e-d426-08d81ab62416 X-MS-Exchange-CrossTenant-AuthSource: MN2PR04MB6207.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2020 16:21:27.0278 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: JxGFtxbzZE6AvUivVmXLer1/+EvNmAHvh6NMxFVVK3DYLWMjluZA3l65fkFimV1TwchYRyoQ6Coo1fwPkDDVLg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5725 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We add DT bindings documentation for CLINT device. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt --- .../bindings/timer/sifive,clint.txt | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt new file mode 100644 index 000000000000..45b75347a7d5 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt @@ -0,0 +1,34 @@ +SiFive Core Local Interruptor (CLINT) +------------------------------------- + +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts. + +It directly connects to the timer and inter-processor interrupt lines of +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt +controller is the parent interrupt controller for CLINT device. + +The clock frequency of CLINT is specified via "timebase-frequency" DT +property of "/cpus" DT node. The "timebase-frequency" DT property is +described in: Documentation/devicetree/bindings/riscv/cpus.yaml + +Required properties: +- compatible : should be "riscv,clint0" or "sifive,clint-1.0.0". A specific + string identifying the actual implementation can be added if implementation + specific worked arounds are needed. +- reg : Should contain 1 register range (address and length). +- interrupts-extended : Specifies which HARTs (or CPUs) are connected to + the CLINT. Each node pointed to should be a riscv,cpu-intc node, which + has a riscv node as parent. + +Example: + + clint@2000000 { + compatible = "sifive,clint-1.0.0", "sifive,fu540-c000-clint"; + interrupts-extended = < + &cpu1-intc 3 &cpu1-intc 7 + &cpu2-intc 3 &cpu2-intc 7 + &cpu3-intc 3 &cpu3-intc 7 + &cpu4-intc 3 &cpu4-intc 7>; + reg = <0x2000000 0x4000000>; + };