From patchwork Mon Aug 7 16:01:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 109578 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1785708qge; Mon, 7 Aug 2017 09:03:06 -0700 (PDT) X-Received: by 10.99.7.131 with SMTP id 125mr990635pgh.136.1502121786175; Mon, 07 Aug 2017 09:03:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502121786; cv=none; d=google.com; s=arc-20160816; b=ggrGp380pXeMsb7htKqqFKvSqbb7auJ7/Z14HTby0ZuVtp6KnmEhbBTPXtP4BZHEgy kIaRk/uQIX9/Wpjtc5LMlwXbLHgtnlLq6QG0UsxUY7Lnrx5XmhJYdmMH/AGTcvIRdSQC 7xCv/wCeOLgPGWJyvgivoYLdSv2rTxRTWumpv5BwV8LdlivvtBoqwzaVapAFPiBDbQBt pGHRcjv8MzDoPOZV0pe4DuR3rVZyPROzkJb8xsGD/YGihx6iCCLwEZfan9k9+s7Ub1X4 JLVHBVxeBlrvnzFlXbjhUQcnXnOj66roE0nz9yE/I5WTUVTTRRxifyBtzycFoo/zwQlW 3Qow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=GuVYnq4rGnI9XTAbDLLM+5PJRJjrHxVP5so1BuhG/dk=; b=iFxZ8M63oNNCkh30+utUasedVFPlMq3RkLgq5UfbgQ4n5r3hXVLsw6V2sobhB6v/Zi Nop3U4zWBCpT1vvs00zXzJ54E1WJC+nule1DB7e8HxTdkMBuhAdws9w1tgs+RAmb+h98 eE2akUL6LiXGbi0TUWOlpPPumdGAQzLG8lIKCTCCgtz5/ed2a4Qwc+qrPhRQsdtkdRRz /nTaeWcWuj4r24Ibq8E6KbDce9u+7fzBTynWJeKptSchWO+VE630Ygs6inZo4RtWSnEg D2cNO5ieq9lwDLbn28ZGv/70ORdosO9RoQYNN1FVhsU847R2caZwDcy1w7a1bAF42gD4 6iuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.b=duwUxG86; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v18si1214608pgb.915.2017.08.07.09.03.05; Mon, 07 Aug 2017 09:03:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.b=duwUxG86; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752121AbdHGQDD (ORCPT + 25 others); Mon, 7 Aug 2017 12:03:03 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:38812 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752069AbdHGQCw (ORCPT ); Mon, 7 Aug 2017 12:02:52 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v77G1vMd015879; Mon, 7 Aug 2017 11:01:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1502121717; bh=Ki6+FdRFUvsHMF2Sax6Qb3mgULuQYPqhD/epVjM51lo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=duwUxG86B3d3YHc7/Kzlm475rmzz5GOcclZE7obtvzF/wqDGjUbwsSyMM3iZ8xZ6W W9IEG2QYp2lVcgLObVPLdilVDWTlED2M4vFPswyhSpwaqn+SPxNcFr9cWQCuh5RhX2 +gSu+BcNZOSTlKdTHvBKLojCGKuofQpcGO831yRE= Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v77G1qBg030291; Mon, 7 Aug 2017 11:01:52 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Mon, 7 Aug 2017 11:01:52 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v77G1jGr023497; Mon, 7 Aug 2017 11:01:49 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Tony Lindgren , Rob Herring , Adrian Hunter CC: , , , , , Subject: [RFC PATCH 1/7] mmc: sdhci: Add quirk to indicate no CRC stripping in MMC_RSP_136 Date: Mon, 7 Aug 2017 21:31:36 +0530 Message-ID: <20170807160142.12134-2-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170807160142.12134-1-kishon@ti.com> References: <20170807160142.12134-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org TI's implementation of sdhci controller used in DRA7 SoC's doesn't strip CRC in responses with length 136 bits. Add quirk to indicate the controller does not strip CRC in MMC_RSP_136. If this quirk is set sdhci library shouldn't shift the response present in SDHCI_RESPONSE register. Signed-off-by: Kishon Vijay Abraham I --- drivers/mmc/host/sdhci.c | 27 +++++++++++++++++++-------- drivers/mmc/host/sdhci.h | 2 ++ 2 files changed, 21 insertions(+), 8 deletions(-) -- 2.11.0 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index ecd0d4350e8a..ece3751d2a25 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1182,14 +1182,25 @@ static void sdhci_finish_command(struct sdhci_host *host) if (cmd->flags & MMC_RSP_PRESENT) { if (cmd->flags & MMC_RSP_136) { - /* CRC is stripped so we need to do some shifting. */ - for (i = 0;i < 4;i++) { - cmd->resp[i] = sdhci_readl(host, - SDHCI_RESPONSE + (3-i)*4) << 8; - if (i != 3) - cmd->resp[i] |= - sdhci_readb(host, - SDHCI_RESPONSE + (3-i)*4-1); + if (!(host->quirks2 & SDHCI_QUIRK2_NO_CRC_STRIPPING)) { + /* + * CRC is stripped so we need to do some + * shifting. + */ + for (i = 0; i < 4; i++) { + cmd->resp[i] = + sdhci_readl(host, SDHCI_RESPONSE + + (3 - i) * 4) << 8; + if (i != 3) + cmd->resp[i] |= + sdhci_readb(host, SDHCI_RESPONSE + + (3 - i) * 4 - 1); + } + } else { + for (i = 0; i < 4; i++) + cmd->resp[i] = + sdhci_readl(host, SDHCI_RESPONSE + + (3 - i) * 4); } } else { cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 0469fa191493..6905131f603d 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -435,6 +435,8 @@ struct sdhci_host { #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) /* Broken Clock divider zero in controller */ #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) +/* Controller does not have CRC stripped in Command Response */ +#define SDHCI_QUIRK2_NO_CRC_STRIPPING (1<<16) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ From patchwork Mon Aug 7 16:01:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 109574 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1784198qge; Mon, 7 Aug 2017 09:02:06 -0700 (PDT) X-Received: by 10.99.163.1 with SMTP id s1mr991027pge.416.1502121726243; Mon, 07 Aug 2017 09:02:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502121726; cv=none; d=google.com; s=arc-20160816; b=rF5cu/AoAmK5m6jjJvt7gH2+OHYZ1L2SC0vCCIz043FIQ+lMuXmmo4oCt2iO8qbQd5 0NVq4KWnctxg5nOgJjjRKtEgwAveqhsDA3TK/M4UJCRBeMYkmtAM/N5fdch8AFSkhGbX +2mgfya584iviQYXluVzsesbg7k/MTvY2m4s8GJ32cCbTN2f5GV9aZSZ4X8kQADySF1M 8DjvGup7JWK9/7y2jJFSRzrxRIa3JWKfqj0aialwdu+5wcuyxzV34V7LfFVtcWF10i6P XB2TtLiFZ6hDOJ5+7ehziqjKau2lo9rwsa0yaA/bWSHWUxu6hISkfl8L0SO/xkErh4Nj C7fw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=BGvAuu5ggaLQZhwF3/9DS/Gxm4SDxuMLyEKct+ehPOg=; b=sJhdMfl9V76D8MDNwqvx/MtW2aO3Yv9JPJyWvC3zLF7eQVXNsHBOWRsQjSc6ohhxjE FZkKQI+qHRmE9DrXDSTZt8L0jwsXI5GPYJzcOX1ZLKQyVbxv3Z5eBsnSOgrCwznQ3O2c qeCttKlD7cipt1plAlxt/BU3AHHhKMa6PvtqVxDHodV+4ZL7ICKly8yQDpTQx36lWTuM a9x41ISdqsxPNywv0KSCGA6E5qbaFXeY1LxBG6QYg0tawgTEc+6UuL3R7+oHwcJs8mVK eWThyDS3NFxZz1D1ENkHskbJvF/il/KCVLVAURx19u3hzUzEwG3fr4YitHEV0wFPeAcF 22Lg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.b=j8dnsDLH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l91si5600307plb.246.2017.08.07.09.02.05; Mon, 07 Aug 2017 09:02:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.b=j8dnsDLH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751962AbdHGQCE (ORCPT + 25 others); Mon, 7 Aug 2017 12:02:04 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:16498 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751904AbdHGQCB (ORCPT ); Mon, 7 Aug 2017 12:02:01 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v77G1uE6016524; Mon, 7 Aug 2017 11:01:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1502121716; bh=KlQ2DkNZuLGF3ZZozeLFRY2s2NP24+Z+pQkBe64fzJY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=j8dnsDLHC1adByzgisLcYWwivKAgmoKc7tXJDXo6/wgrbldSIzNKDL9eAfxDERZ+J jUkPQIkNDY8JsUUSEfJXF0kBztJ0/u5Kc8ZT6B7KswvCcGnf6tLHYPiRs9rnWJYcEa 37IYgxSf682tVjpEkZYWYXn3TvOqgyxVbHTOSX5M= Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v77G1uB3007450; Mon, 7 Aug 2017 11:01:56 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Mon, 7 Aug 2017 11:01:55 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v77G1jGs023497; Mon, 7 Aug 2017 11:01:53 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Tony Lindgren , Rob Herring , Adrian Hunter CC: , , , , , Subject: [RFC PATCH 2/7] mmc: sdhci: Add quirk to indicate controller supports ADMA2 Date: Mon, 7 Aug 2017 21:31:37 +0530 Message-ID: <20170807160142.12134-3-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170807160142.12134-1-kishon@ti.com> References: <20170807160142.12134-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org TI's implementation of sdhci controller used in DRA7 SoC's doesn't have SDHCI_CAN_DO_ADMA2 set in CAPA register though it supports ADMA2. Add quirk to support using ADMA2 even if the controller reports incorrect capability in CAPA. Signed-off-by: Kishon Vijay Abraham I --- drivers/mmc/host/sdhci.c | 3 ++- drivers/mmc/host/sdhci.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) -- 2.11.0 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index ece3751d2a25..fff0baadbc3e 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3264,7 +3264,8 @@ int sdhci_setup_host(struct sdhci_host *host) } if ((host->version >= SDHCI_SPEC_200) && - (host->caps & SDHCI_CAN_DO_ADMA2)) + ((host->caps & SDHCI_CAN_DO_ADMA2) || + (host->quirks2 & SDHCI_QUIRK2_FORCE_ADMA))) host->flags |= SDHCI_USE_ADMA; if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 6905131f603d..d778034e324d 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -437,6 +437,8 @@ struct sdhci_host { #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) /* Controller does not have CRC stripped in Command Response */ #define SDHCI_QUIRK2_NO_CRC_STRIPPING (1<<16) +/* Controller has bad caps bits, but really supports DMA */ +#define SDHCI_QUIRK2_FORCE_ADMA (1<<17) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ From patchwork Mon Aug 7 16:01:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 109576 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1785222qge; Mon, 7 Aug 2017 09:02:45 -0700 (PDT) X-Received: by 10.84.174.4 with SMTP id q4mr1143743plb.235.1502121765156; Mon, 07 Aug 2017 09:02:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502121765; cv=none; d=google.com; s=arc-20160816; b=gcQZuUOV+Wg/g1MuWLXW+CqWl0yFgzojlYd6HCQGk9K+oCvLyGy4y7xRJyU1PNavHL wwY/GHzXpmBVxNUmNBW8cPvoamoju4Q104V7bwhFhkSeBjonHousz1KzRcst+qDcB5oE 2I/jBQqp6Q6DFQmOatl7e+DKtjoPI37RtSXMmy570OU89vD/iQK6ZnOU2nK4izqzZgHu 6uN64BIZTyjzzqLQ5LUvoaYDLpL1UdvFDFq/o4flBMC8nEHD5fvqVhiSnbzefhEIteLe v93nZ1UAH9K7DqnY2k/AptmQoBCWiDJ1jErB0LPILYYugXPonjKogDf5wGng+6YGNqYf 40WA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=0SwCmT7BoBvCVRAmrfEF7afd7A/CXllcr7feGZe1fsc=; b=qc6XuYvbXy/r73j9l6Y1s1KND1lRpO1j/rbYYgSuxfDPpbU3qCz9dtpf3LSt0nlmY2 x/DA4uSGku1i6uQl6lD4FDoVKOiEEjg29iSuunGaOxl+Zph6HVqoreXfTxIfDO1pVig4 5VAdFpqBWGRTBl3tAJbFygd5dRNc2gRZwldA2otcSUeX7oOreH9w7nThfakfCc8Xttl2 j7m1hD+yeUfQsNffAajA4RD0HxkXhdZd9wi8WhYQnxEu0tk4XBRjV/UwXptbQf3TNtDl YYXcwy+WAIsC/6b9+k5s5heqw0Hcb4ND50crAWwRjZjjYJpMr2Xj3VLgzEMl2sGLoTLq B2jg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.b=c3HXkh9u; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v18si1214608pgb.915.2017.08.07.09.02.44; Mon, 07 Aug 2017 09:02:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.b=c3HXkh9u; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752068AbdHGQCl (ORCPT + 25 others); Mon, 7 Aug 2017 12:02:41 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:35266 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751963AbdHGQCJ (ORCPT ); Mon, 7 Aug 2017 12:02:09 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v77G22o7009568; Mon, 7 Aug 2017 11:02:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1502121722; bh=L5FSFKrwAYT7d2ae0ppgomEXxAYtrhKP27vRgFsZ4JI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=c3HXkh9uStR1aeeYuFsJqmPMmJo5II5Dcu/19Zb1/nzHG0814yYxbGeKq3rYA3txZ xcBc3dT/HPk2VrFIXww8hsYXwnlRSs8hdh91s1/RihLVHDzrOK3gAx5MHiaDyB9Abo KQspUlKAYM29VpUV1Vmyy2iTG7T/00iKV7wZFr0c= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v77G21kq030538; Mon, 7 Aug 2017 11:02:02 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Mon, 7 Aug 2017 11:02:02 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v77G1jGu023497; Mon, 7 Aug 2017 11:01:59 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Tony Lindgren , Rob Herring , Adrian Hunter CC: , , , , , Subject: [RFC PATCH 4/7] mmc: sdhci: Add quirk to indicate broken POWER_CONTROL Date: Mon, 7 Aug 2017 21:31:39 +0530 Message-ID: <20170807160142.12134-5-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170807160142.12134-1-kishon@ti.com> References: <20170807160142.12134-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org TI's implementation of sdhci controller used in DRA7 SoC's uses POWER_CONTROL register for configuring IO voltage and not for core voltage (vdd) which is it's intended use. Add a quirk to indicate broken POWER_CONTROL register. Signed-off-by: Kishon Vijay Abraham I --- drivers/mmc/host/sdhci.c | 6 ++++++ drivers/mmc/host/sdhci.h | 2 ++ 2 files changed, 8 insertions(+) -- 2.11.0 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index d5050ec42481..a7465a56e6b5 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1419,6 +1419,9 @@ static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode, mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); + if (host->quirks2 & SDHCI_QUIRK2_BROKEN_POWER_CONTROL) + return; + if (mode != MMC_POWER_OFF) sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL); else @@ -1430,6 +1433,9 @@ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, { u8 pwr = 0; + if (host->quirks2 & SDHCI_QUIRK2_BROKEN_POWER_CONTROL) + return; + if (mode != MMC_POWER_OFF) { switch (1 << vdd) { case MMC_VDD_165_195: diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 39c7a2723906..ba94cca7c892 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -439,6 +439,8 @@ struct sdhci_host { #define SDHCI_QUIRK2_NO_CRC_STRIPPING (1<<16) /* Controller has bad caps bits, but really supports DMA */ #define SDHCI_QUIRK2_FORCE_ADMA (1<<17) +/* Controller uses POWER_CONTROL for managing IO voltage and not core voltage */ +#define SDHCI_QUIRK2_BROKEN_POWER_CONTROL (1<<18) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ From patchwork Mon Aug 7 16:01:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 109575 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1784395qge; Mon, 7 Aug 2017 09:02:14 -0700 (PDT) X-Received: by 10.98.7.132 with SMTP id 4mr1108393pfh.216.1502121734056; Mon, 07 Aug 2017 09:02:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502121734; cv=none; d=google.com; s=arc-20160816; b=bvZYoM18nCWUOj4SVh4x2uES5qlqKu3V5KamDYgpT1y0jBLAL/o26+mr6Z6d7EPHPR AZ0F/lE25BGugUNuAe5m0Z9V9xbZWlvtaav6VrQz6J/gss3oWR9Wsi55vlcppjheBMCz rrDY4Il6V95TIabjjZnIBpUTQbvbxlmT1C/kv8oGjziYNivmdXMrPRQM28iAHbLNfnXe w1TDkgMm7p8lPavPkzD4uOPp9hRC3V6t4nz957DUbtlswclK+qNU02DXyY2RF9p26J5u AO5IyTAlss3jW4X2KkKnGjxTtCv0mGUK8ahCcJnuYErLN1TEO3SCnVsAstZcqPwkvNgr B2fA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=/pU/AbKIUt3pHGtVZo0HSX9Zz/u5oYk6SMp1ArJ9f4s=; b=t0sU9NieDhqiGssbXbSOqJAw6PA6/gDdYJ7xHNDM3VEdHT8Ij4jc7RyBwPqLEKvNca emvVK/tW+fuh4wwtfE0CetFbzCieOzilnspuZ/elCDrX5/ZUkoPAeEc6SC/brxpRHrAX KVypFjMu3v+MxEI4a3I8AgRFuvYc8txUHwZ/ipLZNNgvBtsvH6/NF3Sq1E//guEJeoYr QR21QxCfON+U3VLtK6GfWDVzEUerbz5QH0S6vfqtZ3+LuCf6s4vndK9M9t5uvVpLdH6F PGS6S5pHWfdgnLZezqC8VTfwww9/fIOiLJm687ARdFskOZPngsJiuVkSXqMuey7QhgXp JaDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.b=LJ9Qz/Nb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h7si5574461pln.778.2017.08.07.09.02.13; Mon, 07 Aug 2017 09:02:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.b=LJ9Qz/Nb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751996AbdHGQCL (ORCPT + 25 others); Mon, 7 Aug 2017 12:02:11 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:16520 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751904AbdHGQCJ (ORCPT ); Mon, 7 Aug 2017 12:02:09 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v77G259q016560; Mon, 7 Aug 2017 11:02:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1502121725; bh=mxaZ9ikuDsfB2ktYyZolurU5DPpXXN0rCEa6H1NineM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LJ9Qz/Nbe8aVawOtlW4wZq7BTwhd2Y4k+yVo3qs8zSWt4/p7sOrDeA2r0eZZn/cSa 1EHCE/5lNmEN4D3qRd5E3A1QTMfztTQcXpMH19sAewsUX9DJvAFVFvPMW7LaWc4SFH b7JsEJlbvc0gW90N8tyWqSP/ffZ/lY/YlSJgoIQM= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v77G25uD030927; Mon, 7 Aug 2017 11:02:05 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Mon, 7 Aug 2017 11:02:04 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v77G1jGv023497; Mon, 7 Aug 2017 11:02:02 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Tony Lindgren , Rob Herring , Adrian Hunter CC: , , , , , Subject: [RFC PATCH 5/7] dt-bindings: ti-omap-hsmmc: Document new compatible for sdhci omap Date: Mon, 7 Aug 2017 21:31:40 +0530 Message-ID: <20170807160142.12134-6-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170807160142.12134-1-kishon@ti.com> References: <20170807160142.12134-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the new compatible string "ti,dra7-sdhci" to be used for MMC controllers in DRA7 and DRA72 SoCs. Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt | 1 + 1 file changed, 1 insertion(+) -- 2.11.0 diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt index 0e026c151c1c..db80fdfd05d7 100644 --- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt @@ -13,6 +13,7 @@ Required properties: Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0 Should be "ti,omap4-hsmmc", for OMAP4 controllers Should be "ti,am33xx-hsmmc", for AM335x controllers + Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers - ti,hwmods: Must be "mmc", n is controller instance starting 1 Optional properties: From patchwork Mon Aug 7 16:01:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 109579 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1785942qge; Mon, 7 Aug 2017 09:03:14 -0700 (PDT) X-Received: by 10.98.213.196 with SMTP id d187mr1101451pfg.146.1502121793917; Mon, 07 Aug 2017 09:03:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502121793; cv=none; d=google.com; s=arc-20160816; b=vQptff5OLG37KgCvuNfc8RP4rvbk/ZhdMSDYr+jaR3SmeGtf3up6nqd4TaS+RxVy52 6NpO1Iub056hDmBMdA5BDC0DSLu8+b+XwQGe3Iofligik6EF5O3ki9YtVcXG2EruQeuy oSjsYJKx1rUV9CCuYwYU9M+CTtreon0rg9XBf4ZcmxgO8kmjXA8L/v+m9NfHmPYwNjD9 4BrVfAW2e5LlVXcyj1m/arlwX1r1On/kZHfq96SkQ6jWGelEG3qFuSy71pZ1XfXloHoF FhSpbdWuFmMpR9fl98AiWuGn/y0MeVXuAW9rEYJ7puEJZkIgv6wM+gGqeU45WT5e+YqD r55A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=opEJgx+lnYBo9lPKgsJrrXLlEIWNdg6hptiwji+fnoI=; b=FvsnJmkYsfFzdHBzB6VpEH4N/6UF6feX/WXye2LH5yKXqsXgslzqKEy0EKmIzF6oPI 2E9Dqnq1/V1ZaC1Y2DpkQKLnNfWUI26eRDz6U3FklLi4mR+7fvfJK5c5qbAbPThQfV9p 8psBWIjC7vNHwsD35CfXCGoCffD4EoUabbj2EbxGPHYXJH0ngQ6Wa2+pbPeU7HsFvqLC gikTY+OkS9FVE+dWL9e3q4Q6pn44UmBjBpNdsWgarkZNmq8l70jXJDpBimaILSAjAIWZ i8GtfYYAnbOYmX0fRMEMKX0ELFpDx+WLA0AZOCcnG69TG7/qFMq9CXObPRb1heeSYxVu G14A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.b=tTiocUyV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v18si1214608pgb.915.2017.08.07.09.03.13; Mon, 07 Aug 2017 09:03:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.b=tTiocUyV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752152AbdHGQDL (ORCPT + 25 others); Mon, 7 Aug 2017 12:03:11 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:38825 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752069AbdHGQDJ (ORCPT ); Mon, 7 Aug 2017 12:03:09 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v77G2EN8015906; Mon, 7 Aug 2017 11:02:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1502121734; bh=RPBi5XzsHkRzbnph6mXrWzu8vn92gQxPmsvDzfO7foc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tTiocUyVWumt3xMSUlKI7OZtT4P69bjVaG/tSp0/mbO6BD5DV9+5LvPbAzH5nB1lW oXeGnFnQzN/QwhI7i0rgItlHD9jbMYaVcCgFbzNj2agUfb1qlx/ejKZsircqL37d3f 9iwnxOLaHmlpU9Bcc8NTTQbA5250M9wfeiTvEnLY= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v77G2821008023; Mon, 7 Aug 2017 11:02:08 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Mon, 7 Aug 2017 11:02:08 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v77G1jGw023497; Mon, 7 Aug 2017 11:02:05 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Tony Lindgren , Rob Herring , Adrian Hunter CC: , , , , , Subject: [RFC PATCH 6/7] mmc: sdhci-omap: Add OMAP SDHCI driver Date: Mon, 7 Aug 2017 21:31:41 +0530 Message-ID: <20170807160142.12134-7-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170807160142.12134-1-kishon@ti.com> References: <20170807160142.12134-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Create a new sdhci-omap driver to configure the eMMC/SD/SDIO controller in TI's OMAP SoCs making use of the SDHCI core library. For OMAP specific configurations, populate sdhci_ops with OMAP specific callbacks and use SDHCI quirks. Enable only high speed mode for both SD and eMMC here and add other UHS mode support later. Signed-off-by: Kishon Vijay Abraham I --- drivers/mmc/host/Kconfig | 12 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-omap.c | 593 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 606 insertions(+) create mode 100644 drivers/mmc/host/sdhci-omap.c -- 2.11.0 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 5755b69f2f72..9aa7e5ce43ba 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -871,3 +871,15 @@ config MMC_SDHCI_XENON This selects Marvell Xenon eMMC/SD/SDIO SDHCI. If you have a controller with this interface, say Y or M here. If unsure, say N. + +config MMC_SDHCI_OMAP + tristate "TI SDHCI Controller Support" + depends on MMC_SDHCI_PLTFM + help + This selects the Secure Digital Host Controller Interface (SDHCI) + support present in TI's DRA7 SOCs. The controller supports + SD/MMC/SDIO devices. + + If you have a controller with this interface, say Y or M here. + + If unsure, say N. diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 4d4547116311..30fb8b0fd0e1 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -82,6 +82,7 @@ obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o obj-$(CONFIG_MMC_SDHCI_ST) += sdhci-st.o obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32) += sdhci-pic32.o obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o +obj-$(CONFIG_MMC_SDHCI_OMAP) += sdhci-omap.o ifeq ($(CONFIG_CB710_DEBUG),y) CFLAGS-cb710-mmc += -DDEBUG diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c new file mode 100644 index 000000000000..c067c428a0cd --- /dev/null +++ b/drivers/mmc/host/sdhci-omap.c @@ -0,0 +1,593 @@ +/* + * SDHCI Controller driver for TI's OMAP SoCs + * + * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com + * + * Authors: Kishon Vijay Abraham I + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sdhci-pltfm.h" + +#define SDHCI_OMAP_CON 0x12c +#define CON_DW8 BIT(5) +#define CON_DMA_MASTER BIT(20) +#define CON_INIT BIT(1) +#define CON_OD BIT(0) + +#define SDHCI_OMAP_CMD 0x20c + +#define SDHCI_OMAP_HCTL 0x228 +#define HCTL_SDBP BIT(8) +#define HCTL_SDVS_SHIFT 9 +#define HCTL_SDVS_MASK (0x7 << HCTL_SDVS_SHIFT) +#define HCTL_SDVS_33 (0x7 << HCTL_SDVS_SHIFT) +#define HCTL_SDVS_30 (0x6 << HCTL_SDVS_SHIFT) +#define HCTL_SDVS_18 (0x5 << HCTL_SDVS_SHIFT) + +#define SDHCI_OMAP_SYSCTL 0x22c +#define SYSCTL_CEN BIT(2) +#define SYSCTL_CLKD_SHIFT 6 +#define SYSCTL_CLKD_MASK 0x3ff + +#define SDHCI_OMAP_STAT 0x230 + +#define SDHCI_OMAP_IE 0x234 +#define INT_CC_EN BIT(0) + +#define SDHCI_OMAP_AC12 0x23c +#define AC12_V1V8_SIGEN BIT(19) + +#define SDHCI_OMAP_CAPA 0x240 +#define CAPA_VS33 BIT(24) +#define CAPA_VS30 BIT(25) +#define CAPA_VS18 BIT(26) + +#define MMC_TIMEOUT 1 /* 1 msec */ + +#define SYSCTL_CLKD_MAX 0x3FF + +#define IOV_1V8 1800000 /* 180000 uV */ +#define IOV_3V0 3000000 /* 300000 uV */ +#define IOV_3V3 3300000 /* 330000 uV */ + +struct sdhci_omap_data { + u32 offset; +}; + +struct sdhci_omap_host { + void __iomem *base; + struct device *dev; + struct regulator *pbias; + bool pbias_enabled; + struct sdhci_host *host; + unsigned int flags; + +#define SDHCI_OMAP_SUPPORTS_DUAL_VOLT BIT(0) +#define SDHCI_OMAP_NO_1_8_V BIT(1) + + u8 power_mode; + bool io_3_3v_support; +}; + +static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host, + unsigned int offset) +{ + return readl(host->base + offset); +} + +static inline void sdhci_omap_writel(struct sdhci_omap_host *host, + unsigned int offset, u32 data) +{ + writel(data, host->base + offset); +} + +static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host, + bool power_on, unsigned int iov) +{ + int ret; + struct device *dev = omap_host->dev; + + if (IS_ERR(omap_host->pbias)) + return 0; + + if (power_on) { + ret = regulator_set_voltage(omap_host->pbias, iov, iov); + if (ret) { + dev_err(dev, "pbias set voltage failed\n"); + return ret; + } + + if (omap_host->pbias_enabled) + return 0; + + ret = regulator_enable(omap_host->pbias); + if (ret) { + dev_err(dev, "pbias reg enable fail\n"); + return ret; + } + + omap_host->pbias_enabled = true; + } else { + if (!omap_host->pbias_enabled) + return 0; + + ret = regulator_disable(omap_host->pbias); + if (ret) { + dev_err(dev, "pbias reg disable fail\n"); + return ret; + } + omap_host->pbias_enabled = false; + } + + return 0; +} + +static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host, + unsigned int iov) +{ + int ret; + struct sdhci_host *host = omap_host->host; + struct mmc_host *mmc = host->mmc; + + ret = sdhci_omap_set_pbias(omap_host, false, 0); + if (ret) + return ret; + + if (!IS_ERR(mmc->supply.vqmmc)) { + ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov); + if (ret) { + dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n"); + return ret; + } + } + + ret = sdhci_omap_set_pbias(omap_host, true, iov); + if (ret) + return ret; + + return 0; +} + +static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host, + unsigned char signal_voltage) +{ + u32 reg; + ktime_t timeout; + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL); + reg &= ~HCTL_SDVS_MASK; + + if (signal_voltage == MMC_SIGNAL_VOLTAGE_180) + reg |= HCTL_SDVS_18; + else if (omap_host->io_3_3v_support) + reg |= HCTL_SDVS_33; + else + reg |= HCTL_SDVS_30; + + sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg); + + reg |= HCTL_SDBP; + sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg); + + /* wait 1ms */ + timeout = ktime_add_ms(ktime_get(), MMC_TIMEOUT); + while (!(sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)) { + if (WARN_ON(ktime_after(ktime_get(), timeout))) + return; + usleep_range(5, 10); + } +} + +static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + u32 reg; + int ret; + unsigned int iov; + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host; + struct sdhci_omap_host *omap_host; + struct device *dev; + + pltfm_host = sdhci_priv(host); + omap_host = sdhci_pltfm_priv(pltfm_host); + dev = omap_host->dev; + + if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); + if (!(reg & (CAPA_VS33 | CAPA_VS30))) + return -EOPNOTSUPP; + + sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage); + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); + reg &= ~AC12_V1V8_SIGEN; + sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg); + + if (omap_host->io_3_3v_support) + iov = IOV_3V3; + else + iov = IOV_3V0; + } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); + if (!(reg & CAPA_VS18)) + return -EOPNOTSUPP; + + sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage); + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); + reg |= AC12_V1V8_SIGEN; + sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg); + + iov = IOV_1V8; + } else { + return -EOPNOTSUPP; + } + + ret = sdhci_omap_enable_iov(omap_host, iov); + if (ret) { + dev_err(dev, "failed to switch IO voltage to %dmV\n", iov); + return ret; + } + + dev_dbg(dev, "IO voltage switched to %dmV\n", iov); + return 0; +} + +static void sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host) +{ + u32 reg; + + /* voltage capabilities might be set by boot loader, clear it */ + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); + reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33); + + if (omap_host->flags & SDHCI_OMAP_SUPPORTS_DUAL_VOLT) { + if (omap_host->io_3_3v_support) + reg |= (CAPA_VS33 | CAPA_VS18); + else + reg |= (CAPA_VS30 | CAPA_VS18); + } else if (omap_host->flags & SDHCI_OMAP_NO_1_8_V) { + if (omap_host->io_3_3v_support) + reg |= CAPA_VS33; + else + reg |= CAPA_VS30; + } else { + reg |= CAPA_VS18; + } + + sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg); +} + +static void sdhci_omap_set_bus_mode(struct sdhci_host *host, unsigned int mode) +{ + u32 reg; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); + if (mode == MMC_BUSMODE_OPENDRAIN) + reg |= CON_OD; + else + reg &= ~CON_OD; + sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); +} + +static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); + u32 reg; + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); + if (width == MMC_BUS_WIDTH_8) + reg |= CON_DW8; + else + reg &= ~CON_DW8; + sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); + + sdhci_set_bus_width(host, width); +} + +static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode) +{ + u32 reg; + ktime_t timeout; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); + + if (omap_host->power_mode == power_mode) + return; + + if (power_mode != MMC_POWER_ON) + return; + + disable_irq(host->irq); + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); + reg |= CON_INIT; + sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); + sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0); + + /* wait 1ms */ + timeout = ktime_add_ms(ktime_get(), MMC_TIMEOUT); + while (!(sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)) { + if (WARN_ON(ktime_after(ktime_get(), timeout))) + return; + usleep_range(5, 10); + } + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); + reg &= ~CON_INIT; + sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); + sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN); + + enable_irq(host->irq); + + omap_host->power_mode = power_mode; +} + +static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host, + unsigned int clock) +{ + u16 dsor; + + dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock); + if (dsor > SYSCTL_CLKD_MAX) + dsor = SYSCTL_CLKD_MAX; + + return dsor; +} + +static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host) +{ + u32 reg; + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL); + reg |= SYSCTL_CEN; + sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg); +} + +static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host) +{ + u32 reg; + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL); + reg &= ~SYSCTL_CEN; + sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg); +} + +static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); + unsigned long clkdiv; + + if (!clock) + return; + + sdhci_omap_stop_clock(omap_host); + + clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock); + clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT; + sdhci_enable_clk(host, clkdiv); + + sdhci_omap_start_clock(omap_host); +} + +static int sdhci_omap_enable_dma(struct sdhci_host *host) +{ + u32 reg; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); + reg |= CON_DMA_MASTER; + sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); + + return 0; +} + +unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + + return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX; +} + +static struct sdhci_ops sdhci_omap_ops = { + .set_clock = sdhci_omap_set_clock, + .enable_dma = sdhci_omap_enable_dma, + .get_max_clock = sdhci_pltfm_clk_get_max_clock, + .get_min_clock = sdhci_omap_get_min_clock, + .set_bus_width = sdhci_omap_set_bus_width, + .platform_send_init_74_clocks = sdhci_omap_init_74_clocks, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, + .set_bus_mode = sdhci_omap_set_bus_mode, +}; + +void sdhci_omap_get_of_property(struct sdhci_omap_host *omap_host) +{ + struct device *dev = omap_host->dev; + struct sdhci_host *host = omap_host->host; + struct mmc_host *mmc = host->mmc; + + if (device_property_read_bool(dev, "ti,dual-volt")) + omap_host->flags |= SDHCI_OMAP_SUPPORTS_DUAL_VOLT; + + if (device_property_read_bool(dev, "no-1-8-v")) + omap_host->flags |= SDHCI_OMAP_NO_1_8_V; + + if (device_property_read_bool(dev, "ti,non-removable")) + mmc->caps |= MMC_CAP_NONREMOVABLE; +} + +static const struct sdhci_pltfm_data sdhci_omap_pdata = { + .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | + SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | + SDHCI_QUIRK_NO_HISPD_BIT | + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, + .quirks2 = SDHCI_QUIRK2_NO_1_8_V | + SDHCI_QUIRK2_ACMD23_BROKEN | + SDHCI_QUIRK2_NO_CRC_STRIPPING | + SDHCI_QUIRK2_FORCE_ADMA | + SDHCI_QUIRK2_BROKEN_POWER_CONTROL, + .ops = &sdhci_omap_ops, +}; + +static const struct sdhci_omap_data dra7_data = { + .offset = 0x200, +}; + +static const struct of_device_id omap_sdhci_match[] = { + { .compatible = "ti,dra7-sdhci", .data = &dra7_data }, + {}, +}; +MODULE_DEVICE_TABLE(of, omap_sdhci_match); + +static int sdhci_omap_probe(struct platform_device *pdev) +{ + int ret; + u32 offset; + struct device *dev = &pdev->dev; + struct sdhci_host *host; + struct sdhci_pltfm_host *pltfm_host; + struct sdhci_omap_host *omap_host; + struct mmc_host *mmc; + const struct of_device_id *match; + struct sdhci_omap_data *data; + + match = of_match_device(omap_sdhci_match, dev); + if (!match) + return -EINVAL; + + data = (struct sdhci_omap_data *)match->data; + if (!data) { + dev_err(dev, "no sdhci omap data\n"); + return -EINVAL; + } + + offset = data->offset; + + host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata, + sizeof(*omap_host)); + if (IS_ERR(host)) { + dev_err(dev, "Failed sdhci_pltfm_init\n"); + return PTR_ERR(host); + } + + pltfm_host = sdhci_priv(host); + omap_host = sdhci_pltfm_priv(pltfm_host); + omap_host->host = host; + omap_host->base = host->ioaddr; + omap_host->dev = dev; + sdhci_omap_get_of_property(omap_host); + + host->ioaddr += offset; + + mmc = host->mmc; + ret = mmc_of_parse(mmc); + if (ret) + goto err_of_parse; + + pltfm_host->clk = devm_clk_get(dev, "fck"); + if (IS_ERR(pltfm_host->clk)) { + ret = PTR_ERR(pltfm_host->clk); + goto err_of_parse; + } + + ret = clk_set_rate(pltfm_host->clk, mmc->f_max); + if (ret) { + dev_err(dev, "failed to set clock to %d\n", mmc->f_max); + goto err_of_parse; + } + + omap_host->pbias = devm_regulator_get_optional(dev, "pbias"); + if (IS_ERR(omap_host->pbias)) { + ret = PTR_ERR(omap_host->pbias); + if (ret != -ENODEV) { + dev_err(dev, "CONFIG_REGULATOR_PBIAS not enabled??\n"); + return ret; + } + dev_dbg(dev, "unable to get pbias regulator %ld\n", + PTR_ERR(omap_host->pbias)); + } else { + if (regulator_is_supported_voltage(omap_host->pbias, IOV_3V3, + IOV_3V3)) + omap_host->io_3_3v_support = true; + dev_vdbg(dev, "Max PBIAS support Voltage: %dmv\n", + omap_host->io_3_3v_support ? IOV_3V3 : IOV_3V0); + } + omap_host->pbias_enabled = false; + + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + goto err_get_sync; + } + + sdhci_omap_set_capabilities(omap_host); + + host->mmc_host_ops.get_ro = mmc_gpio_get_ro; + host->mmc_host_ops.start_signal_voltage_switch = + sdhci_omap_start_signal_voltage_switch; + + ret = sdhci_add_host(host); + if (ret) + goto err_get_sync; + + return 0; + +err_get_sync: + pm_runtime_put_sync(dev); + pm_runtime_disable(dev); + +err_of_parse: + sdhci_pltfm_free(pdev); + return ret; +} + +static int sdhci_omap_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct sdhci_host *host = platform_get_drvdata(pdev); + + sdhci_remove_host(host, true); + pm_runtime_put_sync(dev); + pm_runtime_disable(dev); + sdhci_pltfm_free(pdev); + + return 0; +} + +static struct platform_driver sdhci_omap_driver = { + .probe = sdhci_omap_probe, + .remove = sdhci_omap_remove, + .driver = { + .name = "sdhci-omap", + .of_match_table = of_match_ptr(omap_sdhci_match), + }, +}; + +module_platform_driver(sdhci_omap_driver); + +MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs"); +MODULE_AUTHOR("Texas Instruments Inc."); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("OMAP SDHCI Driver"); From patchwork Mon Aug 7 16:01:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 109580 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1786399qge; Mon, 7 Aug 2017 09:03:32 -0700 (PDT) X-Received: by 10.99.45.194 with SMTP id t185mr948062pgt.295.1502121812738; Mon, 07 Aug 2017 09:03:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502121812; cv=none; d=google.com; s=arc-20160816; b=m2Bi+TtI5Hmj9ak14E6w9y1D9gK53+FkIdG+CgqDDfLR64s4Pdodxn2hz+TiDcSSyc A3dMCcoUwePGKiL2E8ZsCulOdTQJw2zPTpJA8R48uVX0UZIQpStJXdQ5+DRIY5tzfTRC JbcqKPq5ToA4Af7gmCyEOY8cZq25UNw9D5BVXKlH7mGqQ5C5A7z7h/2ovRQlH8bt4EAA Unhnm5k7ZrNQk6MZsZMmcN/LPRYb8aXomp1RMrfYwqCb6/wWaLalpV7N8AuJwkmlyMrh BvaN3BksdeG5XkCaBusueqayCbXKw03TmsT2N75I82IoBbjPZRjKSeuQqxJ877uiXB2p JB1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=G4aa+frHPDFosTttzrijpyzhqkRJMYX2oWDyGfjxjuk=; b=gxaP0jOKLn5WqSTdE8whd1BLSUjpsrmI1Z7WvkZomwDjRs4ydZEKSVS4T7vKZSlKkn Lsul7uChK7K8IcFjKeVcs0GJGkWsOM90Z7PM72IpM0RSBrLdu6AakVlHhm2vt8xGl4Ze PkcXbZ41XelaWvobgWcs6YA/6W3YRmAoeRyfhgluyKgmZ9923wIkrw4EhIDYWmH3+fft fVWUaj7B1ydnMNxwpw5uYRGmuF0fov68unRx80PxRg4p0H8bQ8jSKatZkmOKDgh1Zl1j nudf+K8jHpvxQiYm2JHfZwWNRGfFc7CJjnap9FYmhW7HBl3qU01LHYxnlO7HTJ4e8gRb 3Prw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.b=RJi0j/gO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u12si4797242pgo.759.2017.08.07.09.03.32; Mon, 07 Aug 2017 09:03:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.b=RJi0j/gO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752166AbdHGQD3 (ORCPT + 25 others); Mon, 7 Aug 2017 12:03:29 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:38827 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752122AbdHGQDK (ORCPT ); Mon, 7 Aug 2017 12:03:10 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v77G2H5w015917; Mon, 7 Aug 2017 11:02:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1502121737; bh=Rf9AV9tGOd0hSda3y4rgH+aJrOyCBQSN7rG+uMU31HI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RJi0j/gOnduJFZXlrCp36itHeSQwBKaHUhSBUqKQMVglxZ/oqxVxIewDlus1gn9UW wT++juMZmQCOrniT1X0CD2lrNXRIcxDE2mBouj0tH9Rl9Xv5tXwHEyt0mTAq8y8p0u nNGV3lLxofbnLPJASwh7zQp9JRrLcZtQKs/zoLVE= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v77G2CPZ008072; Mon, 7 Aug 2017 11:02:12 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Mon, 7 Aug 2017 11:02:11 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v77G1jGx023497; Mon, 7 Aug 2017 11:02:09 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Tony Lindgren , Rob Herring , Adrian Hunter CC: , , , , , Subject: [RFC PATCH 7/7] MAINTAINERS: Add TI OMAP SDHCI Maintainer Date: Mon, 7 Aug 2017 21:31:42 +0530 Message-ID: <20170807160142.12134-8-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170807160142.12134-1-kishon@ti.com> References: <20170807160142.12134-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Maintainer for the TI OMAP SDHCI driver. Signed-off-by: Kishon Vijay Abraham I --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.11.0 diff --git a/MAINTAINERS b/MAINTAINERS index f66488dfdbc9..10c9dde27c0a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11769,6 +11769,12 @@ L: linux-mmc@vger.kernel.org S: Maintained F: drivers/mmc/host/sdhci-spear.c +SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) TI OMAP DRIVER +M: Kishon Vijay Abraham I +L: linux-mmc@vger.kernel.org +S: Maintained +F: drivers/mmc/host/sdhci-omap.c + SECURE ENCRYPTING DEVICE (SED) OPAL DRIVER M: Scott Bauer M: Jonathan Derrick