From patchwork Thu Jul 20 19:52:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 108437 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp2551446qge; Thu, 20 Jul 2017 12:53:30 -0700 (PDT) X-Received: by 10.99.119.206 with SMTP id s197mr345501pgc.439.1500580410741; Thu, 20 Jul 2017 12:53:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500580410; cv=none; d=google.com; s=arc-20160816; b=ffKBC7PT7wkVdDLGyd7rCAiKSv8fsDrl1zK6w9KxKwsg4Y+6C2+HdCxKnHF3UzH0ms 0MZc55IxUyxLdgcajeQb8cMNAWwOcS31wdG+6Rf530rrXRBA5UJf0q7O8yQAqPrJz15o 7VxRMb5xOBfIoCUgPIGjgL2csItoLEGQKRQ9PNbim/WSzqvIpeQz8UZt/XKfwpb9ITmG uazzVZH234Mu0+oMLGuv7ajFzS78LXVmmfRdUE6OHtV/kKhtvwSgNe9gxLVlUSEc8blR 0YrLA4bsDKj7v07A6Mqs7kOb/9iJVN5rfrQmZhLGWRa9m6jZU+wdhntYXK+NulfLTnf3 L6kQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=xhG5o9jfhup+L4P4phZFuWdcbs0ZWfOksJZrePpa/d8=; b=zaWqiWCTAYNF+dkJkacdoyEjF7JeT+3VPSFt4XHU5byTCOtcIzNaJ5pqvdwvX7WrF+ ZK5LLjHIzllPku4ybay6D+yGxdTXYDg7yL5f4aP5t7UiNBygDUUYrViGTgjWzXY99jj3 ojWr58GF10EHZr6KgaizyvOKSNAwNErhVWhbOqa8pdiKK9F/grqk7MSTxF5I52Q7D75U QDMENND9Lr2m1j9q8nVGWG+O9ovZSW5zdyPN9ye9UxFtsGQXuF+C84jDjVjqo7FFbAet BmZFcTDC8T7CXOUi7Hak+HaFQQTQ13qDqMXCh9eddnIFHAl4fWGUbtoJdTLwdA95R0Eg OYAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=JysnrTI9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z9si1980696plh.729.2017.07.20.12.53.29; Thu, 20 Jul 2017 12:53:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=JysnrTI9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936578AbdGTTx1 (ORCPT + 25 others); Thu, 20 Jul 2017 15:53:27 -0400 Received: from mail-wm0-f50.google.com ([74.125.82.50]:37001 "EHLO mail-wm0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934707AbdGTTw4 (ORCPT ); Thu, 20 Jul 2017 15:52:56 -0400 Received: by mail-wm0-f50.google.com with SMTP id g127so35886360wmd.0 for ; Thu, 20 Jul 2017 12:52:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xhG5o9jfhup+L4P4phZFuWdcbs0ZWfOksJZrePpa/d8=; b=JysnrTI9gBq1EGZFAbE7mn6F8rBJgPDx1yIY31xBsVtS83aJgsJsL00bzLybLe3MKG LSopAqgTuddr6WLrYoVNSqQJGYhTTa0B1Crd0VLSUPP39BIXtD8KLQ0ioj72dpSVV58W OQx65eMmCygAWOm5o5VbkC+rURC6XVXu3VOdM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xhG5o9jfhup+L4P4phZFuWdcbs0ZWfOksJZrePpa/d8=; b=b0wITCSJ71hvmMtSgzJY5BqxK0OtKo1ceRg75XlB0dxj1+mds0zatjV4RlvU2VI++B Ju6EBOWC6qI8GFehgZmMiOeAMYGnQHyCTfhs79UQQSNUiCL4oqAG6xkWs9FE95rvQpx9 P6fm0bvjjbQbSuUP/7BtnI59vDv0+8hDXkAorgG7EWTwN/AQXbDP8UE/w7ntHHgMNEdM lrU2BkjIuLUaIgIeTM/DqJgjS83gjiNRl2CH7o/TylE1/9TA1WDydIj4uitvlFVy+EPy uCDUguE9+OM/RwSnybSUF0tnkEK2tphFLsNQ/4DdoVXbgkdcUnbwShi6Vdd81yflEQbI SKSg== X-Gm-Message-State: AIVw1102EvuwwrHtdTWytsooqGg5YBi91FTBKwJN9QhNZi5ImpWC2ioA d7pc5Y79nJYOyP51 X-Received: by 10.28.23.195 with SMTP id 186mr2974510wmx.173.1500580374796; Thu, 20 Jul 2017 12:52:54 -0700 (PDT) Received: from mms-0441.qualcomm.mm-sol.com ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id h10sm2643134wme.30.2017.07.20.12.52.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Jul 2017 12:52:53 -0700 (PDT) From: Georgi Djakov To: linux-pm@vger.kernel.org Cc: rjw@rjwysocki.net, robh+dt@kernel.org, khilman@baylibre.com, mturquette@baylibre.com, gregkh@linuxfoundation.org, vincent.guittot@linaro.org, skannan@codeaurora.org, sboyd@codeaurora.org, andy.gross@linaro.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, seansw@qti.qualcomm.com, davidai@quicinc.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v2 1/2] interconnect: Add generic on-chip interconnect API Date: Thu, 20 Jul 2017 22:52:49 +0300 Message-Id: <20170720195250.13462-2-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170720195250.13462-1-georgi.djakov@linaro.org> References: <20170720195250.13462-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch introduce a new API to get requirements and configure the interconnect buses across the entire chipset to fit with the current demand. The API is using a consumer/provider-based model, where the providers are the interconnect buses and the consumers could be various drivers. The consumers request interconnect resources (path) between endpoints and set the desired constraints on this data flow path. The providers receive requests from consumers and aggregate these requests for all master-slave pairs on that path. Then the providers configure each participating in the topology node according to the requested data flow path, physical links and constraints. The topology could be complicated and multi-tiered and is SoC specific. Signed-off-by: Georgi Djakov --- Documentation/interconnect/interconnect.rst | 93 +++++++ drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/interconnect/Kconfig | 10 + drivers/interconnect/Makefile | 1 + drivers/interconnect/interconnect.c | 389 ++++++++++++++++++++++++++++ include/linux/interconnect-consumer.h | 72 +++++ include/linux/interconnect-provider.h | 117 +++++++++ 8 files changed, 685 insertions(+) create mode 100644 Documentation/interconnect/interconnect.rst create mode 100644 drivers/interconnect/Kconfig create mode 100644 drivers/interconnect/Makefile create mode 100644 drivers/interconnect/interconnect.c create mode 100644 include/linux/interconnect-consumer.h create mode 100644 include/linux/interconnect-provider.h diff --git a/Documentation/interconnect/interconnect.rst b/Documentation/interconnect/interconnect.rst new file mode 100644 index 000000000000..b057e9c12d70 --- /dev/null +++ b/Documentation/interconnect/interconnect.rst @@ -0,0 +1,93 @@ +===================================== +GENERIC SYSTEM INTERCONNECT SUBSYSTEM +===================================== + +Introduction +------------ + +This framework is designed to provide a standard kernel interface to control +the settings of the interconnects on a SoC. These settings can be throughput, +latency and priority between multiple interconnected devices. This can be +controlled dynamically in order to save power or provide maximum performance. + +The interconnect bus is a hardware with configurable parameters, which can be +set on a data path according to the requests received from various drivers. +An example of interconnect buses are the interconnects between various +components on chipsets. There can be multiple interconnects on a SoC that can +be multi-tiered. + +Below is a simplified diagram of a real-world SoC interconnect bus topology. + +:: + + +----------------+ +----------------+ + | HW Accelerator |--->| M NoC |<---------------+ + +----------------+ +----------------+ | + | | +------------+ + +-----+ +-------------+ V +------+ | | + | DDR | | +--------+ | PCIe | | | + +-----+ | | Slaves | +------+ | | + ^ ^ | +--------+ | | C NoC | + | | V V | | + +------------------+ +------------------------+ | | +-----+ + | |-->| |-->| |-->| CPU | + | |-->| |<--| | +-----+ + | Mem NoC | | S NoC | +------------+ + | |<--| |---------+ | + | |<--| |<------+ | | +--------+ + +------------------+ +------------------------+ | | +-->| Slaves | + ^ ^ ^ ^ ^ | | +--------+ + | | | | | | V + +------+ | +-----+ +-----+ +---------+ +----------------+ +--------+ + | CPUs | | | GPU | | DSP | | Masters |-->| P NoC |-->| Slaves | + +------+ | +-----+ +-----+ +---------+ +----------------+ +--------+ + | + +-------+ + | Modem | + +-------+ + +Terminology +----------- + +Interconnect provider is the software definition of the interconnect hardware. +The interconnect providers on the above diagram are M NoC, S NoC, C NoC and Mem +NoC. + +Interconnect node is the software definition of the interconnect hardware +port. Each interconnect provider consists of multiple interconnect nodes, +which are connected to other SoC components including other interconnect +providers. The point on the diagram where the CPUs connects to the memory is +called an interconnect node, which belongs to the Mem NoC interconnect provider. + +Interconnect endpoits are the first or the last element of the path. Every +endpoint is a node, but not every node is an endpoint. + +Interconnect path is everything between two endpoints including all the nodes +that have to be traversed to reach from a source to destination node. It may +include multiple master-slave pairs across several interconnect providers. + +Interconnect consumers are the entities which make use of the data paths exposed +by the providers. The consumers send requests to providers requesting various +throughput, latency and priority. Usually the consumers are device drivers, that +send request based on their needs. An example for a consumer is a a video +decoder that supports various formats and image sizes. + +Interconnect providers +---------------------- + +Interconnect provider is an entity that implements methods to initialize and +configure a interconnect bus hardware. The interconnect provider driver should +be registered with the interconnect provider core. + +The interconnect framework provider API functions are documented in +.. kernel-doc:: include/linux/interconnect-provider.h + +Interconnect consumers +---------------------- + +Interconnect consumers are the clients which use the interconnect APIs to +get paths between endpoints and set their bandwidth/latency/QoS requirements +for these interconnect paths. + +The interconnect framework consumer API functions are documented in +.. kernel-doc:: include/linux/interconnect-consumer.h diff --git a/drivers/Kconfig b/drivers/Kconfig index 505c676fa9c7..930ecde654d5 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -208,4 +208,6 @@ source "drivers/tee/Kconfig" source "drivers/mux/Kconfig" +source "drivers/interconnect/Kconfig" + endmenu diff --git a/drivers/Makefile b/drivers/Makefile index dfdcda00bfe3..a114b679bb5b 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -182,3 +182,4 @@ obj-$(CONFIG_FPGA) += fpga/ obj-$(CONFIG_FSI) += fsi/ obj-$(CONFIG_TEE) += tee/ obj-$(CONFIG_MULTIPLEXER) += mux/ +obj-$(CONFIG_INTERCONNECT) += interconnect/ diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig new file mode 100644 index 000000000000..1e50e951cdc1 --- /dev/null +++ b/drivers/interconnect/Kconfig @@ -0,0 +1,10 @@ +menuconfig INTERCONNECT + tristate "On-Chip Interconnect management support" + help + Support for management of the on-chip interconnects. + + This framework is designed to provide a generic interface for + managing the interconnects in a SoC. + + If unsure, say no. + diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile new file mode 100644 index 000000000000..d9da6a6c3560 --- /dev/null +++ b/drivers/interconnect/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_INTERCONNECT) += interconnect.o diff --git a/drivers/interconnect/interconnect.c b/drivers/interconnect/interconnect.c new file mode 100644 index 000000000000..237ad2c8fd6e --- /dev/null +++ b/drivers/interconnect/interconnect.c @@ -0,0 +1,389 @@ +/* + * Copyright (c) 2017, Linaro Ltd. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_MUTEX(interconnect_provider_list_mutex); +static LIST_HEAD(interconnect_provider_list); + +/** + * struct interconnect_path - interconnect path structure + * @num_nodes: number of hops (nodes) + * @reqs: array of the requests applicable to this path of nodes + */ +struct interconnect_path { + size_t num_nodes; + struct interconnect_req reqs[0]; +}; + +static struct interconnect_node *node_find(const char *dev_id, int con_id) +{ + struct icp *icp; + struct interconnect_node *node = ERR_PTR(-EPROBE_DEFER); + int match, best = 0; + + mutex_lock(&interconnect_provider_list_mutex); + + list_for_each_entry(icp, &interconnect_provider_list, icp_list) { + struct interconnect_node *n; + + match = 0; + + list_for_each_entry(n, &icp->nodes, icn_list) { + if (n->dev_id) { + if (!dev_id || strncmp(n->dev_id, dev_id, + strlen(dev_id))) + continue; + match += 2; + } + if (n->con_id) { + if (!con_id || n->con_id != con_id) + continue; + match += 1; + } + if (match > best) { + node = n; + if (match == 3) + goto out; + + best = match; + } + } + } + +out: + mutex_unlock(&interconnect_provider_list_mutex); + + return node; +} + +static struct interconnect_path *path_allocate(struct interconnect_node *node, + ssize_t num_nodes) +{ + struct interconnect_path *path; + size_t i; + + path = kzalloc(sizeof(*path) + num_nodes * sizeof(*path->reqs), + GFP_KERNEL); + if (!path) + return ERR_PTR(-ENOMEM); + + path->num_nodes = num_nodes; + + for (i = 0; i < num_nodes; i++) { + hlist_add_head(&path->reqs[i].req_node, &node->req_list); + + /* TODO: populate default values */ + path->reqs[i].node = node; + node = node->reverse; + } + + return path; +} + +static struct interconnect_path *path_find(struct interconnect_node *src, + struct interconnect_node *dst) +{ + struct list_head edge_list; + struct list_head traverse_list; + struct list_head tmp_list; + struct interconnect_node *node = NULL; + size_t i, number = 1; + bool found = false; + + INIT_LIST_HEAD(&traverse_list); + INIT_LIST_HEAD(&edge_list); + INIT_LIST_HEAD(&tmp_list); + + list_add_tail(&src->search_list, &traverse_list); + + do { + list_for_each_entry(node, &traverse_list, search_list) { + if (node == dst) { + found = true; + list_add(&node->search_list, &tmp_list); + break; + } + for (i = 0; i < node->num_links; i++) { + struct interconnect_node *tmp = node->links[i]; + + if (!tmp) { + WARN_ON(1); + return ERR_PTR(-ENOENT); + } + + if (tmp->is_traversed) + continue; + + tmp->is_traversed = true; + tmp->reverse = node; + list_add_tail(&tmp->search_list, &edge_list); + } + } + if (found) + break; + + list_splice_init(&traverse_list, &tmp_list); + list_splice_init(&edge_list, &traverse_list); + + /* count the number of nodes */ + number++; + + } while (!list_empty(&traverse_list)); + + /* reset the traversed state */ + list_for_each_entry(node, &tmp_list, search_list) { + node->is_traversed = false; + } + + if (found) + return path_allocate(dst, number); + + return ERR_PTR(-EPROBE_DEFER); +} + +static int path_init(struct interconnect_path *path) +{ + struct interconnect_node *node; + size_t i; + + for (i = 0; i < path->num_nodes; i++) { + node = path->reqs[i].node; + + mutex_lock(&node->icp->lock); + node->icp->users++; + mutex_unlock(&node->icp->lock); + } + + return 0; +} + +static int interconnect_aggregate(struct interconnect_node *node, + struct interconnect_creq *creq) +{ + struct interconnect_node *n; + struct interconnect_req *r; + struct icp *icp = node->icp; + u32 avg_bw = 0; + u32 peak_bw = 0; + + mutex_lock(&node->icp->lock); + + /* TODO: add interconnect provider specific aggregate() callback */ + + list_for_each_entry(n, &node->icp->nodes, icn_list) { + hlist_for_each_entry(r, &n->req_list, req_node) { + /* sum the average and max the peak */ + avg_bw += r->avg_bw; + peak_bw = max(peak_bw, r->peak_bw); + } + } + + /* save the aggregated values */ + icp->creq.avg_bw = avg_bw; + icp->creq.peak_bw = peak_bw; + + mutex_unlock(&node->icp->lock); + + return 0; +} + +/** + * interconnect_set() - set constraints on a path between two endpoints + * @path: reference to the path returned by interconnect_get() + * @creq: request from the consumer, containing its requirements + * + * This function is used by an interconnect consumer to express its own needs + * in term of bandwidth and QoS for a previously requested path between two + * endpoints. The requests are aggregated and each node is updated accordingly. + * + * Returns 0 on success, or an approproate error code otherwise. + */ +int interconnect_set(struct interconnect_path *path, + struct interconnect_creq *creq) +{ + struct interconnect_node *next, *prev = NULL; + size_t i; + int ret = 0; + + for (i = 0; i < path->num_nodes; i++, prev = next) { + next = path->reqs[i].node; + + /* + * Both endpoints should be valid and master-slave pairs of + * the same interconnect provider that will be configured. + */ + if (!next || !prev) + continue; + if (next->icp != prev->icp) + continue; + + /* update the consumer requirements for this path */ + path->reqs[i].avg_bw = creq->avg_bw; + path->reqs[i].peak_bw = creq->peak_bw; + + /* aggregate requests from all consumers */ + ret = interconnect_aggregate(next, creq); + if (ret) + goto out; + + if (next->icp->ops->set) { + mutex_lock(&next->icp->lock); + /* commit the aggregated constraints */ + ret = next->icp->ops->set(prev, next, &next->icp->creq); + mutex_unlock(&next->icp->lock); + if (ret) + goto out; + } + } + +out: + return ret; +} + +/** + * interconnect_get() - return a handle for path between two endpoints + * @sdev: source device identifier + * @sid: source device port id + * @ddev: destination device identifier + * @did: destination device port id + * + * This function will search for a path between two endpoints and return an + * interconnect_path handle on success. Use interconnect_put() to release + * constraints when the they are not needed anymore. + * + * Return: interconnect_path pointer on success, or ERR_PTR() on error + */ +struct interconnect_path *interconnect_get(const char *sdev, const int sid, + const char *ddev, const int did) +{ + struct interconnect_node *src, *dst; + struct interconnect_path *path; + int ret; + + src = node_find(sdev, sid); + if (IS_ERR(src)) + return ERR_CAST(src); + + dst = node_find(ddev, did); + if (IS_ERR(dst)) + return ERR_CAST(dst); + + /* TODO: cache the path */ + path = path_find(src, dst); + if (IS_ERR(path)) { + pr_err("error finding path between %p and %p (%ld)\n", + src, dst, PTR_ERR(path)); + return path; + } + + ret = path_init(path); + if (ret) + return ERR_PTR(ret); + + return path; +} +EXPORT_SYMBOL_GPL(interconnect_get); + +/** + * interconnect_put() - release the reference to the interconnect_path + * + * @path: interconnect path + * + * Use this function to release the path and free the memory when setting + * constraints on the path is no longer needed. + */ +void interconnect_put(struct interconnect_path *path) +{ + struct interconnect_creq creq = { 0, 0 }; + struct interconnect_node *node; + size_t i; + int ret; + + if (IS_ERR(path)) + return; + + for (i = 0; i < path->num_nodes; i++) { + node = path->reqs[i].node; + + /* + * Remove the constraints from the path, + * update the nodes and free the memory + */ + ret = interconnect_set(path, &creq); + if (ret) + pr_err("%s error %d\n", __func__, ret); + + mutex_lock(&node->icp->lock); + node->icp->users--; + mutex_unlock(&node->icp->lock); + } + + kfree(path); +} +EXPORT_SYMBOL_GPL(interconnect_put); + +/** + * interconnect_add_provider() - add a new interconnect provider + * @icp: the interconnect provider that will be added into topology + * + * Return: 0 on success, or an error code otherwise + */ +int interconnect_add_provider(struct icp *icp) +{ + WARN(!icp->ops->set, "%s: .set is not implemented\n", __func__); + + mutex_lock(&interconnect_provider_list_mutex); + mutex_init(&icp->lock); + list_add(&icp->icp_list, &interconnect_provider_list); + mutex_unlock(&interconnect_provider_list_mutex); + + dev_info(icp->dev, "interconnect provider is added to topology\n"); + + return 0; +} +EXPORT_SYMBOL_GPL(interconnect_add_provider); + +/** + * interconnect_del_provider() - delete previously added interconnect provider + * @icp: the interconnect provider that will be removed from topology + * + * Return: 0 on success, or an error code otherwise + */ +int interconnect_del_provider(struct icp *icp) +{ + mutex_lock(&icp->lock); + if (icp->users) { + mutex_unlock(&icp->lock); + return -EBUSY; + } + mutex_unlock(&icp->lock); + + mutex_lock(&interconnect_provider_list_mutex); + list_del(&icp->icp_list); + mutex_unlock(&interconnect_provider_list_mutex); + + return 0; +} +EXPORT_SYMBOL_GPL(interconnect_del_provider); + +MODULE_AUTHOR("Georgi Djakov + +/** + * struct icp_ops - platform specific callback operations for interconnect + * providers that will be called from drivers + * + * @set: set constraints on interconnect + */ +struct icp_ops { + int (*set)(struct interconnect_node *src, struct interconnect_node *dst, + struct interconnect_creq *creq); +}; + +/** + * struct icp - interconnect provider (controller) entity that might + * provide multiple interconnect controls + * + * @icp_list: list of the registered interconnect providers + * @nodes: internal list of the interconnect provider nodes + * @ops: pointer to device specific struct icp_ops + * @dev: the device this interconnect provider belongs to + * @lock: a lock to protect creq and users + * @creq: the actual state of constraints for this interconnect provider + * @users: count of active users + * @data: pointer to private data + */ +struct icp { + struct list_head icp_list; + struct list_head nodes; + const struct icp_ops *ops; + struct device *dev; + struct mutex lock; + struct interconnect_creq creq; + int users; + void *data; +}; + +/** + * struct interconnect_node - entity that is part of the interconnect topology + * + * @links: links to other interconnect nodes + * @num_links: number of links to other interconnect nodes + * @icp: points to the interconnect provider of this node + * @icn_list: list of interconnect nodes + * @search_list: list used when walking the nodes graph + * @reverse: pointer to previous node when walking the nodes graph + * @is_traversed: flag that is used when walking the nodes graph + * @req_list: a list of QoS constraint requests + * @dev_id: device id + * @con_id: connection id + */ +struct interconnect_node { + struct interconnect_node **links; + size_t num_links; + + struct icp *icp; + struct list_head icn_list; + struct list_head search_list; + struct interconnect_node *reverse; + bool is_traversed; + struct hlist_head req_list; + + const char *dev_id; + int con_id; +}; + +/** + * struct interconnect_req - constraints that are attached to each node + * + * @req_node: the linked list node + * @node: the interconnect node to which this constraint applies + * @avg_bw: an integer describing the average bandwidth in kbps + * @peak_bw: an integer describing the peak bandwidth in kbps + */ +struct interconnect_req { + struct hlist_node req_node; + struct interconnect_node *node; + u32 avg_bw; + u32 peak_bw; +}; + +#if IS_ENABLED(CONFIG_INTERCONNECT) + +int interconnect_add_provider(struct icp *icp); +int interconnect_del_provider(struct icp *icp); + +#else + +static inline int interconnect_add_provider(struct icp *icp) +{ + return -ENOTSUPP; +} + +static inline int interconnect_del_provider(struct icp *icp) +{ + return -ENOTSUPP; +} + +#endif /* CONFIG_INTERCONNECT */ + +#endif /* _LINUX_INTERCONNECT_PROVIDER_H */ From patchwork Thu Jul 20 19:52:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 108436 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp2551087qge; Thu, 20 Jul 2017 12:53:07 -0700 (PDT) X-Received: by 10.99.1.211 with SMTP id 202mr4856564pgb.311.1500580387697; Thu, 20 Jul 2017 12:53:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500580387; cv=none; d=google.com; s=arc-20160816; b=cap9EYgLN11k8mNpzqddn8yLkaeKdV5xaBxgsjG1PWNqxMXRFuStEYrotUjyEQhsSK OUXBHJhKgSWRk4tmT/3+VuHCva85xDlfXQHXbii7Mj+hxGFQRAjINAQx+GU8Jvx3kKgM wDZLco3UjagfXNMcKWf4dMl/JOVme9sTQjSYhPcZbmxdr1o8ifh8nWoQD8AbAt0yHIx1 TtzOTFm6TrrnX1tMRX6b0mABWFxOmMAYnSmjBvzv9CUCghAFCxL2OfkNoFphR2VNuA1l 9iqd5nnAaB+FLuRqRVF6mXRzdhWV8BCuGbmk8aP1mNiW+0B5kZX50OSYaIX8Vzf1jOTy teAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=34kR3xW2caaCN7i2gardk9p+vAh7Y+ukoPIdQn7GsUA=; b=Ck083FtmVPFYVKY7vjncvR/sdl7WhK4TJ/0/bFPBSLhv01PC+hjSlR/SEwxLoiuKa7 Xn8o7CqqFnxHbc4lc5UwRBSidQOa07v+IHqDq7WlbD6eUBHFS2qTZ+dzaNnsWryvRTOi +u48wH9quKwL9toQvFyZr5RBlq/kgkpGGi59qxCEy3o5mojgYQ0/xOyGtl96BXvUrekO xc7kLX2KCuyPkQ7ZGpA92es+deCjHbr8bU6z50hdTbtE7knJpELeYqJKXKTEEpuvpGW8 1LrzYRujE3ZcfpdehIPXaYQ0fintns+2VZcl5NZ7q0uzRbolbGsHRxK3usOesdhzIyqa JBPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=BVssNLz9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h10si1959064pln.765.2017.07.20.12.53.07; Thu, 20 Jul 2017 12:53:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=BVssNLz9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936554AbdGTTxD (ORCPT + 25 others); Thu, 20 Jul 2017 15:53:03 -0400 Received: from mail-wm0-f46.google.com ([74.125.82.46]:37013 "EHLO mail-wm0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936467AbdGTTw6 (ORCPT ); Thu, 20 Jul 2017 15:52:58 -0400 Received: by mail-wm0-f46.google.com with SMTP id g127so35886875wmd.0 for ; Thu, 20 Jul 2017 12:52:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=34kR3xW2caaCN7i2gardk9p+vAh7Y+ukoPIdQn7GsUA=; b=BVssNLz9YrgjAy+YztUeGe1AyNaFJxikm+Gpu6+eQDIVNfiiertPO3O2UYWxzBxjNI eAF4D2SOLQYJPT61iC0xuMruk04dnHsbHmwJbSfOMvl34uuLb7dQjEe9zfyG3dFXKCdA lAzUvvDKiEwtn0gRhDWPsESg5BqN44qR+Q8zQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=34kR3xW2caaCN7i2gardk9p+vAh7Y+ukoPIdQn7GsUA=; b=gaPn/ClE1v3tMvcbvIOZupoCeXe1wCPln248jkAu4Rjx2+E38Qd2/EInJy4evglSt5 b72gFbSKlJSfGJJd1IONbfyWt924BqPUVXI+jAbb1EOC8qYZsJYcu0/eKewOLEEDSw7U v6tyGJWfffN+ImiYFyy8GUbbC4ZSwJJCysnbdhS2an8OmQ5RyWT3WQN6dQ9FelW1PCtI b9wgp/ogRghbwupEzAUgQ/Hcz2r0n17zBHRjjXz+ABLPcHJcpcpbdrfReEuGkFboyo3y ZdR/vznIX0Kzhmmvirv3izEjtbNAa5wfUCcLtn2S8KYTfXpKtsOafDC5JV8vPYo1e2Bd SVmg== X-Gm-Message-State: AIVw113i2UAknFEpnIV9WbEojfkztxhOmgts23GKrEGE0h05krlt+qah Kbz7TkmgcfJQZDORqZ3f0w== X-Received: by 10.28.174.204 with SMTP id x195mr2920437wme.116.1500580376747; Thu, 20 Jul 2017 12:52:56 -0700 (PDT) Received: from mms-0441.qualcomm.mm-sol.com ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id h10sm2643134wme.30.2017.07.20.12.52.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Jul 2017 12:52:55 -0700 (PDT) From: Georgi Djakov To: linux-pm@vger.kernel.org Cc: rjw@rjwysocki.net, robh+dt@kernel.org, khilman@baylibre.com, mturquette@baylibre.com, gregkh@linuxfoundation.org, vincent.guittot@linaro.org, skannan@codeaurora.org, sboyd@codeaurora.org, andy.gross@linaro.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, seansw@qti.qualcomm.com, davidai@quicinc.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v2 2/2] interconnect: Add Qualcomm msm8916 interconnect provider driver Date: Thu, 20 Jul 2017 22:52:50 +0300 Message-Id: <20170720195250.13462-3-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170720195250.13462-1-georgi.djakov@linaro.org> References: <20170720195250.13462-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add driver for the Qualcomm interconnect buses found in msm8916 based platforms. This patch contains only a partial topology to make reviewing easier. Signed-off-by: Georgi Djakov --- drivers/interconnect/Kconfig | 5 + drivers/interconnect/Makefile | 1 + drivers/interconnect/qcom/Kconfig | 12 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/interconnect_msm8916.c | 390 +++++++++++++++++++++++ include/linux/interconnect/qcom-noc.h | 92 ++++++ 6 files changed, 502 insertions(+) create mode 100644 drivers/interconnect/qcom/Kconfig create mode 100644 drivers/interconnect/qcom/Makefile create mode 100644 drivers/interconnect/qcom/interconnect_msm8916.c create mode 100644 include/linux/interconnect/qcom-noc.h diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig index 1e50e951cdc1..b123a76e2f9d 100644 --- a/drivers/interconnect/Kconfig +++ b/drivers/interconnect/Kconfig @@ -8,3 +8,8 @@ menuconfig INTERCONNECT If unsure, say no. +if INTERCONNECT + +source "drivers/interconnect/qcom/Kconfig" + +endif diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile index d9da6a6c3560..62a01de24aeb 100644 --- a/drivers/interconnect/Makefile +++ b/drivers/interconnect/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_INTERCONNECT) += interconnect.o +obj-$(CONFIG_INTERCONNECT_QCOM) += qcom/ diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig new file mode 100644 index 000000000000..1bbbba87549d --- /dev/null +++ b/drivers/interconnect/qcom/Kconfig @@ -0,0 +1,12 @@ +config INTERCONNECT_QCOM + bool "Qualcomm Network-on-Chip interconnect drivers" + depends on INTERCONNECT + depends on ARCH_QCOM || COMPILE_TEST + default y + +config INTERCONNECT_QCOM_MSM8916 + tristate "Qualcomm MSM8916 interconnect driver" + depends on INTERCONNECT_QCOM + help + This is a driver for the Qualcomm Network-on-Chip on msm8916-based platforms. + diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile new file mode 100644 index 000000000000..e5bf8e2b92ac --- /dev/null +++ b/drivers/interconnect/qcom/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += interconnect_msm8916.o + diff --git a/drivers/interconnect/qcom/interconnect_msm8916.c b/drivers/interconnect/qcom/interconnect_msm8916.c new file mode 100644 index 000000000000..ae1cd939dfbb --- /dev/null +++ b/drivers/interconnect/qcom/interconnect_msm8916.c @@ -0,0 +1,390 @@ +/* + * Copyright (C) 2017 Linaro Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define to_qcom_icp(_icp) \ + container_of(_icp, struct qcom_interconnect_provider, icp) +#define to_qcom_node(_node) \ + container_of(_node, struct qcom_interconnect_node, node) + +enum qcom_bus_type { + QCOM_BUS_TYPE_NOC = 0, + QCOM_BUS_TYPE_MEM, +}; + +struct qcom_interconnect_provider { + struct icp icp; + void __iomem *base; + struct clk *bus_clk; + struct clk *bus_a_clk; + u32 base_offset; + u32 qos_offset; + enum qcom_bus_type type; +}; + +struct qcom_interconnect_node { + struct interconnect_node node; + unsigned char *name; + struct interconnect_node *links[8]; + u16 id; + u16 num_links; + u16 port; + u16 buswidth; + u64 rate; +}; + +static struct qcom_interconnect_node snoc_int_0; +static struct qcom_interconnect_node snoc_int_1; +static struct qcom_interconnect_node snoc_int_bimc; +static struct qcom_interconnect_node snoc_bimc_0_mas; +static struct qcom_interconnect_node pnoc_snoc_slv; + +static struct qcom_interconnect_node snoc_bimc_0_slv; +static struct qcom_interconnect_node slv_ebi_ch0; + +static struct qcom_interconnect_node pnoc_int_1; +static struct qcom_interconnect_node mas_pnoc_sdcc_1; +static struct qcom_interconnect_node mas_pnoc_sdcc_2; +static struct qcom_interconnect_node pnoc_snoc_mas; + +struct qcom_interconnect_desc { + struct qcom_interconnect_node **nodes; + size_t num_nodes; +}; + +static struct qcom_interconnect_node snoc_int_0 = { + .id = 10004, + .name = "snoc-int-0", +#if 0 + .links = { &snoc_pnoc_mas.node }, + .num_links = 1, +#endif + .buswidth = 8, +}; + +static struct qcom_interconnect_node snoc_int_1 = { + .id = 10005, + .name = "snoc-int-1", +#if 0 + .links = { &slv_apss.node, &slv_cats_0.node, &slv_cats_1.node }, + .num_links = 3, +#endif + .buswidth = 8, +}; + +static struct qcom_interconnect_node snoc_int_bimc = { + .id = 10006, + .name = "snoc-bimc", + .links = { &snoc_bimc_0_mas.node }, + .num_links = 1, + .buswidth = 8, +}; + +static struct qcom_interconnect_node snoc_bimc_0_mas = { + .id = 10007, + .name = "snoc-bimc-0-mas", + .links = { &snoc_bimc_0_slv.node }, + .num_links = 1, + .buswidth = 8, +}; + +static struct qcom_interconnect_node pnoc_snoc_slv = { + .id = 10011, + .name = "snoc-pnoc", + .links = { &snoc_int_0.node, &snoc_int_bimc.node, &snoc_int_1.node }, + .num_links = 3, + .buswidth = 8, +}; + +static struct qcom_interconnect_node *msm8916_snoc_nodes[] = { + [SNOC_INT_0] = &snoc_int_0, + [SNOC_INT_1] = &snoc_int_1, + [SNOC_INT_BIMC] = &snoc_int_bimc, + [SNOC_BIMC_0_MAS] = &snoc_bimc_0_mas, + [PNOC_SNOC_SLV] = &pnoc_snoc_slv, +}; + +static struct qcom_interconnect_desc msm8916_snoc = { + .nodes = msm8916_snoc_nodes, + .num_nodes = ARRAY_SIZE(msm8916_snoc_nodes), +}; + +static struct qcom_interconnect_node snoc_bimc_0_slv = { + .id = 10025, + .name = "snoc_bimc_0_slv", + .links = { &slv_ebi_ch0.node }, + .num_links = 1, + .buswidth = 8, +}; + +static struct qcom_interconnect_node slv_ebi_ch0 = { + .id = 512, + .name = "slv-ebi-ch0", + .buswidth = 8, +}; + +static struct qcom_interconnect_node *msm8916_bimc_nodes[] = { + [SNOC_BIMC_0_SLV] = &snoc_bimc_0_slv, + [SLV_EBI_CH0] = &slv_ebi_ch0, +}; + +static struct qcom_interconnect_desc msm8916_bimc = { + .nodes = msm8916_bimc_nodes, + .num_nodes = ARRAY_SIZE(msm8916_bimc_nodes), +}; + +static struct qcom_interconnect_node pnoc_int_1 = { + .id = 10013, + .name = "pnoc-int-1", + .links = { &pnoc_snoc_mas.node }, + .num_links = 1, + .buswidth = 8, +}; + +static struct qcom_interconnect_node mas_pnoc_sdcc_1 = { + .id = 78, + .name = "mas-pnoc-sdcc-1", + .links = { &pnoc_int_1.node }, + .num_links = 1, + .port = 7, + .buswidth = 8, +}; + +static struct qcom_interconnect_node mas_pnoc_sdcc_2 = { + .id = 81, + .name = "mas-pnoc-sdcc-2", + .links = { &pnoc_int_1.node }, + .num_links = 1, + .port = 8, + .buswidth = 8, +}; + +static struct qcom_interconnect_node pnoc_snoc_mas = { + .id = 10010, + .name = "pnoc-snoc-mas", + .links = { &pnoc_snoc_slv.node }, + .num_links = 1, + .buswidth = 8, +}; + +static struct qcom_interconnect_node *msm8916_pnoc_nodes[] = { + [PNOC_INT_1] = &pnoc_int_1, + [MAS_PNOC_SDCC_1] = &mas_pnoc_sdcc_1, + [MAS_PNOC_SDCC_2] = &mas_pnoc_sdcc_2, + [PNOC_SNOC_MAS] = &pnoc_snoc_mas, +}; + +static struct qcom_interconnect_desc msm8916_pnoc = { + .nodes = msm8916_pnoc_nodes, + .num_nodes = ARRAY_SIZE(msm8916_pnoc_nodes), +}; + +static int qcom_interconnect_init(struct interconnect_node *node) +{ + struct qcom_interconnect_node *qn = to_qcom_node(node); + int ret = 0; + + /* populate default values */ + if (!qn->buswidth) + qn->buswidth = 8; + + /* TODO: init qos and priority */ + + return ret; +} + +static int qcom_interconnect_set(struct interconnect_node *src, + struct interconnect_node *dst, + struct interconnect_creq *creq) +{ + struct qcom_interconnect_provider *qicp; + struct qcom_interconnect_node *qn; + struct interconnect_node *node; + struct icp *icp; + u64 rate = 0; + int ret = 0; + + if (!src && !dst) + return -ENODEV; + + if (!src) + node = dst; + else + node = src; + + qn = to_qcom_node(node); + icp = qn->node.icp; + qicp = to_qcom_icp(node->icp); + + rate = max(icp->creq.avg_bw, icp->creq.peak_bw); + + do_div(rate, qn->buswidth); + + if (qn->rate != rate) { + ret = clk_set_rate(qicp->bus_clk, rate); + if (ret) { + pr_err("set clk rate %lld error %d\n", rate, ret); + return ret; + } + + ret = clk_set_rate(qicp->bus_a_clk, rate); + if (ret) { + pr_err("set clk rate %lld error %d\n", rate, ret); + return ret; + } + + qn->rate = rate; + } + + return ret; +} + +struct interconnect_onecell_data { + struct interconnect_node **nodes; + unsigned int num_nodes; +}; + +static const struct icp_ops qcom_ops = { + .set = qcom_interconnect_set, +}; + +static int qnoc_probe(struct platform_device *pdev) +{ + struct qcom_interconnect_provider *qicp; + struct icp *icp; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct resource *res; + void __iomem *base; + struct clk *bus_clk, *bus_a_clk; + size_t num_nodes, i; + const struct qcom_interconnect_desc *desc; + struct qcom_interconnect_node **qnodes; + struct interconnect_node *nodes; + struct interconnect_onecell_data *data; + u32 type, base_offset, qos_offset; + + desc = of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + qnodes = desc->nodes; + num_nodes = desc->num_nodes; + + qicp = devm_kzalloc(dev, sizeof(*qicp), GFP_KERNEL); + if (!qicp) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); + if (IS_ERR(bus_clk)) + return PTR_ERR(bus_clk); + bus_a_clk = devm_clk_get(&pdev->dev, "bus_a_clk"); + if (IS_ERR(bus_a_clk)) + return PTR_ERR(bus_a_clk); + + of_property_read_u32(np, "type", &type); + of_property_read_u32(np, "base-offset", &base_offset); + of_property_read_u32(np, "qos-offset", &qos_offset); + + qicp->base = base; + qicp->type = type; + qicp->base_offset = base_offset; + qicp->qos_offset = qos_offset; + qicp->bus_clk = bus_clk; + qicp->bus_a_clk = bus_a_clk; + icp = &qicp->icp; + icp->dev = dev; + icp->ops = &qcom_ops; + INIT_LIST_HEAD(&icp->nodes); + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + icp->data = data; + data->num_nodes = num_nodes; + + data->nodes = devm_kcalloc(dev, num_nodes, sizeof(*nodes), GFP_KERNEL); + if (!data->nodes) + return -ENOMEM; + + for (i = 0; i < num_nodes; i++) { + struct interconnect_node *node; + int ret; + size_t j; + + if (!qnodes[i]) + continue; + + node = &qnodes[i]->node; + node->dev_id = kstrdup_const(qnodes[i]->name, GFP_KERNEL); + node->con_id = qnodes[i]->id; + node->icp = icp; + node->num_links = qnodes[i]->num_links; + node->links = devm_kcalloc(dev, node->num_links, + sizeof(*node->links), GFP_KERNEL); + if (!node->links) + return -ENOMEM; + + /* populate links */ + for (j = 0; j < node->num_links; j++) + node->links[j] = qnodes[i]->links[j]; + + /* add node to interconnect provider */ + data->nodes[i] = node; + list_add_tail(&node->icn_list, &icp->nodes); + dev_dbg(&pdev->dev, "registered node %p %s %d\n", node, + node->dev_id, node->con_id); + + ret = qcom_interconnect_init(node); + if (ret) + dev_err(&pdev->dev, "node init error (%d)\n", ret); + } + + return interconnect_add_provider(icp); +} + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,msm-bus-pnoc", .data = &msm8916_pnoc }, + { .compatible = "qcom,msm-bus-snoc", .data = &msm8916_snoc }, + { .compatible = "qcom,msm-bus-bimc", .data = &msm8916_bimc }, + { }, +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qnoc_probe, + .driver = { + .name = "qcom,qnoc", + .of_match_table = qnoc_of_match, + }, +}; +module_platform_driver(qnoc_driver); +MODULE_AUTHOR("Georgi Djakov "); +MODULE_DESCRIPTION("Qualcomm msm8916 NoC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/interconnect/qcom-noc.h b/include/linux/interconnect/qcom-noc.h new file mode 100644 index 000000000000..355582a09bea --- /dev/null +++ b/include/linux/interconnect/qcom-noc.h @@ -0,0 +1,92 @@ +#ifndef __LINUX_INTERCONNECT_QCOM_NOC_H +#define __LINUX_INTERCONNECT_QCOM_NOC_H + +#define MAS_VIDEO 0 +#define MAS_JPEG 1 +#define MAS_VFE 2 +#define MAS_MDP 3 +#define MAS_QDSS_BAM 4 +#define MAS_SNOC_CFG 5 +#define MAS_QDSS_ETR 6 +#define MM_INT_0 7 +#define MM_INT_1 8 +#define MM_INT_2 9 +#define MM_INT_BIMC 10 +#define SNOC_INT_0 11 +#define SNOC_INT_1 12 +#define SNOC_INT_BIMC 13 +#define SNOC_BIMC_0_MAS 14 +#define SNOC_BIMC_1_MAS 15 +#define QDSS_INT 16 +#define BIMC_SNOC_SLV 17 +#define SNOC_PNOC_MAS 18 +#define PNOC_SNOC_SLV 19 +#define SLV_SRVC_SNOC 20 +#define SLV_QDSS_STM 21 +#define SLV_IMEM 22 +#define SLV_APSS 23 +#define SLV_CATS_0 24 +#define SLV_CATS_1 25 + +#define MAS_APPS 0 +#define MAS_TCU0 1 +#define MAS_TCU1 2 +#define MAS_GFX 3 +#define BIMC_SNOC_MAS 4 +#define SNOC_BIMC_0_SLV 5 +#define SNOC_BIMC_1_SLV 6 +#define SLV_EBI_CH0 7 +#define SLV_APPS_L2 8 + +#define SNOC_PNOC_SLV 0 +#define PNOC_INT_0 1 +#define PNOC_INT_1 2 +#define PNOC_M_0 3 +#define PNOC_M_1 4 +#define PNOC_S_0 5 +#define PNOC_S_1 6 +#define PNOC_S_2 7 +#define PNOC_S_3 8 +#define PNOC_S_4 9 +#define PNOC_S_8 10 +#define PNOC_S_9 11 +#define SLV_IMEM_CFG 12 +#define SLV_CRYPTO_0_CFG 13 +#define SLV_MSG_RAM 14 +#define SLV_PDM 15 +#define SLV_PRNG 16 +#define SLV_CLK_CTL 17 +#define SLV_MSS 18 +#define SLV_TLMM 19 +#define SLV_TCSR 20 +#define SLV_SECURITY 21 +#define SLV_SPDM 22 +#define SLV_PNOC_CFG 23 +#define SLV_PMIC_ARB 24 +#define SLV_BIMC_CFG 25 +#define SLV_BOOT_ROM 26 +#define SLV_MPM 27 +#define SLV_QDSS_CFG 28 +#define SLV_RBCPR_CFG 29 +#define SLV_SNOC_CFG 30 +#define SLV_DEHR_CFG 31 +#define SLV_VENUS_CFG 32 +#define SLV_DISPLAY_CFG 33 +#define SLV_CAMERA_CFG 34 +#define SLV_USB_HS 35 +#define SLV_SDCC_1 36 +#define SLV_BLSP_1 37 +#define SLV_SDCC_2 38 +#define SLV_GFX_CFG 39 +#define SLV_AUDIO 40 +#define MAS_BLSP_1 41 +#define MAS_SPDM 42 +#define MAS_DEHR 43 +#define MAS_AUDIO 44 +#define MAS_USB_HS 45 +#define MAS_PNOC_CRYPTO_0 46 +#define MAS_PNOC_SDCC_1 47 +#define MAS_PNOC_SDCC_2 48 +#define PNOC_SNOC_MAS 49 + +#endif