From patchwork Mon Jun 22 07:59:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 191309 Delivered-To: patch@linaro.org Received: by 2002:a92:1f07:0:0:0:0:0 with SMTP id i7csp817603ile; Mon, 22 Jun 2020 01:00:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwQA+7hd5WBjTxNLr41bMQiEzzOXtRIaWAkU6x8zVP6FZgC6s6lbqFiHnH4IOvV6JMGl0F8 X-Received: by 2002:a50:b964:: with SMTP id m91mr16510918ede.37.1592812806042; Mon, 22 Jun 2020 01:00:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592812806; cv=none; d=google.com; s=arc-20160816; b=XXjIIYk82n4MslgDpITgSG67p0/V8QEsk/snBaWmwZMAvieFMZ7+dkFRs2UNrplJ7A UTDk6nCJ594okhp4/xY+fvGu7QmfNHpwR4B0f/Fw7ciKVZ8XKQFi8aLY14kNQ+iCCcqw p8vXH7t5dk5B0QMU34rLSTuKUEVUha3DS8skKjIIc3IOTkWaJGK9zlGySqSQnG3VbDiD vSeeFaeA/1Fpkrqmu7o6y7LDOQ/ylqN1p72UA92oXYr8x4TNvJtjqyoFCCtSUN250vOo zEUnSipzo+Wls4ryxR7J7C33P49M+rObStES7oAKFOAcn5wThLeLQ9iSr+CX6LcXpjWY lzJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TTeC9Xi4qmQZeAOaphNZwsLRTSZ0LBevI66eeZFDnkA=; b=pJet0yQoZEmE9VmJDfX6Dsnqe/Ksn1ncpjayVTC8InhHibg048lfolUVwNBhbYVCGt bl075+DmG+NnXUxWrCQlmznFgh66Q/j+cMoJ1XPqYWjW0MCrBCIjx8fwZGPog7d/yMY0 /awoIVhNbzX9rSmrgw1IJDDhawdG5UEPMLRMJT3TtyFkB6oPd/Ia1pLJvhHVJHdDU1CO io6apXGI4Bct5rqYPVSTiaSfG8ya++TN9tcGCz+l/IhBl5BAt5zRVkHhMYNCy3y+Fg6e UBJ+WxvVhecgatJ+NICpZh5Fwqoqmb5vPbI0CSIsYcQsG1g8qrHHpo0RfGMhm/jvTEnT Uhxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XAYvSU8H; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id f7sm3135396otl.60.2020.06.22.00.59.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jun 2020 00:59:47 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Ohad Ben-Cohen , Baolin Wang , Rob Herring Cc: linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH v2 2/4] dt-bindings: hwlock: qcom: Allow device on mmio bus Date: Mon, 22 Jun 2020 00:59:54 -0700 Message-Id: <20200622075956.171058-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200622075956.171058-1-bjorn.andersson@linaro.org> References: <20200622075956.171058-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In modern Qualcomm platforms the mutex region of the TCSR is forked off into its own block, all with a offset of 0 and stride of 4096, and in some of these platforms no other registers in this region is accessed from Linux. Update the binding to allow the hardware block to be described directly on the mmio bus, in addition to allowing the existing syscon based definition for backwards compatibility. Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson --- Changes since v1: - None .../bindings/hwlock/qcom-hwspinlock.yaml | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) -- 2.26.2 diff --git a/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.yaml index 71e63b52edd5..88f975837588 100644 --- a/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.yaml +++ b/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.yaml @@ -19,6 +19,9 @@ properties: - qcom,sfpb-mutex - qcom,tcsr-mutex + reg: + maxItems: 1 + '#hwlock-cells': const: 1 @@ -31,7 +34,12 @@ properties: required: - compatible - '#hwlock-cells' - - syscon + +oneOf: + - required: + - reg + - required: + - syscon additionalProperties: false @@ -46,6 +54,12 @@ examples: compatible = "qcom,tcsr-mutex"; syscon = <&tcsr_mutex_block 0 0x80>; + #hwlock-cells = <1>; + }; + - | + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01f40000 0x40000>; #hwlock-cells = <1>; }; ... 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id f7sm3135396otl.60.2020.06.22.00.59.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jun 2020 00:59:49 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Ohad Ben-Cohen , Baolin Wang , Rob Herring Cc: linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH v2 3/4] hwspinlock: qcom: Allow mmio usage in addition to syscon Date: Mon, 22 Jun 2020 00:59:55 -0700 Message-Id: <20200622075956.171058-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200622075956.171058-1-bjorn.andersson@linaro.org> References: <20200622075956.171058-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In modern Qualcomm platforms the mutex region of the TCSR is forked off into its own block, all with a offset of 0 and stride of 4096, and in some of these platforms no other registers in this region is accessed from Linux. So add support for directly memory mapping this register space, to avoid the need to represent this block using a syscon. Reviewed-by: Baolin Wang Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson --- Changes since v1: - Use devm_platform_ioremap_resource() drivers/hwspinlock/qcom_hwspinlock.c | 70 +++++++++++++++++++++------- 1 file changed, 54 insertions(+), 16 deletions(-) -- 2.26.2 diff --git a/drivers/hwspinlock/qcom_hwspinlock.c b/drivers/hwspinlock/qcom_hwspinlock.c index f0da544b14d2..364710966665 100644 --- a/drivers/hwspinlock/qcom_hwspinlock.c +++ b/drivers/hwspinlock/qcom_hwspinlock.c @@ -70,41 +70,79 @@ static const struct of_device_id qcom_hwspinlock_of_match[] = { }; MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match); -static int qcom_hwspinlock_probe(struct platform_device *pdev) +static struct regmap *qcom_hwspinlock_probe_syscon(struct platform_device *pdev, + u32 *base, u32 *stride) { - struct hwspinlock_device *bank; struct device_node *syscon; - struct reg_field field; struct regmap *regmap; - size_t array_size; - u32 stride; - u32 base; int ret; - int i; syscon = of_parse_phandle(pdev->dev.of_node, "syscon", 0); - if (!syscon) { - dev_err(&pdev->dev, "no syscon property\n"); - return -ENODEV; - } + if (!syscon) + return ERR_PTR(-ENODEV); regmap = syscon_node_to_regmap(syscon); of_node_put(syscon); if (IS_ERR(regmap)) - return PTR_ERR(regmap); + return regmap; - ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, &base); + ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, base); if (ret < 0) { dev_err(&pdev->dev, "no offset in syscon\n"); - return -EINVAL; + return ERR_PTR(-EINVAL); } - ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, &stride); + ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, stride); if (ret < 0) { dev_err(&pdev->dev, "no stride syscon\n"); - return -EINVAL; + return ERR_PTR(-EINVAL); } + return regmap; +} + +static const struct regmap_config tcsr_mutex_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x40000, + .fast_io = true, +}; + +static struct regmap *qcom_hwspinlock_probe_mmio(struct platform_device *pdev, + u32 *offset, u32 *stride) +{ + struct device *dev = &pdev->dev; + void __iomem *base; + + /* All modern platform has offset 0 and stride of 4k */ + *offset = 0; + *stride = 0x1000; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return ERR_CAST(base); + + return devm_regmap_init_mmio(dev, base, &tcsr_mutex_config); +} + +static int qcom_hwspinlock_probe(struct platform_device *pdev) +{ + struct hwspinlock_device *bank; + struct reg_field field; + struct regmap *regmap; + size_t array_size; + u32 stride; + u32 base; + int i; + + regmap = qcom_hwspinlock_probe_syscon(pdev, &base, &stride); + if (IS_ERR(regmap) && PTR_ERR(regmap) == -ENODEV) + regmap = qcom_hwspinlock_probe_mmio(pdev, &base, &stride); + + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + array_size = QCOM_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock); bank = devm_kzalloc(&pdev->dev, sizeof(*bank) + array_size, GFP_KERNEL); if (!bank)