From patchwork Thu Jul 13 07:49:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 107568 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp1884539qge; Thu, 13 Jul 2017 00:51:58 -0700 (PDT) X-Received: by 10.99.56.21 with SMTP id f21mr7749565pga.235.1499932318054; Thu, 13 Jul 2017 00:51:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1499932318; cv=none; d=google.com; s=arc-20160816; b=fhWSZRgGFdjH7G3ZEDadApkk8p1SCPfKv9McOSbg8/VxSuZm9GRWMzwPK7IfM4MHZf oUeVtQmfmJn0ZHInossr/kgxukwU9aD+Ehv9kStbZdYnvmVwE+2H8/iIjOUXAz8USC78 3D2TQtaNp/WxHD19FhKC6OKFKBQWofjLN/McpgLrat/c0PpIeUXGJcta+Wx1/d2hNS/J 96+LkbGapjnXUZ1TM6O7pZx4Q0dgnONk/6BmsBhck5dYF//vKn0GEfNEer2gehrsOOFX LGoV4cMHh6CLy2p6cJgTKh7mYsE8C9jT221E0TU4xrrKMKXdY+skZCh1Asn9asNI1snf WjHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=Lpl1jg6iv+soDbtIrT0L8z6kjzt1PEOVGGO6zZl79v0=; b=c2UkYYMIHdxMP3bdOHnaNRNitcKi0g3EoT4j9JyNiNLMoMOqDRRYoVUaTlYAaMmVo1 JouuGAwBQsfgK6amJAxlrHVp9EEIBpGwBBOvl68orQiGQ6KNdNjPWDmmA1t4/0fiOiuR VD0tsq5vzr0oFtYEmQd6NnlYdZ5UjchNR/Q0w/N0b/ZuIGCvyMq85gnkH3BvyG+iMZRM GtVwVgS+sgOgxNSmkPdn/Uj42qJgc1p8DBLqPBBUBi+8TXRtOpcuBoW8izHHcChnayTP cITOutYOB+GkyM0tW2sJY84TlCfaLYCKN+HdRC8397WjSPmSPKjDKjObCjR22Sm5AVGn 8P2g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l1si3854429plb.356.2017.07.13.00.51.57; Thu, 13 Jul 2017 00:51:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751219AbdGMHvw (ORCPT + 7 others); Thu, 13 Jul 2017 03:51:52 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:48047 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751145AbdGMHtn (ORCPT ); Thu, 13 Jul 2017 03:49:43 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 2A47021FE0; Thu, 13 Jul 2017 09:49:40 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id B312E21FC7; Thu, 13 Jul 2017 09:49:39 +0200 (CEST) From: Quentin Schulz To: mturquette@baylibre.com, sboyd@codeaurora.org, robh+dt@kernel.org, mark.rutland@arm.com, lgirdwood@gmail.com, broonie@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@free-electrons.com, linux@armlinux.org.uk, boris.brezillon@free-electrons.com, perex@perex.cz, tiwai@suse.com Cc: Cyrille Pitchen , cyrille.pitchen@wedev4u.fr, thomas.petazzoni@free-electrons.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, linux-arm-kernel@lists.infradead.org, Nicolas Ferre , Quentin Schulz Subject: [PATCH v3 4/9] ARM: dts: at91: sama5d2: add classd nodes Date: Thu, 13 Jul 2017 09:49:22 +0200 Message-Id: <20170713074927.10882-5-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170713074927.10882-1-quentin.schulz@free-electrons.com> References: <20170713074927.10882-1-quentin.schulz@free-electrons.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Cyrille Pitchen This patch adds nodes for the classd device and its generated clock. Signed-off-by: Cyrille Pitchen Signed-off-by: Nicolas Ferre Signed-off-by: Quentin Schulz --- arch/arm/boot/dts/sama5d2.dtsi | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index cc06da394366..a564cd1ba327 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -494,6 +494,24 @@ clocks = <&plla>; }; + audio_pll_frac: audiopll_fracck { + compatible = "atmel,sama5d2-clk-audio-pll-frac"; + #clock-cells = <0>; + clocks = <&main>; + }; + + audio_pll_pad: audiopll_padck { + compatible = "atmel,sama5d2-clk-audio-pll-pad"; + #clock-cells = <0>; + clocks = <&audio_pll_frac>; + }; + + audio_pll_pmc: audiopll_pmcck { + compatible = "atmel,sama5d2-clk-audio-pll-pmc"; + #clock-cells = <0>; + clocks = <&audio_pll_frac>; + }; + utmi: utmick { compatible = "atmel,at91sam9x5-clk-utmi"; #clock-cells = <0>; @@ -895,7 +913,7 @@ #address-cells = <1>; #size-cells = <0>; interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>; sdmmc0_gclk: sdmmc0_gclk { #clock-cells = <0>; @@ -951,6 +969,12 @@ reg = <57>; atmel,clk-output-range = <0 80000000>; }; + + classd_gclk: classd_gclk { + #clock-cells = <0>; + reg = <59>; + atmel,clk-output-range = <0 100000000>; + }; }; }; @@ -1406,6 +1430,19 @@ status = "okay"; }; + classd: classd@fc048000 { + compatible = "atmel,sama5d2-classd"; + reg = <0xfc048000 0x100>; + interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(47))>; + dma-names = "tx"; + clocks = <&classd_clk>, <&classd_gclk>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + can1: can@fc050000 { compatible = "bosch,m_can"; reg = <0xfc050000 0x4000>, <0x210000 0x4000>;