From patchwork Mon Jan 20 16:30:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 190604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00E7EC33CAA for ; Mon, 20 Jan 2020 16:32:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CD78924656 for ; Mon, 20 Jan 2020 16:32:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="G2IagIBO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729324AbgATQci (ORCPT ); Mon, 20 Jan 2020 11:32:38 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:34989 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728842AbgATQau (ORCPT ); Mon, 20 Jan 2020 11:30:50 -0500 Received: by mail-wm1-f68.google.com with SMTP id p17so241373wmb.0 for ; Mon, 20 Jan 2020 08:30:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qsI/xaPXMqNdKm9K1igbwkE2PA4fRpWtUntr4tiEc9c=; b=G2IagIBOWzh/x16MmgeTD8wsIydKubQXPVKg1rv4Z4RR14LDQWt4zUhDU1HfrMHczS g2r9eRIVi4i/ydvfIil0I54FM5sMKiwf39RnsBZSyhht06aVtE2SnZ0ieVphedo49NHE jyM9X8ahmWECdxjbEEEKkrA8C6jqWVGjCx3+mWK3UP1CKmMc7ZJeoiUO+sWU5PGFXemw zpIi9XvkZfWSNzY6KYAnoZbZJ4XiUdOJl7/BKzSETmz/GahtWUPtDVdmLoNqDJwfDswp 38kre8EH+B9ShaUuYJ3dKFx96kX7u04ZL+AN6b+ayfcCPPkyHlf/ntH6qcrqH+/Dk+05 LwsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qsI/xaPXMqNdKm9K1igbwkE2PA4fRpWtUntr4tiEc9c=; b=N0/717UuzMdEypE/c3+pWKQGZ+R6Qy8mIFe1szNGF6IPN1VV0g8v4e3/Ykn+wKd2or rJ41GbY9EpQ7Z87nCwRVsx6dV3305HIJRbcVpjzSsuZ6es/SJXd3/fcIZhgc9HWLXAW5 CukqfXb1VKI+S2xQVm72U9+YW8Rs6sJO87MKTxwdwxDvlsZUqlSfTeUsG9HZ5ZG14iBg dhmdW5jHkh5/Rbc5p3+TC4HZR8CMH9IgaXlDAIxkYbE3VSQ2LVA0EZhrsFrdRN3u9gie NUsSc4yjC7l0GJkJ+bf3D79Dg3Y8dfCHC76v4C1VrYjYTKwaqdw8GXEjYVofN2ka1ADH Gi+A== X-Gm-Message-State: APjAAAXAvfInWoqBj1G+nb3tVj4I80wBZW+mVDvTEVRpDE6XKDrKmqSe PZoeVDPZPZVuetZe/XQ9d28VOvRZ5iU= X-Google-Smtp-Source: APXvYqzzFJTUL2uBj8UC6wtxz6N+1fzM94B2exU3q07GUKuUf2SDhArGvq1P2gzxo5nwlVOdim5jTg== X-Received: by 2002:a1c:22c6:: with SMTP id i189mr165624wmi.15.1579537847957; Mon, 20 Jan 2020 08:30:47 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id p26sm22631756wmc.24.2020.01.20.08.30.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2020 08:30:47 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Jorge Ramirez-Ortiz , Jorge Ramirez-Ortiz , Bryan O'Donoghue Subject: [PATCH v2 01/19] dt-bindings: phy: remove qcom-dwc3-usb-phy Date: Mon, 20 Jan 2020 16:30:58 +0000 Message-Id: <20200120163116.1197682-2-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> References: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jorge Ramirez-Ortiz This binding is not used by any driver. Signed-off-by: Jorge Ramirez-Ortiz Cc: Jorge Ramirez-Ortiz Signed-off-by: Bryan O'Donoghue --- .../bindings/phy/qcom-dwc3-usb-phy.txt | 37 ------------------- 1 file changed, 37 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt diff --git a/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt b/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt deleted file mode 100644 index a1697c27aecd..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt +++ /dev/null @@ -1,37 +0,0 @@ -Qualcomm DWC3 HS AND SS PHY CONTROLLER --------------------------------------- - -DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer -controllers. Each DWC3 PHY controller should have its own node. - -Required properties: -- compatible: should contain one of the following: - - "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller - - "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller -- reg: offset and length of the DWC3 PHY controller register set -- #phy-cells: must be zero -- clocks: a list of phandles and clock-specifier pairs, one for each entry in - clock-names. -- clock-names: Should contain "ref" for the PHY reference clock - -Optional clocks: - "xo" External reference clock - -Example: - phy@100f8800 { - compatible = "qcom,dwc3-hs-usb-phy"; - reg = <0x100f8800 0x30>; - clocks = <&gcc USB30_0_UTMI_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - }; - - phy@100f8830 { - compatible = "qcom,dwc3-ss-usb-phy"; - reg = <0x100f8830 0x30>; - clocks = <&gcc USB30_0_MASTER_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - }; From patchwork Mon Jan 20 16:30:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 190613 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E908C33CAA for ; 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Mon, 20 Jan 2020 08:30:49 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id p26sm22631756wmc.24.2020.01.20.08.30.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2020 08:30:48 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Sriharsha Allenki , Anu Ramanathan , Shawn Guo , Andy Gross , Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Jorge Ramirez-Ortiz , devicetree@vger.kernel.org, Bryan O'Donoghue Subject: [PATCH v2 02/19] dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY binding Date: Mon, 20 Jan 2020 16:30:59 +0000 Message-Id: <20200120163116.1197682-3-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> References: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sriharsha Allenki Adds bindings for QCS404 USB PHY supporting Low-Speed, Full-Speed and Hi-Speed USB connectivity on Qualcomm chipsets. [bod: Converted to YAML. Changed name dropping snps, 28nm components] Signed-off-by: Sriharsha Allenki Signed-off-by: Anu Ramanathan Signed-off-by: Bjorn Andersson Signed-off-by: Shawn Guo Cc: Andy Gross Cc: Bjorn Andersson Cc: Kishon Vijay Abraham I Cc: Rob Herring Cc: Mark Rutland Cc: Jorge Ramirez-Ortiz Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- .../bindings/phy/qcom,qcs404-usb-hs.yaml | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,qcs404-usb-hs.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs404-usb-hs.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs404-usb-hs.yaml new file mode 100644 index 000000000000..d71beb822ae2 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,qcs404-usb-hs.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,qcs404-usb-hs.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Synopsys QCS-404 High-Speed PHY + +maintainers: + - Bryan O'Donoghue + +description: | + Qualcomm QCS-404 Low-Speed, Full-Speed, Hi-Speed USB PHY + +properties: + compatible: + enum: + - qcom,qcs404-usb-hsphy + + reg: + maxItems: 1 + description: USB PHY base address and length of the register map. + + "#phy-cells": + const: 0 + description: Should be 0. See phy/phy-bindings.txt for details. + + clocks: + minItems: 3 + maxItems: 3 + description: phandles to rpmcc ref clock, PHY AHB clock, rentention clock. + + clock-names: + items: + - const: ref + - const: phy + - const: sleep + + resets: + items: + - description: PHY core reset + - description: POR reset + + reset-names: + items: + - const: phy + - const: por + + vdd-supply: + maxItems: 1 + description: phandle to the regulator VDD supply node. + + vdda1p8-supply: + maxItems: 1 + description: phandle to the regulator 1.8V supply node. + + vdda3p3-supply: + maxItems: 1 + description: phandle to the regulator 3.3V supply node. + +examples: + - | + #include + #include + usb2_phy_prim: phy@7a000 { + compatible = "qcom,qcs404-usb-hsphy"; + reg = <0x0007a000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "phy", "sleep"; + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&gcc GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + }; +... From patchwork Mon Jan 20 16:31:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 190605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF2A7C2D0DB for ; Mon, 20 Jan 2020 16:32:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B23D82087E for ; Mon, 20 Jan 2020 16:32:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="qcs9p5Jc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729402AbgATQa4 (ORCPT ); Mon, 20 Jan 2020 11:30:56 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:55514 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729190AbgATQax (ORCPT ); Mon, 20 Jan 2020 11:30:53 -0500 Received: by mail-wm1-f66.google.com with SMTP id q9so191153wmj.5 for ; Mon, 20 Jan 2020 08:30:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FIB8X4KTMSMav9IDv7FsBm+HOZtjyAZ9FH0A+hL6eL0=; b=qcs9p5JcmW2r+77XD45BXAYQtxkigFSgl6mx9RuivEMqEIOpfVKKWsQL5bStvnuFRO gLBxrPwmYXAtcr02lFZmcTcMN+OOEUhKZ7J1+COASDkcmIUA4YFifai+5AoW5LIiXXWS CZVRzOkV7by98h2Rbik5MzMGTUO/+zBBKZFvwjxjmwqtdIDfI8QIDnHOlgYwg58PkJl0 iReA5ENtLboXugSOHei3z3fDKeT1QrTDT8f+0sro3NZ7PIcEJ9PnuY6lAzr6DNuaGZw5 qXpOsB/kwaqMDWWFfIX3cXjYzuG4PunnD3Ee6biwrJMlizyhWomWJmk9WltMC8sjgoGo jxDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FIB8X4KTMSMav9IDv7FsBm+HOZtjyAZ9FH0A+hL6eL0=; b=sSyfElS2CtSXUd+T59ZKk1ltqya41JH6E2oX+G4qdwVQ62wlppKpHyVWBrTJiBzLU3 jLW3iuNEKEpJWJWugusr7YL1P4n87/BBt9JKkGpbV3+Y9Rkh2k9BCrNyrM+WU6hoIUL9 Cf5CU69dVvX5ekVyWnz0KqZEqX1EEb+ZaNQRYf7O4qlTv5T2Y5y+r9cF/6344mOZef7d oojeCXO8evEPsDvwdI/gZaTnD4F6F8WibWqtt0hpH8UJvD5hoh61aaoVxu2C1bYmtk0d wMwMGCT0gQ9BONi7czz6IyGejJ20XFmO2xJlm2FeLIyKh41oZIARuQDTtm7HQbar4TUr p/1Q== X-Gm-Message-State: APjAAAUqtf1Q/WkrqUaRcLMk3EyTrxsBFZdP2VKCGptFMiMXnWXgscsl bA9JkhUNr4k+bLL82JVM1WVPaSHe/yM= X-Google-Smtp-Source: APXvYqx3eoAWLsQGc56aB9fnyuVxlVv5VSmTrsS83u6ZCDRd9abn0bfAqIMD+LLyw2IkwuQNVMcyRQ== X-Received: by 2002:a1c:541b:: with SMTP id i27mr153340wmb.137.1579537850534; Mon, 20 Jan 2020 08:30:50 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id p26sm22631756wmc.24.2020.01.20.08.30.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2020 08:30:50 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Shawn Guo , Andy Gross , Kishon Vijay Abraham I , Philipp Zabel , Jorge Ramirez-Ortiz , Bryan O'Donoghue Subject: [PATCH v2 03/19] phy: qualcomm: Add Synopsys Hi-Speed USB PHY driver Date: Mon, 20 Jan 2020 16:31:00 +0000 Message-Id: <20200120163116.1197682-4-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> References: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Shawn Guo Adds Qualcomm QCS404 Hi-Speed USB PHY driver support. This PHY is usually is usually paired with Synopsys DWC3 USB controllers on Qualcomm SoCs. [bod: Updated qcom_snps_hsphy_set_mode to match new method signature Added disjunct on mode > 0 Removed regulator_set_voltage() in favour of setting floor in dts Removed 'snps' and '28nm' from driver name] Signed-off-by: Shawn Guo Cc: Andy Gross Cc: Bjorn Andersson Cc: Kishon Vijay Abraham I Cc: Philipp Zabel Cc: Jorge Ramirez-Ortiz Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- drivers/phy/qualcomm/Kconfig | 10 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-qcs404-usb-hs.c | 415 ++++++++++++++++++ 3 files changed, 426 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qcs404-usb-hs.c diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index e46824da29f6..cc3f2bb01ad1 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -91,3 +91,13 @@ config PHY_QCOM_USB_HSIC select GENERIC_PHY help Support for the USB HSIC ULPI compliant PHY on QCOM chipsets. + +config PHY_QCOM_QCS404_USB_HS + tristate "Qualcomm QCS404 Hi-Speed USB PHY driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in + select GENERIC_PHY + help + Enable this to support the Qualcomm QCS404 USB Hi-Speed PHY driver. + This driver supports the Hi-Speed PHY which is usually paired with + either the ChipIdea or Synopsys DWC3 USB IPs on MSM SOCs. diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index 283251d6a5d9..a4a3b21240fa 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-qcom-ufs-qmp-14nm.o obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o +obj-$(CONFIG_PHY_QCOM_QCS404_USB_HS) += phy-qcom-qcs404-usb-hs.o diff --git a/drivers/phy/qualcomm/phy-qcom-qcs404-usb-hs.c b/drivers/phy/qualcomm/phy-qcom-qcs404-usb-hs.c new file mode 100644 index 000000000000..0ea7c32941dd --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qcs404-usb-hs.c @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2009-2018, Linux Foundation. All rights reserved. + * Copyright (c) 2018-2020, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PHY register and bit definitions */ +#define PHY_CTRL_COMMON0 0x078 +#define SIDDQ BIT(2) +#define PHY_IRQ_CMD 0x0d0 +#define PHY_INTR_MASK0 0x0d4 +#define PHY_INTR_CLEAR0 0x0dc +#define DPDM_MASK 0x1e +#define DP_1_0 BIT(4) +#define DP_0_1 BIT(3) +#define DM_1_0 BIT(2) +#define DM_0_1 BIT(1) + +enum hsphy_voltage { + VOL_NONE, + VOL_MIN, + VOL_MAX, + VOL_NUM, +}; + +enum hsphy_vreg { + VDD, + VDDA_1P8, + VDDA_3P3, + VREG_NUM, +}; + +struct hsphy_init_seq { + int offset; + int val; + int delay; +}; + +struct hsphy_data { + const struct hsphy_init_seq *init_seq; + unsigned int init_seq_num; +}; + +struct hsphy_priv { + void __iomem *base; + struct clk_bulk_data *clks; + int num_clks; + struct reset_control *phy_reset; + struct reset_control *por_reset; + struct regulator_bulk_data vregs[VREG_NUM]; + const struct hsphy_data *data; + enum phy_mode mode; +}; + +static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + + priv->mode = PHY_MODE_INVALID; + + if (mode > 0) + priv->mode = mode; + + return 0; +} + +static void qcom_snps_hsphy_enable_hv_interrupts(struct hsphy_priv *priv) +{ + u32 val; + + /* Clear any existing interrupts before enabling the interrupts */ + val = readb(priv->base + PHY_INTR_CLEAR0); + val |= DPDM_MASK; + writeb(val, priv->base + PHY_INTR_CLEAR0); + + writeb(0x0, priv->base + PHY_IRQ_CMD); + usleep_range(200, 220); + writeb(0x1, priv->base + PHY_IRQ_CMD); + + /* Make sure the interrupts are cleared */ + usleep_range(200, 220); + + val = readb(priv->base + PHY_INTR_MASK0); + switch (priv->mode) { + case PHY_MODE_USB_HOST_HS: + case PHY_MODE_USB_HOST_FS: + case PHY_MODE_USB_DEVICE_HS: + case PHY_MODE_USB_DEVICE_FS: + val |= DP_1_0 | DM_0_1; + break; + case PHY_MODE_USB_HOST_LS: + case PHY_MODE_USB_DEVICE_LS: + val |= DP_0_1 | DM_1_0; + break; + default: + /* No device connected */ + val |= DP_0_1 | DM_0_1; + break; + } + writeb(val, priv->base + PHY_INTR_MASK0); +} + +static void qcom_snps_hsphy_disable_hv_interrupts(struct hsphy_priv *priv) +{ + u32 val; + + val = readb(priv->base + PHY_INTR_MASK0); + val &= ~DPDM_MASK; + writeb(val, priv->base + PHY_INTR_MASK0); + + /* Clear any pending interrupts */ + val = readb(priv->base + PHY_INTR_CLEAR0); + val |= DPDM_MASK; + writeb(val, priv->base + PHY_INTR_CLEAR0); + + writeb(0x0, priv->base + PHY_IRQ_CMD); + usleep_range(200, 220); + + writeb(0x1, priv->base + PHY_IRQ_CMD); + usleep_range(200, 220); +} + +static void qcom_snps_hsphy_enter_retention(struct hsphy_priv *priv) +{ + u32 val; + + val = readb(priv->base + PHY_CTRL_COMMON0); + val |= SIDDQ; + writeb(val, priv->base + PHY_CTRL_COMMON0); +} + +static void qcom_snps_hsphy_exit_retention(struct hsphy_priv *priv) +{ + u32 val; + + val = readb(priv->base + PHY_CTRL_COMMON0); + val &= ~SIDDQ; + writeb(val, priv->base + PHY_CTRL_COMMON0); +} + +static int qcom_snps_hsphy_power_on(struct phy *phy) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = regulator_bulk_enable(VREG_NUM, priv->vregs); + if (ret) + return ret; + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) + goto err_disable_regulator; + qcom_snps_hsphy_disable_hv_interrupts(priv); + qcom_snps_hsphy_exit_retention(priv); + + return 0; + +err_disable_regulator: + regulator_bulk_disable(VREG_NUM, priv->vregs); + + return ret; +} + +static int qcom_snps_hsphy_power_off(struct phy *phy) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + + qcom_snps_hsphy_enter_retention(priv); + qcom_snps_hsphy_enable_hv_interrupts(priv); + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + regulator_bulk_disable(VREG_NUM, priv->vregs); + + return 0; +} + +static int qcom_snps_hsphy_reset(struct hsphy_priv *priv) +{ + int ret; + + ret = reset_control_assert(priv->phy_reset); + if (ret) + return ret; + + usleep_range(10, 15); + + ret = reset_control_deassert(priv->phy_reset); + if (ret) + return ret; + + usleep_range(80, 100); + + return 0; +} + +static void qcom_snps_hsphy_init_sequence(struct hsphy_priv *priv) +{ + const struct hsphy_data *data = priv->data; + const struct hsphy_init_seq *seq; + int i; + + /* Device match data is optional. */ + if (!data) + return; + + seq = data->init_seq; + + for (i = 0; i < data->init_seq_num; i++, seq++) { + writeb(seq->val, priv->base + seq->offset); + if (seq->delay) + usleep_range(seq->delay, seq->delay + 10); + } +} + +static int qcom_snps_hsphy_por_reset(struct hsphy_priv *priv) +{ + int ret; + + ret = reset_control_assert(priv->por_reset); + if (ret) + return ret; + + /* + * The Femto PHY is POR reset in the following scenarios. + * + * 1. After overriding the parameter registers. + * 2. Low power mode exit from PHY retention. + * + * Ensure that SIDDQ is cleared before bringing the PHY + * out of reset. + */ + qcom_snps_hsphy_exit_retention(priv); + + /* + * As per databook, 10 usec delay is required between + * PHY POR assert and de-assert. + */ + usleep_range(10, 20); + ret = reset_control_deassert(priv->por_reset); + if (ret) + return ret; + + /* + * As per databook, it takes 75 usec for PHY to stabilize + * after the reset. + */ + usleep_range(80, 100); + + return 0; +} + +static int qcom_snps_hsphy_init(struct phy *phy) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = qcom_snps_hsphy_reset(priv); + if (ret) + return ret; + + qcom_snps_hsphy_init_sequence(priv); + + ret = qcom_snps_hsphy_por_reset(priv); + if (ret) + return ret; + + return 0; +} + +static const struct phy_ops qcom_snps_hsphy_ops = { + .init = qcom_snps_hsphy_init, + .power_on = qcom_snps_hsphy_power_on, + .power_off = qcom_snps_hsphy_power_off, + .set_mode = qcom_snps_hsphy_set_mode, + .owner = THIS_MODULE, +}; + +static const char * const qcom_snps_hsphy_clks[] = { + "ref", + "phy", + "sleep", +}; + +static int qcom_snps_hsphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *provider; + struct hsphy_priv *priv; + struct phy *phy; + int ret; + int i; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->num_clks = ARRAY_SIZE(qcom_snps_hsphy_clks); + priv->clks = devm_kcalloc(dev, priv->num_clks, sizeof(*priv->clks), + GFP_KERNEL); + if (!priv->clks) + return -ENOMEM; + + for (i = 0; i < priv->num_clks; i++) + priv->clks[i].id = qcom_snps_hsphy_clks[i]; + + ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks); + if (ret) + return ret; + + priv->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); + if (IS_ERR(priv->phy_reset)) + return PTR_ERR(priv->phy_reset); + + priv->por_reset = devm_reset_control_get_exclusive(dev, "por"); + if (IS_ERR(priv->por_reset)) + return PTR_ERR(priv->por_reset); + + priv->vregs[VDD].supply = "vdd"; + priv->vregs[VDDA_1P8].supply = "vdda1p8"; + priv->vregs[VDDA_3P3].supply = "vdda3p3"; + + ret = devm_regulator_bulk_get(dev, VREG_NUM, priv->vregs); + if (ret) + return ret; + + /* Get device match data */ + priv->data = device_get_match_data(dev); + + phy = devm_phy_create(dev, dev->of_node, &qcom_snps_hsphy_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + phy_set_drvdata(phy, priv); + + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(provider)) + return PTR_ERR(provider); + + ret = regulator_set_load(priv->vregs[VDDA_1P8].consumer, 19000); + if (ret < 0) + return ret; + + ret = regulator_set_load(priv->vregs[VDDA_3P3].consumer, 16000); + if (ret < 0) + goto unset_1p8_load; + + return 0; + +unset_1p8_load: + regulator_set_load(priv->vregs[VDDA_1P8].consumer, 0); + + return ret; +} + +/* + * The macro is used to define an initialization sequence. Each tuple + * is meant to program 'value' into phy register at 'offset' with 'delay' + * in us followed. + */ +#define HSPHY_INIT_CFG(o, v, d) { .offset = o, .val = v, .delay = d, } + +static const struct hsphy_init_seq init_seq_qcs404[] = { + HSPHY_INIT_CFG(0xc0, 0x01, 0), + HSPHY_INIT_CFG(0xe8, 0x0d, 0), + HSPHY_INIT_CFG(0x74, 0x12, 0), + HSPHY_INIT_CFG(0x98, 0x63, 0), + HSPHY_INIT_CFG(0x9c, 0x03, 0), + HSPHY_INIT_CFG(0xa0, 0x1d, 0), + HSPHY_INIT_CFG(0xa4, 0x03, 0), + HSPHY_INIT_CFG(0x8c, 0x23, 0), + HSPHY_INIT_CFG(0x78, 0x08, 0), + HSPHY_INIT_CFG(0x7c, 0xdc, 0), + HSPHY_INIT_CFG(0x90, 0xe0, 20), + HSPHY_INIT_CFG(0x74, 0x10, 0), + HSPHY_INIT_CFG(0x90, 0x60, 0), +}; + +static const struct hsphy_data hsphy_data_qcs404 = { + .init_seq = init_seq_qcs404, + .init_seq_num = ARRAY_SIZE(init_seq_qcs404), +}; + +static const struct of_device_id qcom_snps_hsphy_match[] = { + { .compatible = "qcom,qcs404-usb-hsphy", .data = &hsphy_data_qcs404, }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_match); + +static struct platform_driver qcom_snps_hsphy_driver = { + .probe = qcom_snps_hsphy_probe, + .driver = { + .name = "qcom-qcs404-usb-hsphy", + .of_match_table = qcom_snps_hsphy_match, + }, +}; +module_platform_driver(qcom_snps_hsphy_driver); + +MODULE_DESCRIPTION("Qualcomm QCS404 Hi-Speed USB PHY driver"); +MODULE_LICENSE("GPL v2"); From patchwork Mon Jan 20 16:31:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 190612 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 627A9C33CB8 for ; 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Mon, 20 Jan 2020 08:30:56 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id p26sm22631756wmc.24.2020.01.20.08.30.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2020 08:30:55 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Yu Chen , Rob Herring , Mark Rutland , ShuFan Lee , Heikki Krogerus , Suzuki K Poulose , Chunfeng Yun , Hans de Goede , Andy Shevchenko , Jun Li , Valentin Schneider , devicetree@vger.kernel.org, John Stultz , Bryan O'Donoghue Subject: [PATCH v2 07/19] usb: dwc3: Registering a role switch in the DRD code. Date: Mon, 20 Jan 2020 16:31:04 +0000 Message-Id: <20200120163116.1197682-8-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> References: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Yu Chen The Type-C drivers use USB role switch API to inform the system about the negotiated data role, so registering a role switch in the DRD code in order to support platforms with USB Type-C connectors. Cc: Greg Kroah-Hartman Cc: Rob Herring Cc: Mark Rutland CC: ShuFan Lee Cc: Heikki Krogerus Cc: Suzuki K Poulose Cc: Chunfeng Yun Cc: Yu Chen Cc: Felipe Balbi Cc: Hans de Goede Cc: Andy Shevchenko Cc: Jun Li Cc: Valentin Schneider Cc: Jack Pham Cc: linux-usb@vger.kernel.org Cc: devicetree@vger.kernel.org Suggested-by: Heikki Krogerus Signed-off-by: Yu Chen Signed-off-by: John Stultz Signed-off-by: Bryan O'Donoghue --- drivers/usb/dwc3/core.h | 3 ++ drivers/usb/dwc3/drd.c | 77 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 79 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 77c4a9abe365..a99e57636172 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -953,6 +954,7 @@ struct dwc3_scratchpad_array { * @hsphy_mode: UTMI phy mode, one of following: * - USBPHY_INTERFACE_MODE_UTMI * - USBPHY_INTERFACE_MODE_UTMIW + * @role_sw: usb_role_switch handle * @usb2_phy: pointer to USB2 PHY * @usb3_phy: pointer to USB3 PHY * @usb2_generic_phy: pointer to USB2 PHY @@ -1086,6 +1088,7 @@ struct dwc3 { struct extcon_dev *edev; struct notifier_block edev_nb; enum usb_phy_interface hsphy_mode; + struct usb_role_switch *role_sw; u32 fladj; u32 irq_gadget; diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c index c946d64142ad..3b57d2ddda93 100644 --- a/drivers/usb/dwc3/drd.c +++ b/drivers/usb/dwc3/drd.c @@ -476,6 +476,73 @@ static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) return edev; } +#ifdef CONFIG_USB_ROLE_SWITCH +#define ROLE_SWITCH 1 +static int dwc3_usb_role_switch_set(struct device *dev, enum usb_role role) +{ + struct dwc3 *dwc = dev_get_drvdata(dev); + u32 mode; + + switch (role) { + case USB_ROLE_HOST: + mode = DWC3_GCTL_PRTCAP_HOST; + break; + case USB_ROLE_DEVICE: + mode = DWC3_GCTL_PRTCAP_DEVICE; + break; + default: + mode = DWC3_GCTL_PRTCAP_DEVICE; + break; + } + + dwc3_set_mode(dwc, mode); + return 0; +} + +static enum usb_role dwc3_usb_role_switch_get(struct device *dev) +{ + struct dwc3 *dwc = dev_get_drvdata(dev); + unsigned long flags; + enum usb_role role; + + spin_lock_irqsave(&dwc->lock, flags); + switch (dwc->current_dr_role) { + case DWC3_GCTL_PRTCAP_HOST: + role = USB_ROLE_HOST; + break; + case DWC3_GCTL_PRTCAP_DEVICE: + role = USB_ROLE_DEVICE; + break; + case DWC3_GCTL_PRTCAP_OTG: + role = dwc->current_otg_role; + break; + default: + role = USB_ROLE_DEVICE; + break; + } + spin_unlock_irqrestore(&dwc->lock, flags); + return role; +} + +static int dwc3_setup_role_switch(struct dwc3 *dwc) +{ + struct usb_role_switch_desc dwc3_role_switch = {NULL}; + + dwc3_role_switch.fwnode = dev_fwnode(dwc->dev); + dwc3_role_switch.set = dwc3_usb_role_switch_set; + dwc3_role_switch.get = dwc3_usb_role_switch_get; + dwc->role_sw = usb_role_switch_register(dwc->dev, &dwc3_role_switch); + if (IS_ERR(dwc->role_sw)) + return PTR_ERR(dwc->role_sw); + + dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); + return 0; +} +#else +#define ROLE_SWITCH 0 +#define dwc3_setup_role_switch(x) 0 +#endif + int dwc3_drd_init(struct dwc3 *dwc) { int ret, irq; @@ -484,7 +551,12 @@ int dwc3_drd_init(struct dwc3 *dwc) if (IS_ERR(dwc->edev)) return PTR_ERR(dwc->edev); - if (dwc->edev) { + if (ROLE_SWITCH && + device_property_read_bool(dwc->dev, "usb-role-switch")) { + ret = dwc3_setup_role_switch(dwc); + if (ret < 0) + return ret; + } else if (dwc->edev) { dwc->edev_nb.notifier_call = dwc3_drd_notifier; ret = extcon_register_notifier(dwc->edev, EXTCON_USB_HOST, &dwc->edev_nb); @@ -531,6 +603,9 @@ void dwc3_drd_exit(struct dwc3 *dwc) { unsigned long flags; + if (dwc->role_sw) + usb_role_switch_unregister(dwc->role_sw); + if (dwc->edev) extcon_unregister_notifier(dwc->edev, EXTCON_USB_HOST, &dwc->edev_nb); From patchwork Mon Jan 20 16:31:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 190606 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7515FC33CAA for ; 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Mon, 20 Jan 2020 08:30:57 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id p26sm22631756wmc.24.2020.01.20.08.30.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2020 08:30:56 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, John Stultz , Rob Herring , Mark Rutland , ShuFan Lee , Heikki Krogerus , Suzuki K Poulose , Chunfeng Yun , Yu Chen , Hans de Goede , Andy Shevchenko , Jun Li , Valentin Schneider , devicetree@vger.kernel.org, Rob Herring , Bryan O'Donoghue Subject: [PATCH v2 08/19] dt-bindings: usb: generic: Add role-switch-default-mode binding Date: Mon, 20 Jan 2020 16:31:05 +0000 Message-Id: <20200120163116.1197682-9-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> References: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: John Stultz Add binding to configure the default role the controller assumes is host mode when the usb role is USB_ROLE_NONE. Cc: Greg Kroah-Hartman Cc: Rob Herring Cc: Mark Rutland CC: ShuFan Lee Cc: Heikki Krogerus Cc: Suzuki K Poulose Cc: Chunfeng Yun Cc: Yu Chen Cc: Felipe Balbi Cc: Hans de Goede Cc: Andy Shevchenko Cc: Jun Li Cc: Valentin Schneider Cc: Jack Pham Cc: linux-usb@vger.kernel.org Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: John Stultz Signed-off-by: Bryan O'Donoghue --- Documentation/devicetree/bindings/usb/generic.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/generic.txt b/Documentation/devicetree/bindings/usb/generic.txt index cf5a1ad456e6..dd733fa81fad 100644 --- a/Documentation/devicetree/bindings/usb/generic.txt +++ b/Documentation/devicetree/bindings/usb/generic.txt @@ -34,6 +34,12 @@ Optional properties: the USB data role (USB host or USB device) for a given USB connector, such as Type-C, Type-B(micro). see connector/usb-connector.txt. + - role-switch-default-mode: indicating if usb-role-switch is enabled, the + device default operation mode of controller while usb + role is USB_ROLE_NONE. Valid arguments are "host" and + "peripheral". Defaults to "peripheral" if not + specified. + This is an attribute to a USB controller such as: From patchwork Mon Jan 20 16:31:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 190607 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98DD9C33CAA for ; Mon, 20 Jan 2020 16:32:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6EEFA22527 for ; Mon, 20 Jan 2020 16:32:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="B/hlEJlT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729516AbgATQcD (ORCPT ); Mon, 20 Jan 2020 11:32:03 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:34158 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729462AbgATQbC (ORCPT ); Mon, 20 Jan 2020 11:31:02 -0500 Received: by mail-wr1-f65.google.com with SMTP id t2so133229wrr.1 for ; Mon, 20 Jan 2020 08:31:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=q0F3sFz0+h3FHMff0QjQ0SHaRu2x6ApQiXqi+8cwCoc=; b=B/hlEJlTL+fIjLXMxKm3nVoYjnT4XT5RXh4Fr/mW9OuLB4LHCwI0SgJmzOo2Xb9RcI ManBCVKlAOW/t3qYFFZWNYjcv7t2lK95GsZ9YW60qHQ4netbjr3LLyD6EnXvFhPsfdAy FUbUeMPkXIYRSsKkKa9qZ/G5d8bq3VK43txAwJT0tu4agoIQmBjE7LTfc1KpXwgPwrZ1 naJtf1gYVc1u5vbY5qtMmukR/pSdLJMBfQmSk3fhcFz42IBsmX9VXB9QELxFZIK3BehO HMmxb8KNcdH7NaQi4H33/1YYo8AdC6/SWwE6AEE+MTIjhVnnfyftxViXoWWcGibDS3TJ CiKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q0F3sFz0+h3FHMff0QjQ0SHaRu2x6ApQiXqi+8cwCoc=; b=kXPTSWBglTkYwEbsc8Pg4JUjITWdBfciSsj6+NHo2+1EQ+0J8w5Ls2+gBSyfi88XIx hm0OO14Mx0obiVudal1gcO77ncchrtlUrpJHv2Tkmz3tcmv82db9uoZTgUCkh6Z+uGdA 3fP486BCZfbYrOZ9MfipSzMsGADObfUWZy1Cifa1vrq5fZQPuozxU8DEzBypj71dDHs5 8mLlPZ65w2J4GTE480jL8AriZee9cmsNXH//xg5EO3RbKc7+bFm9lFdKVA5/5B5oeure 5J4DPrxuL1ytq291yKGousKAzjBvQMVYt4nDlIiVSAFhkEFR4c8zCLqqL+FbK3wa9TBb /sow== X-Gm-Message-State: APjAAAX0nU0VMGS3/Mbw867dZ5fr9CrNzkyuIKYAgkfm6jupXi4mXkyT HTzR2EBHEM4q8lZAYCY49p7Dsxw2Vwg= X-Google-Smtp-Source: APXvYqyNOqDmnv+8BSB1QXFOi3u33eA+uNslImQyu/Uo/GPAvsDSs41AmYIyKFKLifk+xQD6vA/j0g== X-Received: by 2002:adf:dc86:: with SMTP id r6mr371782wrj.68.1579537860898; Mon, 20 Jan 2020 08:31:00 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id p26sm22631756wmc.24.2020.01.20.08.30.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2020 08:31:00 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Bryan O'Donoghue , John Stultz , Lee Jones , Rob Herring , Mark Rutland , ShuFan Lee , Heikki Krogerus , Suzuki K Poulose , Chunfeng Yun , Yu Chen , Hans de Goede , Andy Shevchenko , Jun Li , Valentin Schneider , devicetree@vger.kernel.org Subject: [PATCH v2 11/19] usb: dwc3: Add support for usb-conn-gpio connectors Date: Mon, 20 Jan 2020 16:31:08 +0000 Message-Id: <20200120163116.1197682-12-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> References: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch adds the ability to probe and enumerate a connector based on usb-conn-gpio. A device node label gpio_usb_connector is used to identify a usb-conn-gpio as a child of the USB interface. You would use usb-conn-gpio when a regulator in your system provides VBUS directly to the connector instead of supplying via the USB PHY. The parent device must have the "usb-role-switch" property, so that when the usb-conn-gpio driver calls usb_role_switch_set_role() the notification in dwc3 will run and the block registers will be updated to match the state detected at the connector. Cc: John Stultz Cc: Bjorn Andersson Cc: Lee Jones Cc: Greg Kroah-Hartman Cc: Rob Herring Cc: Mark Rutland CC: ShuFan Lee Cc: Heikki Krogerus Cc: Suzuki K Poulose Cc: Chunfeng Yun Cc: Yu Chen Cc: Felipe Balbi Cc: Hans de Goede Cc: Andy Shevchenko Cc: Jun Li Cc: Valentin Schneider Cc: Jack Pham Cc: linux-usb@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- drivers/usb/dwc3/drd.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c index 865341facece..c6bb7cb809d5 100644 --- a/drivers/usb/dwc3/drd.c +++ b/drivers/usb/dwc3/drd.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "debug.h" #include "core.h" @@ -557,9 +558,32 @@ static int dwc3_setup_role_switch(struct dwc3 *dwc) dwc3_set_mode(dwc, mode); return 0; } + +static int dwc3_register_gpio_usb_connector(struct dwc3 *dwc) +{ + struct device *dev = dwc->dev; + struct device_node *np = dev->of_node, *con_np; + int ret; + + con_np = of_get_child_by_name(np, "gpio_usb_connector"); + if (!np) { + dev_dbg(dev, "no usb_connector child node specified\n"); + return 0; + } + + ret = of_platform_populate(np, NULL, NULL, dev); + if (ret) { + dev_err(dev, "failed to register usb_connector - %d\n", ret); + return ret; + } + + return 0; +} + #else #define ROLE_SWITCH 0 #define dwc3_setup_role_switch(x) 0 +#define dwc3_register_gpio_usb_connector(x) 0 #endif int dwc3_drd_init(struct dwc3 *dwc) @@ -575,6 +599,9 @@ int dwc3_drd_init(struct dwc3 *dwc) ret = dwc3_setup_role_switch(dwc); if (ret < 0) return ret; + ret = dwc3_register_gpio_usb_connector(dwc); + if (ret < 0) + return ret; } else if (dwc->edev) { dwc->edev_nb.notifier_call = dwc3_drd_notifier; ret = extcon_register_notifier(dwc->edev, EXTCON_USB_HOST, From patchwork Mon Jan 20 16:31:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 190608 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC743C2D0DB for ; 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Mon, 20 Jan 2020 08:31:02 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id p26sm22631756wmc.24.2020.01.20.08.31.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2020 08:31:01 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Vinod Koul , Shawn Guo , Andy Gross , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, Bryan O'Donoghue Subject: [PATCH v2 12/19] arm64: dts: qcom: qcs404: Add USB devices and PHYs Date: Mon, 20 Jan 2020 16:31:09 +0000 Message-Id: <20200120163116.1197682-13-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> References: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bjorn Andersson QCS404 sports HS and SS USB controllers based on dwc3 block with two HS PHYs and one SS PHY. Add nodes for these devices and enable them for EVB board. Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Shawn Guo Cc: Andy Gross Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 100 +++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index f5f0c4c9cb16..73565a5b99d1 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -272,6 +272,48 @@ rpm_msg_ram: memory@60000 { reg = <0x00060000 0x6000>; }; + usb3_phy: phy@78000 { + compatible = "qcom,usb-ssphy"; + reg = <0x00078000 0x400>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref", "phy", "pipe"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + status = "disabled"; + }; + + usb2_phy_prim: phy@7a000 { + compatible = "qcom,qcs404-usb-hsphy"; + reg = <0x0007a000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "phy", "sleep"; + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&gcc GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + + usb2_phy_sec: phy@7c000 { + compatible = "qcom,qcs404-usb-hsphy"; + reg = <0x0007c000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "phy", "sleep"; + resets = <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + qfprom: qfprom@a4000 { compatible = "qcom,qfprom"; reg = <0x000a4000 0x1000>; @@ -379,6 +421,64 @@ glink-edge { }; }; + usb3: usb@7678800 { + compatible = "qcom,dwc3"; + reg = <0x07678800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + status = "disabled"; + + dwc3@7580000 { + compatible = "snps,dwc3"; + reg = <0x07580000 0xcd00>; + interrupts = ; + phys = <&usb2_phy_sec>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + dr_mode = "otg"; + }; + }; + + usb2: usb@79b8800 { + compatible = "qcom,dwc3"; + reg = <0x079b8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, + <&gcc GCC_PCNOC_USB2_CLK>, + <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + status = "disabled"; + + dwc3@78c0000 { + compatible = "snps,dwc3"; + reg = <0x078c0000 0xcc00>; + interrupts = ; + phys = <&usb2_phy_prim>; + phy-names = "usb2-phy"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + dr_mode = "peripheral"; + }; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,qcs404-pinctrl"; reg = <0x01000000 0x200000>, From patchwork Mon Jan 20 16:31:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 190609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 267D2C33CA1 for ; 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Mon, 20 Jan 2020 08:31:06 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id p26sm22631756wmc.24.2020.01.20.08.31.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2020 08:31:05 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Bryan O'Donoghue , Andy Gross , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v2 16/19] arm64: dts: qcom: qcs404-evb: Describe external VBUS regulator Date: Mon, 20 Jan 2020 16:31:13 +0000 Message-Id: <20200120163116.1197682-17-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> References: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org VBUS is supplied by an external regulator controlled by a GPIO pin. This patch models the regulator as regulator-usb3-vbus. Cc: Andy Gross Cc: Bjorn Andersson Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index abfb2a9a37e9..01ef59e8e5b7 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -33,6 +33,18 @@ vdd_esmps3_3p3: vdd-esmps3-3p3-regulator { regulator-max-microvolt = <3300000>; regulator-always-on; }; + + usb3_vbus_reg: regulator-usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "VBUS_BOOST_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_vbus_boost_pin>; + vin-supply = <&vph_pwr>; + enable-active-high; + }; }; &blsp1_uart3 { From patchwork Mon Jan 20 16:31:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 190610 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6621CC2D0DB for ; Mon, 20 Jan 2020 16:31:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3CA7722314 for ; Mon, 20 Jan 2020 16:31:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="KrTOAFoS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729108AbgATQbk (ORCPT ); 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Mon, 20 Jan 2020 08:31:06 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Bryan O'Donoghue , Andy Gross , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v2 17/19] arm64: dts: qcom: qcs404-evb: Raise vreg_l12_3p3 minimum voltage Date: Mon, 20 Jan 2020 16:31:14 +0000 Message-Id: <20200120163116.1197682-18-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> References: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rather than set the minimum microvolt for this regulator in the USB SS PHY driver, set it in the DTS. Suggested-by: Bjorn Andersson Cc: Andy Gross Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 01ef59e8e5b7..0fff50f755ef 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -199,7 +199,7 @@ vreg_l11_sdc2: l11 { }; vreg_l12_3p3: l12 { - regulator-min-microvolt = <2968000>; + regulator-min-microvolt = <3050000>; regulator-max-microvolt = <3300000>; }; From patchwork Mon Jan 20 16:31:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 190611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0F1AC33CA1 for ; Mon, 20 Jan 2020 16:31:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 78EC324125 for ; Mon, 20 Jan 2020 16:31:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LhOTSKfy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729588AbgATQbL (ORCPT ); Mon, 20 Jan 2020 11:31:11 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:40201 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729616AbgATQbK (ORCPT ); Mon, 20 Jan 2020 11:31:10 -0500 Received: by mail-wr1-f67.google.com with SMTP id c14so85814wrn.7 for ; Mon, 20 Jan 2020 08:31:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LUSoU/XhVbuFFL332MrsGCHzak9+7MGgmls9JTYC/Cw=; b=LhOTSKfyxGu3QzNqPFlliI+E+JTZs7hl2ag76/1M4qOSHfq42vXcYje+r3VACQUqrv OA14VXRHnGA6xSd8TH/hySb60jJHoKlVYDrGuHwkfE8yV07+BfZx9/+7WEdoeZksxg32 IVZrSp6tkYItg31aYaLazuFk1KpjXqwYIlZkHWRGiNi36Oj7E+PBFpZBc/NMohFfxwcE CNmLEi2YVRpEA7IvbWqNdltO29jS+7z+Vp4MuYahgS37ZpKb7mBMfD7Lsi5lcut5J2Ne PFlESpL04Dst9VVWkPKKgm2IzDYm6aqm1wvH5jj9MFQAr+1MMjoTWdJZ+u6I/xxgEWR8 EKGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LUSoU/XhVbuFFL332MrsGCHzak9+7MGgmls9JTYC/Cw=; b=WQBJ8JTbrBLoiaX9IiGWECghI0Ol7dAhWU67Olt5w+ACb7zlNZgLK9G+pR/XOw3hKg Qb18kR+sHpFM+BOqn4xX0JtT5TGrBP5Mctr/GUSEHYt7MxSIEo1+KWx88FgWZfMBp23V 1FqBTeIpCi3a/cVQ3bwAeDqKRlu8rQdfWGG3Dhs7ti6gvNLCfRzgBM8NbnlgsvVcrTuq StlnMnvMBDH6b5GyYD6MK/nyCe/INerVZdSpy4cIsh0iaIQ/7uxK18SL3onWL9tCmHHk Zq6eFqlaC7yLu3zvsyLIAoaTFgd8EiCG6uRD4llBvxF8fH/f8tBZn8ErZ3QaoxQAbpIR zSBw== X-Gm-Message-State: APjAAAVwpOSkmM8OgamGILLakUvCiWDmA18A79ngnS89CF2tb9jfK1L0 zRb2A+uzFfOCAD5uRDXi9vgWXsErnGo= X-Google-Smtp-Source: APXvYqzh7+KwjH0AIYADBk8ipLPpoqsbpCKHss8cKke6kclzqR1hmQ5ry7k/jdlbdpit8NlVbn8tew== X-Received: by 2002:adf:cd92:: with SMTP id q18mr289882wrj.261.1579537868525; Mon, 20 Jan 2020 08:31:08 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id p26sm22631756wmc.24.2020.01.20.08.31.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2020 08:31:07 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Bryan O'Donoghue , Andy Gross , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v2 18/19] arm64: dts: qcom: qcs404-evb: Enable secondary USB controller Date: Mon, 20 Jan 2020 16:31:15 +0000 Message-Id: <20200120163116.1197682-19-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> References: <20200120163116.1197682-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch enables the second DWC3 controller which has one USB Hi-Speed PHY attached to it. Cc: Andy Gross Cc: Bjorn Andersson Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 0fff50f755ef..07d6d793a922 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -318,6 +318,17 @@ pinconf { }; }; +&usb2 { + status = "okay"; +}; + +&usb2_phy_sec { + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + status = "okay"; +}; + &wifi { status = "okay"; vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>;