From patchwork Wed Mar 11 19:13:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 190026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE38AC5ACC2 for ; Wed, 11 Mar 2020 19:14:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B06AA2074B for ; Wed, 11 Mar 2020 19:14:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Ay+QlVEB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731103AbgCKTO0 (ORCPT ); Wed, 11 Mar 2020 15:14:26 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:45713 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731083AbgCKTOE (ORCPT ); Wed, 11 Mar 2020 15:14:04 -0400 Received: by mail-wr1-f66.google.com with SMTP id m9so4087639wro.12 for ; Wed, 11 Mar 2020 12:14:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6TXvp/hgnbBEE+3PAwbtcQCr5QoU1b6s07axWH6/RUg=; b=Ay+QlVEBOL/0e7o+/gvQhcRxio+sMll2rHA1eD7ibml+VDLdgYphOUtH/iQ5bNtYww ClYokrdzFRv06VwEVYaigLIOSN17CKOHTB8AGg3XztYci4bEUYotC2ErvhjPbO7j3Jzx EuaNL5uzTnoPrNSraPlyX/VkhY3EGSC/h6+CupI3+w9orewwJTclni2BGDwGjltQ7Mzt dCBUxvU1HHjxC6cDL3odRauXpTPxc/bxSLCkflmeZA074Lv6HgmyLENMX+5maInPzKRI 0P7leVsOl/6ZPMYqO3pAtpLy3I4wopkX6flmHn//a/tHSs6dhAC6sEp/YAIUuavR/lBP Z6dA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6TXvp/hgnbBEE+3PAwbtcQCr5QoU1b6s07axWH6/RUg=; b=s50YW91j/K1NSpwE7Yc5b2DAw2fu36XxpdVtWssFDx8wXm4K4AqphdxwFx1cAGDdpy Nug8ZVQAurP+Ifpf2B4vKi5F+Q8ma1lCmbBqZ6JDy/Cz2dDxEGbEnUvUP6V1amBntgX1 H8ow9NqOHA6RrEb/BH6QHuqRAXhw5XM1Cz4q/ivTZ8t1l/z/GCOLvvCkrCg41VS3l8Rl hzhP5vArqsNhJgCAVq6GZkMeCyjWFXcyuY/HYjN1m24AI85LiT2c/gm31C9RlVIY4Sd6 723GgZXEM131fFAdJUNNcq1IvPoSAUVSr3XKq7ttJ6CnMeyFR8jLuaHGu4ixvz70L+Bj hBKQ== X-Gm-Message-State: ANhLgQ23AWQpQKeWemCytZWIZVmIQt+faliV7o+XAk1g+5X4J4KA45kO gNiG/gTAeJx6zwaezZGJB8iMPg== X-Google-Smtp-Source: ADFU+vsbEv2tuX+E1jYdkMH5f0uMwjyU8P2rDau6VWAyG7B1QlgLDIYBiQajaZazh3TacboViVryFA== X-Received: by 2002:adf:f2ca:: with SMTP id d10mr6207510wrp.247.1583954041879; Wed, 11 Mar 2020 12:14:01 -0700 (PDT) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id v8sm69443919wrw.2.2020.03.11.12.14.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2020 12:14:01 -0700 (PDT) From: Bryan O'Donoghue To: kishon@ti.com Cc: linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-msm@vger.kernel.org, jackp@codeaurora.org, robh@kernel.org, bjorn.andersson@linaro.org, p.zabel@pengutronix.de, Sriharsha Allenki , Anu Ramanathan , Shawn Guo , Andy Gross , Rob Herring , Mark Rutland , Jorge Ramirez-Ortiz , devicetree@vger.kernel.org, Bryan O'Donoghue Subject: [PATCH 2/5] dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY binding Date: Wed, 11 Mar 2020 19:13:55 +0000 Message-Id: <20200311191358.8102-3-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200311191358.8102-1-bryan.odonoghue@linaro.org> References: <20200311191358.8102-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sriharsha Allenki Adds bindings for Qualcomm's 28 nm USB PHY supporting Low-Speed, Full-Speed and Hi-Speed USB connectivity on Qualcomm chipsets. [bod: Converted to YAML. Changed name dropping snps, 28nm components] Signed-off-by: Sriharsha Allenki Signed-off-by: Anu Ramanathan Signed-off-by: Bjorn Andersson Signed-off-by: Shawn Guo Reviewed-by: Rob Herring Tested-by: Bjorn Andersson Cc: Andy Gross Cc: Bjorn Andersson Cc: Kishon Vijay Abraham I Cc: Rob Herring Cc: Mark Rutland Cc: Jorge Ramirez-Ortiz Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- .../bindings/phy/qcom,usb-hs-28nm.yaml | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml new file mode 100644 index 000000000000..ca6a0836b53c --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY + +maintainers: + - Bryan O'Donoghue + +description: | + Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY + +properties: + compatible: + enum: + - qcom,usb-hs-28nm-femtophy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: rpmcc ref clock + - description: PHY AHB clock + - description: Rentention clock + + clock-names: + items: + - const: ref + - const: ahb + - const: sleep + + resets: + items: + - description: PHY core reset + - description: POR reset + + reset-names: + items: + - const: phy + - const: por + + vdd-supply: + description: phandle to the regulator VDD supply node. + + vdda1p8-supply: + description: phandle to the regulator 1.8V supply node. + + vdda3p3-supply: + description: phandle to the regulator 3.3V supply node. + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - resets + - reset-names + - vdd-supply + - vdda1p8-supply + - vdda3p3-supply + +additionalProperties: false + +examples: + - | + #include + #include + usb2_phy_prim: phy@7a000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + reg = <0x0007a000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "ahb", "sleep"; + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&gcc GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + }; +... From patchwork Wed Mar 11 19:13:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 190027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75FD5C5ACC0 for ; Wed, 11 Mar 2020 19:14:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5C63720749 for ; Wed, 11 Mar 2020 19:14:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="bf/b4c/p" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731099AbgCKTOZ (ORCPT ); Wed, 11 Mar 2020 15:14:25 -0400 Received: from mail-wm1-f66.google.com ([209.85.128.66]:36902 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731105AbgCKTOF (ORCPT ); Wed, 11 Mar 2020 15:14:05 -0400 Received: by mail-wm1-f66.google.com with SMTP id a141so3394841wme.2 for ; Wed, 11 Mar 2020 12:14:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NgvMc7i25yDAHnugh3Vxjp3oZOiea1Kicbytox9AQ0c=; b=bf/b4c/pYEdagBgPhBlX/fhHSXCpWCn68LojLia5mmXizN3l7/19/+tF2OEfJ888aV MLUSA7EMx+Wirap5FwJn7XuFxSCW5zqP0Z4Q2cmdvNw4QUrDSF13p3vNDVAXp/dmJFr2 MlFW98fXSz0N8w1Cx+CFb2UtQCVBo10URP7+oQemG+AE9ibwuh0IATN/PEzxHz7QfXPF Yc2HSEK59Y/JzzIN/D8L7uZB5XlQC2Z8Bj6pnvMMECngGrF7x6yZveHJ4lhHdII1AKxB 7c5GOag3w0v8rbWC5nwRnqYIIRbyO57DsZlCTTIOeE75lurJjacFVjqBJoi/PPGz/sM8 m7aA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NgvMc7i25yDAHnugh3Vxjp3oZOiea1Kicbytox9AQ0c=; b=JzEyUNrGpCXJTNM0kWP7eun9gmR2ei/AOrXimevOuy6JsLDih/k00xRyDXuOPjMejA IzZT3kOBOuaNZQtWZtU2lZOW+1iwwytLDRHYM6wkNSwQoG+ClZvUBV9+59ot3Jw9Hs8/ kstDgTHkc06sviA4t6z2KWRNz3wABa9WToZ0PdiFJAeYrNwLKSxbiOk3FZg4FjNQM9yd sZcRDg2mFCYNHVtH5HEVnnxE/SAFhlhIOrpJgp/lae+bklyCGqRtOjsDQYyzbxZdKFm8 7gGRfbsgyG5lg6+RGorKhPAm5pqeiJRFiVnXIJRhQCTtmLyJsBjB8xQSseZzdrjKEtwl R4eQ== X-Gm-Message-State: ANhLgQ2vMcUA8yMqRRioQTMTIwLsPrX2APs2vFKbBFFBfD7xMr5BNtyo GvoDFL9xjBKC9k56EhFJjM/IaA== X-Google-Smtp-Source: ADFU+vsbBVZ+i6l13QL4BdNKAJtE5pTBHjVgd1EoiHx5QBBgWrVWrpNbc439wZfO0NvZdfWrYHi2Rg== X-Received: by 2002:a1c:9a88:: with SMTP id c130mr222919wme.73.1583954044313; Wed, 11 Mar 2020 12:14:04 -0700 (PDT) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id v8sm69443919wrw.2.2020.03.11.12.14.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2020 12:14:03 -0700 (PDT) From: Bryan O'Donoghue To: kishon@ti.com Cc: linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-msm@vger.kernel.org, jackp@codeaurora.org, robh@kernel.org, bjorn.andersson@linaro.org, p.zabel@pengutronix.de, Jorge Ramirez-Ortiz , Jorge Ramirez-Ortiz , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, Bryan O'Donoghue Subject: [PATCH 4/5] dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings Date: Wed, 11 Mar 2020 19:13:57 +0000 Message-Id: <20200311191358.8102-5-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200311191358.8102-1-bryan.odonoghue@linaro.org> References: <20200311191358.8102-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jorge Ramirez-Ortiz Binding description for Qualcomm's Synopsys 1.0.0 SuperSpeed PHY. This PHY appears in a number of SoCs on various flavors of 20nm and 28nm nodes. This commit adds information related to the 28nm node only. Based on Sriharsha Allenki's original definitions. [bod: converted to yaml format] Signed-off-by: Jorge Ramirez-Ortiz Cc: Jorge Ramirez-Ortiz Cc: Rob Herring Cc: Mark Rutland Cc: Bjorn Andersson Cc: Jorge Ramirez-Ortiz Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Rob Herring Tested-by: Bjorn Andersson Signed-off-by: Bryan O'Donoghue --- .../devicetree/bindings/phy/qcom,usb-ss.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml new file mode 100644 index 000000000000..bd1388d62ce0 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY + +maintainers: + - Bryan O'Donoghue + +description: | + Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY + +properties: + compatible: + enum: + - qcom,usb-ss-28nm-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: rpmcc clock + - description: PHY AHB clock + - description: SuperSpeed pipe clock + + clock-names: + items: + - const: ref + - const: ahb + - const: pipe + + vdd-supply: + description: phandle to the regulator VDD supply node. + + vdda1p8-supply: + description: phandle to the regulator 1.8V supply node. + + resets: + items: + - description: COM reset + - description: PHY reset line + + reset-names: + items: + - const: com + - const: phy + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - vdd-supply + - vdda1p8-supply + +additionalProperties: false + +examples: + - | + #include + #include + usb3_phy: usb3-phy@78000 { + compatible = "qcom,usb-ss-28nm-phy"; + reg = <0x78000 0x400>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref", "ahb", "pipe"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + vdd-supply = <&vreg_l3_1p05>; + vdda1p8-supply = <&vreg_l5_1p8>; + }; +... From patchwork Wed Mar 11 19:13:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 190028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9423C4CECE for ; Wed, 11 Mar 2020 19:14:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BDA1620578 for ; Wed, 11 Mar 2020 19:14:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Q5IO7jmx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731113AbgCKTOQ (ORCPT ); Wed, 11 Mar 2020 15:14:16 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:37965 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731123AbgCKTOJ (ORCPT ); Wed, 11 Mar 2020 15:14:09 -0400 Received: by mail-wm1-f68.google.com with SMTP id n2so3395442wmc.3 for ; Wed, 11 Mar 2020 12:14:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KJ8pyUFNVfAAPsA5IqEGNlFaiQhnm267Cj5yjO4ggQM=; b=Q5IO7jmxJuuKfQcRwsjcZfdS+3HWdI/qftDW8SWNdwA8NXFFlaFJjPJdIT3q1L7XUy pxgttXf36s2UrRuvDO9bg9TfHFmG68upALHLabanXgSJ5c+cdceC7Oe6/B4pRz4eSQQK awsitvGSAE4L6kOgvt8ltZsnpjJ3uMI7uLdK0Sr3lvLTN/fJxK9OrIsCvfD83WeQ6DHA xr0La+IShbnZ/8l8cIfltUuH/cz8G+Yhy/KdFkBh0fUpYnIVUFPSVqv2uSzlWJg6s4fF R9WsrUTFvX/ZxMnmBqB+rOeuTdiFpFwVqzPAdPdgX0clnwxEbFzYagYVcJZS1kXXJLq7 mG9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KJ8pyUFNVfAAPsA5IqEGNlFaiQhnm267Cj5yjO4ggQM=; b=kz3xGAblcPl5Lo/905Qm7NXtGE74ElGMDWlJ1rffiKs0otVou2u3LThvrWFLBykC4I 3Zikg2KyB5MIK7Rn6FIfdvWUwsjHvLnAaJlNwRvgX7NsuETdNP0IghPqyHbRknACWCB9 ex2W9uckqzWREn3iyFjINBf2/oa5lNLtShvRPwvg4OTlg5LaZs6czxeH9Ev4LbGrGTcE te0sRouYSrVUyX4pCNX+Cypq1AHgbFfeDcn0y3bmbw+sN/nW6BML5KBgMr6LsRsSv9qh U7aS6iZoDl4aWUEJkaR2tKwfIhUyQWkVvBy4Mlc+kUoIzhfcLRm9y/3WUwWKlkK217+9 J9cQ== X-Gm-Message-State: ANhLgQ1JFkV0LYhZayH8OM+5u80o7qgUwcmLg+GAcnJeWobvO0lBSeq2 YM6dPaHZqxtgJkDtJHCvshsqEg== X-Google-Smtp-Source: ADFU+vs025imCI+nzJY9mJGdjpRPDkFlc+v6Mg53Kz/G7ojZlRnhfOyOBg/gKSvBrOzjTZ0ELfdW8g== X-Received: by 2002:a1c:c3c3:: with SMTP id t186mr244481wmf.118.1583954045957; Wed, 11 Mar 2020 12:14:05 -0700 (PDT) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id v8sm69443919wrw.2.2020.03.11.12.14.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2020 12:14:05 -0700 (PDT) From: Bryan O'Donoghue To: kishon@ti.com Cc: linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-msm@vger.kernel.org, jackp@codeaurora.org, robh@kernel.org, bjorn.andersson@linaro.org, p.zabel@pengutronix.de, Jorge Ramirez-Ortiz , Jorge Ramirez-Ortiz , Sriharsha Allenki's , Andy Gross , Bryan O'Donoghue Subject: [PATCH 5/5] phy: qualcomm: usb: Add SuperSpeed PHY driver Date: Wed, 11 Mar 2020 19:13:58 +0000 Message-Id: <20200311191358.8102-6-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200311191358.8102-1-bryan.odonoghue@linaro.org> References: <20200311191358.8102-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jorge Ramirez-Ortiz Controls Qualcomm's SS PHY 1.0.0 implemented on various SoCs on both the 20nm and 28nm process nodes. Based on Sriharsha Allenki's original code. [bod: Removed dependency on extcon. Switched to gpio-usb-conn to handle VBUS On/Off Switched to usb-role-switch to bind gpio-usb-conn to DWC3] Signed-off-by: Jorge Ramirez-Ortiz Cc: Jorge Ramirez-Ortiz Cc: Sriharsha Allenki's Cc: Andy Gross Cc: Bjorn Andersson Cc: Kishon Vijay Abraham I Cc: Philipp Zabel Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Philipp Zabel Tested-by: Bjorn Andersson Signed-off-by: Bryan O'Donoghue --- drivers/phy/qualcomm/Kconfig | 9 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-usb-ss.c | 246 +++++++++++++++++++++++++ 3 files changed, 256 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-ss.c diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index 9c56a7216f72..98674ed094d9 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -102,3 +102,12 @@ config PHY_QCOM_USB_HS_28NM High-Speed PHY driver. This driver supports the Hi-Speed PHY which is usually paired with either the ChipIdea or Synopsys DWC3 USB IPs on MSM SOCs. + +config PHY_QCOM_USB_SS + tristate "Qualcomm USB Super-Speed PHY driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in + select GENERIC_PHY + help + Enable this to support the Super-Speed USB transceiver on various + Qualcomm chipsets. diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index a4dab5329de0..1f14aeacbd70 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o +obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qualcomm/phy-qcom-usb-ss.c b/drivers/phy/qualcomm/phy-qcom-usb-ss.c new file mode 100644 index 000000000000..a3a6d3ce7ea1 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-usb-ss.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2012-2014,2017 The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2020, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PHY_CTRL0 0x6C +#define PHY_CTRL1 0x70 +#define PHY_CTRL2 0x74 +#define PHY_CTRL4 0x7C + +/* PHY_CTRL bits */ +#define REF_PHY_EN BIT(0) +#define LANE0_PWR_ON BIT(2) +#define SWI_PCS_CLK_SEL BIT(4) +#define TST_PWR_DOWN BIT(4) +#define PHY_RESET BIT(7) + +#define NUM_BULK_CLKS 3 +#define NUM_BULK_REGS 2 + +struct ssphy_priv { + void __iomem *base; + struct device *dev; + struct reset_control *reset_com; + struct reset_control *reset_phy; + struct regulator_bulk_data regs[NUM_BULK_REGS]; + struct clk_bulk_data clks[NUM_BULK_CLKS]; + enum phy_mode mode; +}; + +static inline void qcom_ssphy_updatel(void __iomem *addr, u32 mask, u32 val) +{ + writel((readl(addr) & ~mask) | val, addr); +} + +static int qcom_ssphy_do_reset(struct ssphy_priv *priv) +{ + int ret; + + if (!priv->reset_com) { + qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, + PHY_RESET); + usleep_range(10, 20); + qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, 0); + } else { + ret = reset_control_assert(priv->reset_com); + if (ret) { + dev_err(priv->dev, "Failed to assert reset com\n"); + return ret; + } + + ret = reset_control_assert(priv->reset_phy); + if (ret) { + dev_err(priv->dev, "Failed to assert reset phy\n"); + return ret; + } + + usleep_range(10, 20); + + ret = reset_control_deassert(priv->reset_com); + if (ret) { + dev_err(priv->dev, "Failed to deassert reset com\n"); + return ret; + } + + ret = reset_control_deassert(priv->reset_phy); + if (ret) { + dev_err(priv->dev, "Failed to deassert reset phy\n"); + return ret; + } + } + + return 0; +} + +static int qcom_ssphy_power_on(struct phy *phy) +{ + struct ssphy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = regulator_bulk_enable(NUM_BULK_REGS, priv->regs); + if (ret) + return ret; + + ret = clk_bulk_prepare_enable(NUM_BULK_CLKS, priv->clks); + if (ret) + goto err_disable_regulator; + + ret = qcom_ssphy_do_reset(priv); + if (ret) + goto err_disable_clock; + + writeb(SWI_PCS_CLK_SEL, priv->base + PHY_CTRL0); + qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, LANE0_PWR_ON); + qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, REF_PHY_EN); + qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, 0); + + return 0; +err_disable_clock: + clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks); +err_disable_regulator: + regulator_bulk_disable(NUM_BULK_REGS, priv->regs); + + return ret; +} + +static int qcom_ssphy_power_off(struct phy *phy) +{ + struct ssphy_priv *priv = phy_get_drvdata(phy); + + qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, 0); + qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, 0); + qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, TST_PWR_DOWN); + + clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks); + regulator_bulk_disable(NUM_BULK_REGS, priv->regs); + + return 0; +} + +static int qcom_ssphy_init_clock(struct ssphy_priv *priv) +{ + priv->clks[0].id = "ref"; + priv->clks[1].id = "ahb"; + priv->clks[2].id = "pipe"; + + return devm_clk_bulk_get(priv->dev, NUM_BULK_CLKS, priv->clks); +} + +static int qcom_ssphy_init_regulator(struct ssphy_priv *priv) +{ + int ret; + + priv->regs[0].supply = "vdd"; + priv->regs[1].supply = "vdda1p8"; + ret = devm_regulator_bulk_get(priv->dev, NUM_BULK_REGS, priv->regs); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(priv->dev, "Failed to get regulators\n"); + return ret; + } + + return ret; +} + +static int qcom_ssphy_init_reset(struct ssphy_priv *priv) +{ + priv->reset_com = devm_reset_control_get_optional_exclusive(priv->dev, "com"); + if (IS_ERR(priv->reset_com)) { + dev_err(priv->dev, "Failed to get reset control com\n"); + return PTR_ERR(priv->reset_com); + } + + if (priv->reset_com) { + /* if reset_com is present, reset_phy is no longer optional */ + priv->reset_phy = devm_reset_control_get_exclusive(priv->dev, "phy"); + if (IS_ERR(priv->reset_phy)) { + dev_err(priv->dev, "Failed to get reset control phy\n"); + return PTR_ERR(priv->reset_phy); + } + } + + return 0; +} + +static const struct phy_ops qcom_ssphy_ops = { + .power_off = qcom_ssphy_power_off, + .power_on = qcom_ssphy_power_on, + .owner = THIS_MODULE, +}; + +static int qcom_ssphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *provider; + struct ssphy_priv *priv; + struct phy *phy; + int ret; + + priv = devm_kzalloc(dev, sizeof(struct ssphy_priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + priv->mode = PHY_MODE_INVALID; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + ret = qcom_ssphy_init_clock(priv); + if (ret) + return ret; + + ret = qcom_ssphy_init_reset(priv); + if (ret) + return ret; + + ret = qcom_ssphy_init_regulator(priv); + if (ret) + return ret; + + phy = devm_phy_create(dev, dev->of_node, &qcom_ssphy_ops); + if (IS_ERR(phy)) { + dev_err(dev, "Failed to create the SS phy\n"); + return PTR_ERR(phy); + } + + phy_set_drvdata(phy, priv); + + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(provider); +} + +static const struct of_device_id qcom_ssphy_match[] = { + { .compatible = "qcom,usb-ss-28nm-phy", }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_ssphy_match); + +static struct platform_driver qcom_ssphy_driver = { + .probe = qcom_ssphy_probe, + .driver = { + .name = "qcom-usb-ssphy", + .of_match_table = qcom_ssphy_match, + }, +}; +module_platform_driver(qcom_ssphy_driver); + +MODULE_DESCRIPTION("Qualcomm SuperSpeed USB PHY driver"); +MODULE_LICENSE("GPL v2");