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[81.169.180.215]) by mx.google.com with ESMTP id n42si1668197edd.38.2017.07.11.09.22.27; Tue, 11 Jul 2017 09:22:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.b=BEOBwgTr; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id EBDDBC21E5B; Tue, 11 Jul 2017 16:20:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5B46CC21DF0; Tue, 11 Jul 2017 16:20:36 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3D144C21E43; Tue, 11 Jul 2017 16:20:26 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id E4663C21DDA for ; Tue, 11 Jul 2017 16:20:22 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v6BGKL9V022671; Tue, 11 Jul 2017 11:20:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1499790021; bh=3mNe+5zQxOtdRyRifmj9bpCUY8dKulXJrlC87cafCEc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BEOBwgTrWXl/eGSBGfvovo1TDZKSfGmHoWoZpziIULgxwmo6I8+nk9EYDnP2rPROg gi2EYKwv8iFbaEGyH34cbVHWNeoO6gOqngy5c8MXP7+qjGaACAdQ+gXBaN86r9pgaP wbCcQo957USvWLXXu7vsLlpAL7cgyGAt4hxmd3tc= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v6BGKLRp012200; Tue, 11 Jul 2017 11:20:21 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Tue, 11 Jul 2017 11:20:20 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v6BGKKuR009707; Tue, 11 Jul 2017 11:20:20 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Tue, 11 Jul 2017 18:20:12 +0200 Message-ID: <1499790014-29964-4-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1499790014-29964-1-git-send-email-jjhiblot@ti.com> References: <1499790014-29964-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 Subject: [U-Boot] [PATCH 3/5] mmc: omap_hsmmc: Add support for DMA (ADMA2) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I The omap hsmmc host controller can have the ADMA2 feature. It brings better read and write throughput. On most SOC, the capability is read from the hl_hwinfo register. On OMAP3, DMA support is compiled out. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- arch/arm/include/asm/omap_mmc.h | 12 ++- drivers/mmc/omap_hsmmc.c | 186 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 195 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 2b489a4..206badb 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -29,7 +29,10 @@ struct hsmmc { #ifndef CONFIG_OMAP34XX - unsigned char res0[0x100]; + unsigned int hl_rev; + unsigned int hl_hwinfo; + unsigned int hl_sysconfig; + unsigned char res0[0xf4]; #endif unsigned char res1[0x10]; unsigned int sysconfig; /* 0x10 */ @@ -52,6 +55,9 @@ struct hsmmc { unsigned int ie; /* 0x134 */ unsigned char res4[0x8]; unsigned int capa; /* 0x140 */ + unsigned char res5[0x10]; + unsigned int admaes; /* 0x154 */ + unsigned int admasal; /* 0x158 */ }; struct omap_hsmmc_plat { @@ -64,6 +70,7 @@ struct omap_hsmmc_plat { /* * OMAP HS MMC Bit definitions */ +#define MADMA_EN (0x1 << 0) #define MMC_SOFTRESET (0x1 << 1) #define RESETDONE (0x1 << 0) #define NOOPENDRAIN (0x0 << 0) @@ -80,6 +87,7 @@ struct omap_hsmmc_plat { #define WPP_ACTIVEHIGH (0x0 << 8) #define RESERVED_MASK (0x3 << 9) #define CTPL_MMC_SD (0x0 << 11) +#define DMA_MASTER (0x1 << 20) #define BLEN_512BYTESLEN (0x200 << 0) #define NBLK_STPCNT (0x0 << 16) #define DE_DISABLE (0x0 << 0) @@ -119,6 +127,7 @@ struct omap_hsmmc_plat { #define SDBP_PWRON (0x1 << 8) #define SDVS_1V8 (0x5 << 9) #define SDVS_3V0 (0x6 << 9) +#define DMA_SELECT (0x2 << 3) #define ICE_MASK (0x1 << 0) #define ICE_STOP (0x0 << 0) #define ICS_MASK (0x1 << 1) @@ -148,6 +157,7 @@ struct omap_hsmmc_plat { #define IE_DTO (0x01 << 20) #define IE_DCRC (0x01 << 21) #define IE_DEB (0x01 << 22) +#define IE_ADMAE (0x01 << 25) #define IE_CERR (0x01 << 28) #define IE_BADA (0x01 << 29) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 2c1e429..3419dc5 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -71,10 +72,37 @@ struct omap_hsmmc_data { int wp_gpio; #endif #endif + u8 controller_flags; +#ifndef CONFIG_OMAP34XX + struct omap_hsmmc_adma_desc *adma_desc_table; + uint desc_slot; +#endif +}; + +#ifndef CONFIG_OMAP34XX +struct omap_hsmmc_adma_desc { + u8 attr; + u8 reserved; + u16 len; + u32 addr; }; +#define ADMA_MAX_LEN 63488 + +/* Decriptor table defines */ +#define ADMA_DESC_ATTR_VALID BIT(0) +#define ADMA_DESC_ATTR_END BIT(1) +#define ADMA_DESC_ATTR_INT BIT(2) +#define ADMA_DESC_ATTR_ACT1 BIT(4) +#define ADMA_DESC_ATTR_ACT2 BIT(5) + +#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2 +#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2) +#endif + /* If we fail after 1 second wait, something is really bad */ #define MAX_RETRY_MS 1000 +#define OMAP_HSMMC_USE_ADMA BIT(2) static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, @@ -242,6 +270,11 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) return -ETIMEDOUT; } } +#ifndef CONFIG_OMAP34XX + reg_val = readl(&mmc_base->hl_hwinfo); + if (reg_val & MADMA_EN) + priv->controller_flags |= OMAP_HSMMC_USE_ADMA; +#endif writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, &mmc_base->capa); @@ -269,8 +302,8 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | - IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, - &mmc_base->ie); + IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC | + IE_CC, &mmc_base->ie); mmc_init_stream(mmc_base); @@ -322,6 +355,123 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) } } } + +#ifndef CONFIG_OMAP34XX +static int omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end) +{ + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + struct omap_hsmmc_adma_desc *desc; + u8 attr; + + desc = &priv->adma_desc_table[priv->desc_slot]; + + attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA; + if (!end) + priv->desc_slot++; + else + attr |= ADMA_DESC_ATTR_END; + + desc->len = len; + desc->addr = (u32)buf; + desc->reserved = 0; + desc->attr = attr; + + return 0; +} + +static int omap_hsmmc_prepare_adma_table(struct mmc *mmc, struct mmc_data *data) +{ + uint total_len = data->blocksize * data->blocks; + uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN); + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + int i = desc_count; + char *buf; + + priv->desc_slot = 0; + priv->adma_desc_table = (struct omap_hsmmc_adma_desc *) + memalign(ARCH_DMA_MINALIGN, desc_count * + sizeof(struct omap_hsmmc_adma_desc)); + + if (data->flags & MMC_DATA_READ) + buf = data->dest; + else + buf = (char *)data->src; + + while (--i) { + omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false); + buf += ADMA_MAX_LEN; + total_len -= ADMA_MAX_LEN; + } + + omap_hsmmc_adma_desc(mmc, buf, total_len, true); + + flush_dcache_range((long)priv->adma_desc_table, + (long)priv->adma_desc_table + + ROUND(desc_count * + sizeof(struct omap_hsmmc_adma_desc), + ARCH_DMA_MINALIGN)); + return 0; +} + +static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data) +{ + struct hsmmc *mmc_base; + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + u32 val; + char *buf; + + mmc_base = priv->base_addr; + omap_hsmmc_prepare_adma_table(mmc, data); + + if (data->flags & MMC_DATA_READ) + buf = data->dest; + else + buf = (char *)data->src; + + val = readl(&mmc_base->hctl); + val |= DMA_SELECT; + writel(val, &mmc_base->hctl); + + val = readl(&mmc_base->con); + val |= DMA_MASTER; + writel(val, &mmc_base->con); + + writel((u32)priv->adma_desc_table, &mmc_base->admasal); + + /* TODO: This shouldn't be required for read. However I don't seem + * to get valid data without this. + */ + flush_dcache_range((u32)buf, + (u32)buf + + ROUND(data->blocksize * data->blocks, + ARCH_DMA_MINALIGN)); +} + +static void omap_hsmmc_dma_cleanup(struct mmc *mmc) +{ + struct hsmmc *mmc_base; + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + u32 val; + + mmc_base = priv->base_addr; + + val = readl(&mmc_base->con); + val &= ~DMA_MASTER; + writel(val, &mmc_base->con); + + val = readl(&mmc_base->hctl); + val &= ~DMA_SELECT; + writel(val, &mmc_base->hctl); + + kfree(priv->adma_desc_table); +} +#else +#define omap_hsmmc_adma_desc +#define omap_hsmmc_prepare_adma_table +#define omap_hsmmc_prepare_data +#define omap_hsmmc_dma_cleanup +#endif + #ifndef CONFIG_DM_MMC static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) @@ -332,6 +482,8 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data) { struct omap_hsmmc_data *priv = dev_get_priv(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct mmc *mmc = upriv->mmc; #endif struct hsmmc *mmc_base; unsigned int flags, mmc_stat; @@ -405,6 +557,14 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, flags |= (DP_DATA | DDIR_READ); else flags |= (DP_DATA | DDIR_WRITE); + +#ifndef CONFIG_OMAP34XX + if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && + !mmc_is_tuning_cmd(cmd->cmdidx)) { + omap_hsmmc_prepare_data(mmc, data); + flags |= DE_ENABLE; + } +#endif } writel(cmd->cmdarg, &mmc_base->arg); @@ -441,6 +601,28 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, } } +#ifndef CONFIG_OMAP34XX + if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data && + !mmc_is_tuning_cmd(cmd->cmdidx)) { + if (mmc_stat & IE_ADMAE) { + omap_hsmmc_dma_cleanup(mmc); + return -1; + } + + do { + mmc_stat = readl(&mmc_base->stat); + if (mmc_stat & TC_MASK) { + writel(readl(&mmc_base->stat) | TC_MASK, + &mmc_base->stat); + break; + } + } while (1); + + omap_hsmmc_dma_cleanup(mmc); + return 0; + } +#endif + if (data && (data->flags & MMC_DATA_READ)) { mmc_read_data(mmc_base, data->dest, data->blocksize * data->blocks); From patchwork Tue Jul 11 16:20:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 107407 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp5087787qge; Tue, 11 Jul 2017 09:23:24 -0700 (PDT) X-Received: by 10.80.179.12 with SMTP id q12mr3082710edd.151.1499790204054; Tue, 11 Jul 2017 09:23:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1499790204; cv=none; d=google.com; s=arc-20160816; b=CWUaKRzb59EtnuP9beFOvwtWoIK9rm3wWMXPWArMSNcVhSZhG8cvmAmSbNqkcumB3S wjhSE/CRdZ6tdPN4vwRLc8POlDvQBAv+091Q8EYy3OnKjEzWidYiBmVWmIgUinHCuXI/ 3uSZUYOtab91ldocYmkCESdyMX3bT5ox6trIL8H0rBbxG2NuyWgQKzT1F+B+l/FH0xwy oJD9taqjwbC9frjbwqlulibe9dsLXI15lXW4pmgZ73A4cyu0LjkaOVCy8S20LIoyY5Pn WAI21a2o7K1wUicTuXfhl00XPPmoCVdRhQFlU+ImKT7FaltpWE9Fcw5cvLjhlOJQeYzv eBhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=hYXO1zEPN1f5VQ4P7c4Iyn0LlAAMPQCQ+nj7po54Ed0=; b=o8qSNNJc+Ju0+I4KI/rXG+Xm9P45iQueNDDJ6MXkzGDcYLDfOC+YrQK9BKeh6zsmAB fzvZBJvmfqnuueSbVFgbhCgw/xCUTVCxyU2qU0EwVj4f9mluZ7133qWehFQf3i6upI8b Jc0b7L8MKRHsL+Jj/M4/KH8zEfB87VmonFkS4ChsslCvO6zM/1As3h8qchVkX3B1khZX Mb+aGXQ9kT+3yMAO44v4qjAJzKyrGNaZ4ZgyzrqnSPPgyKdi9pYa9eqwCVMHvA5zwdN9 arhVDfBVSz7RmiGBpn0npUoupCf2ZEqgQgTBmiZTlpg4oOsuwt88NzczgAzIH8txCZAZ aX4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.b=jolb6dGS; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id d33si1889946edd.209.2017.07.11.09.23.23; Tue, 11 Jul 2017 09:23:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.b=jolb6dGS; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 9DE27C21D56; Tue, 11 Jul 2017 16:21:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7D2C1C21E58; Tue, 11 Jul 2017 16:20:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 124C0C21C73; Tue, 11 Jul 2017 16:20:27 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id 0D5B0C21E63 for ; Tue, 11 Jul 2017 16:20:23 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v6BGKMx5006028; Tue, 11 Jul 2017 11:20:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1499790022; bh=drYEDhcZcg8IetpQxi5107b9LTd5UecDZtwzcYmjOVI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jolb6dGS1S5NEtNTEwkFuVNiNsf0WpRGuEUDPY2zrfvzYi5tc0wDMNA8rzKNQMqCE GrfVLv3ipwbqdvi7zkfh0NsP4MoMEGNjaYsqDgmCc8ppvYE5eHduErg0c+HvetWY7g 2tx3EQcsolA26e1KSNIaBE2WNVaTrYE0lNYBMsIs= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v6BGKMVD012217; Tue, 11 Jul 2017 11:20:22 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Tue, 11 Jul 2017 11:20:21 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v6BGKLoQ028982; Tue, 11 Jul 2017 11:20:21 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Tue, 11 Jul 2017 18:20:13 +0200 Message-ID: <1499790014-29964-5-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1499790014-29964-1-git-send-email-jjhiblot@ti.com> References: <1499790014-29964-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 Subject: [U-Boot] [PATCH 4/5] mmc: omap_hsmmc: Enable Auto command (CMD12) enable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I Instead of sending STOP TRANSMISSION command from MMC core, enable the auto command feature so that the Host Controller issues CMD12 automatically when last block transfer is completed. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- drivers/mmc/omap_hsmmc.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 3419dc5..3ee81bb 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -490,6 +490,10 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, ulong start; mmc_base = priv->base_addr; + + if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) + return 0; + start = get_timer(0); while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { if (get_timer(0) - start > MAX_RETRY_MS) { @@ -546,7 +550,7 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, if (data) { if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { - flags |= (MSBS_MULTIBLK | BCE_ENABLE); + flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE); data->blocksize = 512; writel(data->blocksize | (data->blocks << 16), &mmc_base->blk); From patchwork Tue Jul 11 16:20:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 107406 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp5087186qge; Tue, 11 Jul 2017 09:22:54 -0700 (PDT) X-Received: by 10.80.135.175 with SMTP id a44mr3169597eda.90.1499790174811; Tue, 11 Jul 2017 09:22:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1499790174; cv=none; d=google.com; s=arc-20160816; b=v8bHjHb1S1MhXdKbTtezLjUJ/A09IWaSQWdk2e7IzOP1F7CdodhGp00njGE2O/mAeB 34IyeUXm+NXJTyOrH9glWihcrDO5QuicVvntT3bkvvhT8M5zPpPuEFzQIdCab6UJJSEy 0zJvoBg70lreeEb9jKsUflY+QY+Q3baWd2uNJ5Or+hKt0glHpP94cqFwUuKccffQqW+7 z8tdgYkekknLoG/SaeGJkLpt1BYrVSRbrM/5OhnVwyaCR/w2p6s4f0N+RsdkpVuWfWhr PW43en9h+9uNHd1JsmYNH1A1sPKetVR9cZZCkDyxcqFbbdWflCVc1vEbDKmvCiitkSzd HyZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=HOx2UAzzGVyFAI7tBXVZkfH6PQG/1ZpVGdE2UhZEE5o=; b=gEK1zYx3IrrEhW7dT+uGVcCsjEWq7VNqf//G4Bkj1KeiCfan4B+xI15Sy3lDnklVpy obPOsC8jIgSMSSE3qVbCqb3zpuni+EQtniJpFloNb3cg1SXdzFrVaaJ0XKO7gVtCQGlF Bmc2uLVxhD2O3XebKo8hY9lN5n4x6zqEBMwsBBCTNCWcaGR/F9Fz+YZOnGFwxkocl//t CWp7JgVQh10jPtv8OFmK7ZgRpX8YRqcF8swAd2B7BRCFIExnKcy0J+6DHU3KgzFMugbR 4u8VSWzBs9Y48tHH67crWvxdd6E+EznRdLF5B8lo6IVjdW+8F48sjZrapVAso4II+CXw 5IjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.b=h5KA3axW; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id y30si1729263edy.113.2017.07.11.09.22.54; Tue, 11 Jul 2017 09:22:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.b=h5KA3axW; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 6AE02C21D63; Tue, 11 Jul 2017 16:21:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 93EF8C21DD1; Tue, 11 Jul 2017 16:21:48 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1302FC21E5B; Tue, 11 Jul 2017 16:21:16 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id 1B6FBC21DF0 for ; Tue, 11 Jul 2017 16:21:10 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v6BGKScN006364; Tue, 11 Jul 2017 11:20:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1499790028; bh=pG62pox9cWoE44RtNztsV8i+oSfVqa2ijK3xA7aXV9k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=h5KA3axWnNEVh7KXlTeeIwdbyLiQtK4NNhR1ov1ls6ENZNrBPCAFFn7t5Vh05f97f ZEUNSB6V591xYMSCkHUeODPwpjrxSv3bEU6pntKKh783ytswGHDlru5LDBW/0nhFRC j9B/nZDegOajvzOi+5tXPiqNmSeGMdy2+8J4qQ1o= Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v6BGKNSA016929; Tue, 11 Jul 2017 11:20:23 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Tue, 11 Jul 2017 11:20:23 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v6BGKMjj008682; Tue, 11 Jul 2017 11:20:23 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Tue, 11 Jul 2017 18:20:14 +0200 Message-ID: <1499790014-29964-6-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1499790014-29964-1-git-send-email-jjhiblot@ti.com> References: <1499790014-29964-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 Subject: [U-Boot] [PATCH 5/5] mmc: omap_hsmmc: Fix incorrect bit operations for disabling a bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I omap_hsmmc driver uses "|" in a couple of places for disabling a bit. While it's okay to use it in "mmc_reg_out" (since mmc_reg_out has a _mask_ argument to take care of resetting a bit), it's incorrectly used for resetting flags in "omap_hsmmc_send_cmd". Fix it here by using "&= ~()" to reset a bit. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- arch/arm/include/asm/omap_mmc.h | 6 ++---- drivers/mmc/omap_hsmmc.c | 7 ++++--- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 206badb..964bc5c 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -90,10 +90,9 @@ struct omap_hsmmc_plat { #define DMA_MASTER (0x1 << 20) #define BLEN_512BYTESLEN (0x200 << 0) #define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) +#define DE_ENABLE (0x1 << 0) #define BCE_ENABLE (0x1 << 1) -#define ACEN_DISABLE (0x0 << 2) +#define ACEN_ENABLE (0x1 << 2) #define DDIR_OFFSET (4) #define DDIR_MASK (0x1 << 4) #define DDIR_WRITE (0x0 << 4) @@ -134,7 +133,6 @@ struct omap_hsmmc_plat { #define ICS_NOTREADY (0x0 << 1) #define ICE_OSCILLATE (0x1 << 0) #define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) #define CEN_ENABLE (0x1 << 2) #define CLKD_OFFSET (6) #define CLKD_MASK (0x3FF << 6) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 3ee81bb..28865c0 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -287,7 +287,7 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) dsor = 240; mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), - (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); + (ICE_STOP | DTO_15THDTO)); mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, (dsor << CLKD_OFFSET) | ICE_OSCILLATE); start = get_timer(0); @@ -540,7 +540,8 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, /* enable default flags */ flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | - MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); + MSBS_SGLEBLK); + flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE); if (cmd->resp_type & MMC_RSP_CRC) flags |= CCCE_CHECK; @@ -794,7 +795,7 @@ static int omap_hsmmc_set_ios(struct udevice *dev) } mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), - (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); + (ICE_STOP | DTO_15THDTO)); mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, (dsor << CLKD_OFFSET) | ICE_OSCILLATE);