From patchwork Thu Apr 2 12:11:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 189768 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0F5CC43331 for ; Thu, 2 Apr 2020 12:12:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B1BAA2078C for ; Thu, 2 Apr 2020 12:12:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ilkvR70S" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388182AbgDBMME (ORCPT ); Thu, 2 Apr 2020 08:12:04 -0400 Received: from mail-ed1-f68.google.com ([209.85.208.68]:33303 "EHLO mail-ed1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388239AbgDBMMD (ORCPT ); Thu, 2 Apr 2020 08:12:03 -0400 Received: by mail-ed1-f68.google.com with SMTP id z65so3841414ede.0; Thu, 02 Apr 2020 05:12:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0dGTHqx3bG6gs03S9XoD7W3tW7je5nP9W1EztY8BydA=; b=ilkvR70Sx0A+pxHqWws9O1/N3VKSPMn8ZoXhFFp/mng5/RYun7AYZHAQyZRGZM88YG G0gdJ3TWV8zMxooeAkQmExPp+anICrT7GDAV7EscDKlxteBAuHGQiWTq8ICicQnhEr6f 7Pyqd30ahoZYiZJxsMrlKm8FtOGnn1+ZsWlkkepJzbdIvE3TgevlQf4DbS3Cwuu0etyw iFVUARt+Xsvt/gWB4ooItHtjTweQvrNwFsofidUwhna8bdjiOFDbptVItpWxxwSqM7Rb KZLJ5yMiC1beqWsapbSVnIvqMLPlm0g+FyfO5pIUd6DilO6HdHM5JQmhFmXQ2FVgOe4L Wzog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0dGTHqx3bG6gs03S9XoD7W3tW7je5nP9W1EztY8BydA=; b=lW0zFj93OrTJRYWMEXypSR3++ktYZXdoV+B0y3OjNB2Yq0AyJPrynWJUGup9C47hpq tSb8sQwgLWTGmGYxaDIphPFRwI7yrVSpbo6fs2ThKt8qreZQxvwajRH5S7JPdPMHfifT qa57Ld5xlnLDhXN/LZ206qq3mX27KINJ6I1PFifi/Mg2tyy5df76id7QveF+7oO6ZfSx yMhMvQbZKjRO6X0ArudEM+hcvttA8LkSaHo2GyMWPypw2NL8pB5gkDAzeamFJStmfhAV yrp2OXbzdORL5Ct3r8MnEMr5Zwc/1Waq/onu7ej+bBXiOXAIPASUmK6VCzM1Ve3eH32O ISiQ== X-Gm-Message-State: AGi0PuaJ9bxqUsPswAjOby6VS2kcUXlltsoak9NY5Pdfg+lbblPH217t LtLfNMNjhkiiEaXwQ6A0iQ0= X-Google-Smtp-Source: APiQypKYxjtcBBgBHnW12cQvcF13VWJDWgS7QE+pl2tfSyIFd+Kdh7NemNhQs3sSx010992j+hGdXw== X-Received: by 2002:a17:906:640f:: with SMTP id d15mr2959847ejm.191.1585829520480; Thu, 02 Apr 2020 05:12:00 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host250-251-dynamic.250-95-r.retail.telecomitalia.it. [95.250.251.250]) by smtp.googlemail.com with ESMTPSA id w20sm1083611ejv.40.2020.04.02.05.11.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 05:11:59 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Ansuel Smith , Rob Herring , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 02/10] devicetree: bindings: pci: add missing clks to qcom, pcie Date: Thu, 2 Apr 2020 14:11:39 +0200 Message-Id: <20200402121148.1767-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com> References: <20200402121148.1767-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document missing clks used in ipq806x soc. Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 981b4de12807..becdbdc0fffa 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -90,6 +90,8 @@ Definition: Should contain the following entries - "core" Clocks the pcie hw block - "phy" Clocks the pcie PHY block + - "aux" Clocks the pcie AUX block + - "ref" Clocks the pcie ref block - clock-names: Usage: required for apq8084/ipq4019 Value type: @@ -277,8 +279,10 @@ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc PCIE_A_CLK>, <&gcc PCIE_H_CLK>, - <&gcc PCIE_PHY_CLK>; - clock-names = "core", "iface", "phy"; + <&gcc PCIE_PHY_CLK>, + <&gcc PCIE_AUX_CLK>, + <&gcc PCIE_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; resets = <&gcc PCIE_ACLK_RESET>, <&gcc PCIE_HCLK_RESET>, <&gcc PCIE_POR_RESET>, From patchwork Thu Apr 2 12:11:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 189769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9A08C2BA17 for ; Thu, 2 Apr 2020 12:12:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B0EF42078B for ; Thu, 2 Apr 2020 12:12:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RgRQbPEz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388279AbgDBMMI (ORCPT ); Thu, 2 Apr 2020 08:12:08 -0400 Received: from mail-ed1-f68.google.com ([209.85.208.68]:41582 "EHLO mail-ed1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388270AbgDBMMH (ORCPT ); Thu, 2 Apr 2020 08:12:07 -0400 Received: by mail-ed1-f68.google.com with SMTP id v1so3778621edq.8; Thu, 02 Apr 2020 05:12:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QTJvUrUZh6Asz0TpkI0T8aoHyYL8TgG05bomTjzSOyM=; b=RgRQbPEzT5t5qyUie+NZNDm7W//5r0zMUaVjO0vTHJXLn1Jq+AFFTQ8NF6cuRQg3+r jw/UZ0DJckiTbrsc2w+LRw9hB6+7eL355HC2PuA/h9kNI0v/BB7GMtLZFI2h2ggYUkzO 2kWywja4BJWC6XJrGLixUBQ3ljfSuaSCOndwZ2/U0e7YWUQaq8COd31WDAGmAdJ/94yh yPe70XqwKy2yEEQjQyKtkqApsUALuBjY6nHOPvhtvtaWRIVWjeRoSSxZQDNQ7g4CPmMb xx/RPHnWVJ8675BRNXgFsSccucnSRJBTzypSeCXH6FRq5vzNuJuKye5C6I5dMdtdtYeK 3k9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QTJvUrUZh6Asz0TpkI0T8aoHyYL8TgG05bomTjzSOyM=; b=uc3AlM4XzV/n30xVL7NjtLsyGSQTIW8McC753TdFZ6U4S0f/SaygdwI0d0ab6EVwyl hWrhJGD+r4ExHc+xUlSeojeIRPXvylx0HG/5id9KqDJ21q69/e5L67x/WJr4OTsQl+Tg iCh+MZG5rmSbMXg5ysq+i032jtXRwohGQ1lZTHgEXj4uq+LFonAcuULep4xO6jOXDirw /76HgHgSE9POuKB4fmmYBUOAMfdTepUHt/QS8uVhvEOwBbskQBbQ26UZ7EEHcPjLh38Q GanjOsLeBALiV9a29U7CX+bSMskg/zZHc2Zrr6TB7XqooPv6HfkON5PlCuzjYKI+kXlV tUYQ== X-Gm-Message-State: AGi0PuZXCAisRoNnXecsqQjTsM2A1hE9t8YuKoPL+2CC0gAW/Vejt4Ok shWmWKwm3RC+xrx7pEU95Uo= X-Google-Smtp-Source: APiQypIapMX5g/RNGOzYfHeGKlNQ8T/bL6HvSioskJYSxgPjXIMKz7gAV5jsSa4/pYer1Ua7q64ybQ== X-Received: by 2002:a05:6402:705:: with SMTP id w5mr2585708edx.288.1585829524941; Thu, 02 Apr 2020 05:12:04 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host250-251-dynamic.250-95-r.retail.telecomitalia.it. [95.250.251.250]) by smtp.googlemail.com with ESMTPSA id w20sm1083611ejv.40.2020.04.02.05.12.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 05:12:04 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Ansuel Smith , Abhishek Sahu , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 04/10] PCIe: qcom: Fixed pcie_phy_clk branch issue Date: Thu, 2 Apr 2020 14:11:41 +0200 Message-Id: <20200402121148.1767-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com> References: <20200402121148.1767-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Following backtraces are observed in PCIe deinit operation. Hardware name: Qualcomm (Flattened Device Tree) (unwind_backtrace) from [] (show_stack+0x10/0x14) (show_stack) from [] (dump_stack+0x84/0x98) (dump_stack) from [] (warn_slowpath_common+0x9c/0xb8) (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40) (warn_slowpath_fmt) from [] (clk_branch_wait+0x114/0x120) (clk_branch_wait) from [] (clk_core_disable+0xd0/0x1f4) (clk_core_disable) from [] (clk_disable+0x24/0x30) (clk_disable) from [] (qcom_pcie_deinit_v0+0x6c/0xb8) (qcom_pcie_deinit_v0) from [] (qcom_pcie_host_init+0xe0/0xe8) (qcom_pcie_host_init) from [] (dw_pcie_host_init+0x3b0/0x538) (dw_pcie_host_init) from [] (qcom_pcie_probe+0x20c/0x2e4) pcie_phy_clk is generated for PCIe controller itself and the GCC controls its branch operation. This error is coming since the assert operations turn off the parent clock before branch clock. Now this patch moves clk_disable_unprepare before assert operations. Similarly, during probe function, the clock branch operation should be done after dessert operation. Currently, it does not generate any error since bootloader enables the pcie_phy_clk but the same error is coming during probe, if bootloader disables pcie_phy_clk. Signed-off-by: Abhishek Sahu Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 1fcc7fed8443..596731b54728 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -280,6 +280,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; + clk_disable_unprepare(res->phy_clk); reset_control_assert(res->pci_reset); reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); @@ -287,7 +288,6 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); - clk_disable_unprepare(res->phy_clk); clk_disable_unprepare(res->aux_clk); clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -325,12 +325,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_clk_core; } - ret = clk_prepare_enable(res->phy_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable phy clock\n"); - goto err_clk_phy; - } - ret = clk_prepare_enable(res->aux_clk); if (ret) { dev_err(dev, "cannot prepare/enable aux clock\n"); @@ -383,6 +377,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return ret; } + ret = clk_prepare_enable(res->phy_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable phy clock\n"); + goto err_deassert_ahb; + } + /* wait for clock acquisition */ usleep_range(1000, 1500); @@ -400,8 +400,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) err_clk_ref: clk_disable_unprepare(res->aux_clk); err_clk_aux: - clk_disable_unprepare(res->phy_clk); -err_clk_phy: clk_disable_unprepare(res->core_clk); err_clk_core: clk_disable_unprepare(res->iface_clk); From patchwork Thu Apr 2 12:11:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 189770 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22734C2BA1A for ; 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[95.250.251.250]) by smtp.googlemail.com with ESMTPSA id w20sm1083611ejv.40.2020.04.02.05.12.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 05:12:09 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Ansuel Smith , Rob Herring , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 06/10] devicetree: bindings: pci: add ext reset to qcom, pcie Date: Thu, 2 Apr 2020 14:11:43 +0200 Message-Id: <20200402121148.1767-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com> References: <20200402121148.1767-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document ext reset used in ipq806x soc by qcom pcie driver Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index becdbdc0fffa..6efcef040741 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -179,6 +179,7 @@ - "pwr" PWR reset - "ahb" AHB reset - "phy_ahb" PHY AHB reset + - "ext" EXT reset - reset-names: Usage: required for ipq8074 @@ -287,8 +288,9 @@ <&gcc PCIE_HCLK_RESET>, <&gcc PCIE_POR_RESET>, <&gcc PCIE_PCI_RESET>, - <&gcc PCIE_PHY_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy"; + <&gcc PCIE_PHY_RESET>, + <&gcc PCIE_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; pinctrl-0 = <&pcie_pins_default>; pinctrl-names = "default"; }; From patchwork Thu Apr 2 12:11:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 189772 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A61DBC2BA15 for ; Thu, 2 Apr 2020 12:12:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 72D3C20757 for ; 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[95.250.251.250]) by smtp.googlemail.com with ESMTPSA id w20sm1083611ejv.40.2020.04.02.05.12.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 05:12:11 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Ansuel Smith , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 07/10] PCIe: qcom: fix init problem with missing PARF programming Date: Thu, 2 Apr 2020 14:11:44 +0200 Message-Id: <20200402121148.1767-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com> References: <20200402121148.1767-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PARF programming was missing and this cause initilizzation problem on some ipq806x based device (Netgear R7800 for example). This cause a total lock of the system on kernel load. Fixes: 82a82383 PCI: qcom: Add Qualcomm PCIe controller driver Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 48 +++++++++++++++++++++----- 1 file changed, 39 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 211a1aa7d0f1..77b1ab7e23a3 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -46,6 +46,9 @@ #define PCIE20_PARF_PHY_CTRL 0x40 #define PCIE20_PARF_PHY_REFCLK 0x4C +#define REF_SSP_EN BIT(16) +#define REF_USE_PAD BIT(12) + #define PCIE20_PARF_DBI_BASE_ADDR 0x168 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 @@ -77,6 +80,18 @@ #define DBI_RO_WR_EN 1 #define PERST_DELAY_US 1000 +/* PARF registers */ +#define PCIE20_PARF_PCS_DEEMPH 0x34 +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) (x << 16) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) (x << 8) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) (x << 0) + +#define PCIE20_PARF_PCS_SWING 0x38 +#define PCS_SWING_TX_SWING_FULL(x) (x << 8) +#define PCS_SWING_TX_SWING_LOW(x) (x << 0) + +#define PCIE20_PARF_CONFIG_BITS 0x50 +#define PHY_RX0_EQ(x) (x << 24) #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 @@ -184,6 +199,16 @@ struct qcom_pcie { #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) +static inline void qcom_clear_and_set_dword(void __iomem *addr, + u32 clear_mask, u32 set_mask) +{ + u32 val = readl(addr); + + val &= ~clear_mask; + val |= set_mask; + writel(val, addr); +} + static void qcom_ep_reset_assert(struct qcom_pcie *pcie) { gpiod_set_value_cansleep(pcie->reset, 1); @@ -304,7 +329,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; - u32 val; int ret; ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); @@ -355,15 +379,21 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_deassert_ahb; } - /* enable PCIe clocks and resets */ - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); - val &= ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0); + + /* PARF programming */ + writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) | + PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) | + PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22), + pcie->parf + PCIE20_PARF_PCS_DEEMPH); + writel(PCS_SWING_TX_SWING_FULL(0x78) | + PCS_SWING_TX_SWING_LOW(0x78), + pcie->parf + PCIE20_PARF_PCS_SWING); + writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS); - /* enable external reference clock */ - val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); - val |= BIT(16); - writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); + /* enable reference clock */ + qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_REFCLK, + REF_USE_PAD, REF_SSP_EN); ret = reset_control_deassert(res->phy_reset); if (ret) { From patchwork Thu Apr 2 12:11:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 189771 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31134C2BA17 for ; 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[95.250.251.250]) by smtp.googlemail.com with ESMTPSA id w20sm1083611ejv.40.2020.04.02.05.12.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 05:12:18 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Sham Muthayyan , Ansuel Smith , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 10/10] PCIe: qcom: add Force GEN1 support Date: Thu, 2 Apr 2020 14:11:47 +0200 Message-Id: <20200402121148.1767-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com> References: <20200402121148.1767-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sham Muthayyan Add Force GEN1 support needed in some ipq806x board that needs to limit some pcie line to gen1 for some hardware limitation. This is set by the max-link-speed dts entry and needed by some soc based on ipq806x. (for example Netgear R7800 router) Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8047ac7dc8c7..2212e9498b91 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -27,6 +27,7 @@ #include #include +#include "../../pci.h" #include "pcie-designware.h" #define PCIE20_PARF_SYS_CTRL 0x00 @@ -99,6 +100,8 @@ #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0 + #define DEVICE_TYPE_RC 0x4 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 @@ -199,6 +202,7 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; const struct qcom_pcie_ops *ops; + bool force_gen1; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -441,6 +445,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) /* wait for clock acquisition */ usleep_range(1000, 1500); + if (pcie->force_gen1) { + writel_relaxed((readl_relaxed( + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1), + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); + } /* Set the Max TLP size to 2K, instead of using default of 4K */ @@ -1440,6 +1449,10 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } + ret = of_pci_get_max_link_speed(pdev->dev.of_node); + if (ret == 1) + pcie->force_gen1 = true; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf"); pcie->parf = devm_ioremap_resource(dev, res); if (IS_ERR(pcie->parf)) {