From patchwork Tue Apr 14 02:55:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sivaprakash Murugesan X-Patchwork-Id: 189614 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C4BEC2BA2B for ; Tue, 14 Apr 2020 02:55:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E88C720644 for ; Tue, 14 Apr 2020 02:55:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404247AbgDNCzd (ORCPT ); Mon, 13 Apr 2020 22:55:33 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:51909 "EHLO alexa-out-sd-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404233AbgDNCzb (ORCPT ); Mon, 13 Apr 2020 22:55:31 -0400 Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-01.qualcomm.com with ESMTP; 13 Apr 2020 19:55:29 -0700 Received: from sivaprak-linux.qualcomm.com ([10.201.3.202]) by ironmsg03-sd.qualcomm.com with ESMTP; 13 Apr 2020 19:55:25 -0700 Received: by sivaprak-linux.qualcomm.com (Postfix, from userid 459349) id 45E3B216B4; Tue, 14 Apr 2020 08:25:24 +0530 (IST) From: Sivaprakash Murugesan To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Sivaprakash Murugesan Subject: [PATCH V3 3/8] clk: qcom: Add A53 PLL support for ipq6018 devices Date: Tue, 14 Apr 2020 08:25:17 +0530 Message-Id: <1586832922-29191-4-git-send-email-sivaprak@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586832922-29191-1-git-send-email-sivaprak@codeaurora.org> References: <1586832922-29191-1-git-send-email-sivaprak@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The CPUs on Qualcomm IPQ6018 platform is primarily clocked by A53 PLL. This patch adds support for the A53 PLL on IPQ6018 devices which can support CPU frequencies above 1Ghz. Signed-off-by: Sivaprakash Murugesan --- drivers/clk/qcom/a53-pll.c | 136 ++++++++++++++++++++++++++++++++++++--------- 1 file changed, 111 insertions(+), 25 deletions(-) diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c index 45cfc57..a95351c 100644 --- a/drivers/clk/qcom/a53-pll.c +++ b/drivers/clk/qcom/a53-pll.c @@ -11,11 +11,40 @@ #include #include #include +#include #include "clk-pll.h" #include "clk-regmap.h" +#include "clk-alpha-pll.h" -static const struct pll_freq_tbl a53pll_freq[] = { +struct a53_alpha_pll { + struct alpha_pll_config *pll_config; + struct clk_alpha_pll *pll; +}; + +union a53pll { + struct clk_pll *pll; + struct a53_alpha_pll alpha_pll; +}; + +struct a53pll_data { +#define PLL_IS_ALPHA BIT(0) + u8 flags; + union a53pll a53pll; +}; + +static const u8 ipq_pll_offsets[] = { + [PLL_OFF_L_VAL] = 0x08, + [PLL_OFF_ALPHA_VAL] = 0x10, + [PLL_OFF_USER_CTL] = 0x18, + [PLL_OFF_CONFIG_CTL] = 0x20, + [PLL_OFF_CONFIG_CTL_U] = 0x24, + [PLL_OFF_STATUS] = 0x28, + [PLL_OFF_TEST_CTL] = 0x30, + [PLL_OFF_TEST_CTL_U] = 0x34, +}; + +static const struct pll_freq_tbl msm8996_a53pll_freq[] = { { 998400000, 52, 0x0, 0x1, 0 }, { 1094400000, 57, 0x0, 0x1, 0 }, { 1152000000, 62, 0x0, 0x1, 0 }, @@ -26,6 +55,64 @@ static const struct pll_freq_tbl a53pll_freq[] = { { } }; +static struct clk_pll msm8996_pll = { + .mode_reg = 0x0, + .l_reg = 0x04, + .m_reg = 0x08, + .n_reg = 0x0c, + .config_reg = 0x14, + .status_reg = 0x1c, + .status_bit = 16, + .freq_tbl = msm8996_a53pll_freq, + .clkr.hw.init = &(struct clk_init_data){ + .name = "a53pll", + .flags = CLK_IS_CRITICAL, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + .name = "xo", + }, + .num_parents = 1, + .ops = &clk_pll_sr2_ops, + }, +}; + +static struct clk_alpha_pll ipq6018_pll = { + .offset = 0x0, + .regs = ipq_pll_offsets, + .flags = SUPPORTS_DYNAMIC_UPDATE, + .clkr = { + .enable_reg = 0x0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "a53pll", + .flags = CLK_IS_CRITICAL, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static struct alpha_pll_config ipq6018_pll_config = { + .l = 0x37, + .config_ctl_val = 0x04141200, + .config_ctl_hi_val = 0x0, + .early_output_mask = BIT(3), + .main_output_mask = BIT(0), +}; + +static struct a53pll_data msm8996pll_data = { + .a53pll.pll = &msm8996_pll, +}; + +static struct a53pll_data ipq6018pll_data = { + .flags = PLL_IS_ALPHA, + .a53pll.alpha_pll.pll = &ipq6018_pll, + .a53pll.alpha_pll.pll_config = &ipq6018_pll_config, +}; + static const struct regmap_config a53pll_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -39,14 +126,16 @@ static int qcom_a53pll_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct regmap *regmap; struct resource *res; - struct clk_pll *pll; + const struct a53pll_data *pll_data; + struct clk_regmap *clkr; void __iomem *base; - struct clk_init_data init = { }; int ret; - pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); - if (!pll) - return -ENOMEM; + pll_data = of_device_get_match_data(dev); + if (!pll_data) { + dev_err(dev, "failed to get platform data\n"); + return -ENODEV; + } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(dev, res); @@ -57,30 +146,26 @@ static int qcom_a53pll_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - pll->l_reg = 0x04; - pll->m_reg = 0x08; - pll->n_reg = 0x0c; - pll->config_reg = 0x14; - pll->mode_reg = 0x00; - pll->status_reg = 0x1c; - pll->status_bit = 16; - pll->freq_tbl = a53pll_freq; - - init.name = "a53pll"; - init.parent_names = (const char *[]){ "xo" }; - init.num_parents = 1; - init.ops = &clk_pll_sr2_ops; - init.flags = CLK_IS_CRITICAL; - pll->clkr.hw.init = &init; - - ret = devm_clk_register_regmap(dev, &pll->clkr); + if (pll_data->flags & PLL_IS_ALPHA) { + struct clk_alpha_pll *alpha_pll = + pll_data->a53pll.alpha_pll.pll; + struct alpha_pll_config *alpha_pll_config = + pll_data->a53pll.alpha_pll.pll_config; + + clk_alpha_pll_configure(alpha_pll, regmap, alpha_pll_config); + clkr = &pll_data->a53pll.alpha_pll.pll->clkr; + } else { + clkr = &pll_data->a53pll.pll->clkr; + } + + ret = devm_clk_register_regmap(dev, clkr); if (ret) { dev_err(dev, "failed to register regmap clock: %d\n", ret); return ret; } ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, - &pll->clkr.hw); + &clkr->hw); if (ret) { dev_err(dev, "failed to add clock provider: %d\n", ret); return ret; @@ -90,7 +175,8 @@ static int qcom_a53pll_probe(struct platform_device *pdev) } static const struct of_device_id qcom_a53pll_match_table[] = { - { .compatible = "qcom,msm8916-a53pll" }, + { .compatible = "qcom,msm8916-a53pll", .data = &msm8996pll_data}, + { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018pll_data}, { } }; From patchwork Tue Apr 14 02:55:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sivaprakash Murugesan X-Patchwork-Id: 189612 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2577FC2BBFD for ; Tue, 14 Apr 2020 02:56:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0F50E20768 for ; Tue, 14 Apr 2020 02:56:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404295AbgDNC4U (ORCPT ); Mon, 13 Apr 2020 22:56:20 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:51914 "EHLO alexa-out-sd-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404250AbgDNCze (ORCPT ); Mon, 13 Apr 2020 22:55:34 -0400 Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-01.qualcomm.com with ESMTP; 13 Apr 2020 19:55:33 -0700 Received: from sivaprak-linux.qualcomm.com ([10.201.3.202]) by ironmsg03-sd.qualcomm.com with ESMTP; 13 Apr 2020 19:55:29 -0700 Received: by sivaprak-linux.qualcomm.com (Postfix, from userid 459349) id 698B5216B5; Tue, 14 Apr 2020 08:25:24 +0530 (IST) From: Sivaprakash Murugesan To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Sivaprakash Murugesan Subject: [PATCH V3 5/8] clk: qcom: Add ipq apss clock controller Date: Tue, 14 Apr 2020 08:25:19 +0530 Message-Id: <1586832922-29191-6-git-send-email-sivaprak@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586832922-29191-1-git-send-email-sivaprak@codeaurora.org> References: <1586832922-29191-1-git-send-email-sivaprak@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The CPU on Qualcomm's IPQ platform devices are clocked primarily by a PLL and xo which are connected to a mux and enable block, This patch adds support for the mux and the enable. Signed-off-by: Sivaprakash Murugesan --- drivers/clk/qcom/Kconfig | 10 +++++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apss-ipq.c | 107 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 118 insertions(+) create mode 100644 drivers/clk/qcom/apss-ipq.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 15cdcdc..8573f2e 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -89,6 +89,16 @@ config APQ_MMCC_8084 Say Y if you want to support multimedia devices such as display, graphics, video encode/decode, camera, etc. +config IPQ_APSS + tristate "IPQ APSS Clock Controller" + default N + help + Support for APSS clock controller on ipq platform devices. The + APSS clock controller manages the Mux and enable block that feeds the + CPUs. + Say Y if you want to support CPU frequency scaling on + ipq based devices. + config IPQ_GCC_4019 tristate "IPQ4019 Global Clock Controller" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 656a87e..1e4b296 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -19,6 +19,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o # Keep alphabetically sorted by config obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o +obj-$(CONFIG_IPQ_APSS) += apss-ipq.o obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o diff --git a/drivers/clk/qcom/apss-ipq.c b/drivers/clk/qcom/apss-ipq.c new file mode 100644 index 0000000..a37cd98 --- /dev/null +++ b/drivers/clk/qcom/apss-ipq.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "clk-regmap.h" +#include "clk-branch.h" +#include "clk-alpha-pll.h" +#include "clk-regmap-mux.h" + +enum { + P_XO, + P_APSS_PLL_EARLY, +}; + +static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { + { .fw_name = "xo" }, + { .fw_name = "pll" }, +}; + +static const struct parent_map parents_apcs_alias0_clk_src_map[] = { + { P_XO, 0 }, + { P_APSS_PLL_EARLY, 5 }, +}; + +static struct clk_regmap_mux apcs_alias0_clk_src = { + .reg = 0x0050, + .width = 3, + .shift = 7, + .parent_map = parents_apcs_alias0_clk_src_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "apcs_alias0_clk_src", + .parent_data = parents_apcs_alias0_clk_src, + .num_parents = 2, + .ops = &clk_regmap_mux_closest_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/*required for cpufreq*/ +static struct clk_branch apcs_alias0_core_clk = { + .halt_reg = 0x0058, + .clkr = { + .enable_reg = 0x0058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "apcs_alias0_core_clk", + .parent_hws = (const struct clk_hw *[]){ + &apcs_alias0_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static const struct regmap_config apss_ipq_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1000, + .fast_io = true, +}; + +static struct clk_regmap *apss_ipq_clks[] = { + [APCS_ALIAS0_CLK_SRC] = &apcs_alias0_clk_src.clkr, + [APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr, +}; + +static const struct qcom_cc_desc apss_ipq_desc = { + .config = &apss_ipq_regmap_config, + .clks = apss_ipq_clks, + .num_clks = ARRAY_SIZE(apss_ipq_clks), +}; + +static int apss_ipq_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return qcom_cc_really_probe(pdev, &apss_ipq_desc, regmap); +} + +static struct platform_driver apss_ipq_driver = { + .probe = apss_ipq_probe, + .driver = { + .name = "qcom,apss-ipq-clk", + }, +}; + +module_platform_driver(apss_ipq_driver); + +MODULE_DESCRIPTION("QCOM APSS IPQ CLK Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Tue Apr 14 02:55:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sivaprakash Murugesan X-Patchwork-Id: 189613 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 830D9C2BA2B for ; Tue, 14 Apr 2020 02:56:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 69AFF2072A for ; Tue, 14 Apr 2020 02:56:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404268AbgDNCzm (ORCPT ); Mon, 13 Apr 2020 22:55:42 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:51914 "EHLO alexa-out-sd-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404262AbgDNCzj (ORCPT ); Mon, 13 Apr 2020 22:55:39 -0400 Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-01.qualcomm.com with ESMTP; 13 Apr 2020 19:55:38 -0700 Received: from sivaprak-linux.qualcomm.com ([10.201.3.202]) by ironmsg04-sd.qualcomm.com with ESMTP; 13 Apr 2020 19:55:30 -0700 Received: by sivaprak-linux.qualcomm.com (Postfix, from userid 459349) id 9F17F216BB; Tue, 14 Apr 2020 08:25:24 +0530 (IST) From: Sivaprakash Murugesan To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Sivaprakash Murugesan Subject: [PATCH V3 7/8] mailbox: qcom: Add ipq6018 apcs compatible Date: Tue, 14 Apr 2020 08:25:21 +0530 Message-Id: <1586832922-29191-8-git-send-email-sivaprak@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586832922-29191-1-git-send-email-sivaprak@codeaurora.org> References: <1586832922-29191-1-git-send-email-sivaprak@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Qualcomm ipq6018 has apcs block, add compatible for the same. Also, the apcs provides a clock controller functionality similar to msm8916 but the clock driver is different. Create a child platform device based on the apcs compatible for the clock controller functionality. Signed-off-by: Sivaprakash Murugesan --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index eeebafd..19f6ba1 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -45,6 +45,16 @@ static const struct mbox_chan_ops qcom_apcs_ipc_ops = { .send_data = qcom_apcs_ipc_send_data, }; +static const struct of_device_id apcs_clk_match_table[] = { + { .compatible = "qcom,msm8916-apcs-kpss-global", + .data = "qcom-apcs-msm8916-clk", }, + { .compatible = "qcom,qcs404-apcs-apps-global", + .data = "qcom-apcs-msm8916-clk", }, + { .compatible = "qcom,ipq6018-apcs-apps-global", + .data = "qcom,apss-ipq-clk", }, + {} +}; + static int qcom_apcs_ipc_probe(struct platform_device *pdev) { struct qcom_apcs_ipc *apcs; @@ -54,11 +64,7 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev) void __iomem *base; unsigned long i; int ret; - const struct of_device_id apcs_clk_match_table[] = { - { .compatible = "qcom,msm8916-apcs-kpss-global", }, - { .compatible = "qcom,qcs404-apcs-apps-global", }, - {} - }; + const struct of_device_id *clk_device; apcs = devm_kzalloc(&pdev->dev, sizeof(*apcs), GFP_KERNEL); if (!apcs) @@ -93,9 +99,10 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev) return ret; } - if (of_match_device(apcs_clk_match_table, &pdev->dev)) { + clk_device = of_match_device(apcs_clk_match_table, &pdev->dev); + if (clk_device) { apcs->clk = platform_device_register_data(&pdev->dev, - "qcom-apcs-msm8916-clk", + (const char *)clk_device->data, PLATFORM_DEVID_NONE, NULL, 0); if (IS_ERR(apcs->clk)) @@ -127,6 +134,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 }, { .compatible = "qcom,sm8150-apss-shared", .data = (void *)12 }, { .compatible = "qcom,ipq8074-apcs-apps-global", .data = (void *)8 }, + { .compatible = "qcom,ipq6018-apcs-apps-global", .data = (void *)8 }, {} }; MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);