From patchwork Fri May 15 02:39:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandeep Maheswaram X-Patchwork-Id: 189126 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F702C433DF for ; Fri, 15 May 2020 02:40:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 847DB206D8 for ; Fri, 15 May 2020 02:40:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728245AbgEOCkB (ORCPT ); Thu, 14 May 2020 22:40:01 -0400 Received: from alexa-out-blr-01.qualcomm.com ([103.229.18.197]:31867 "EHLO alexa-out-blr-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728149AbgEOCkB (ORCPT ); Thu, 14 May 2020 22:40:01 -0400 Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by alexa-out-blr-01.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 May 2020 08:09:52 +0530 Received: from c-sanm-linux.qualcomm.com ([10.206.25.31]) by ironmsg01-blr.qualcomm.com with ESMTP; 15 May 2020 08:09:32 +0530 Received: by c-sanm-linux.qualcomm.com (Postfix, from userid 2343233) id 817CC29A7; Fri, 15 May 2020 08:09:31 +0530 (IST) From: Sandeep Maheswaram To: Andy Gross , Bjorn Andersson , Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Stephen Boyd , Doug Anderson , Matthias Kaehlcke Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manu Gautam , Sandeep Maheswaram Subject: [PATCH v7 2/4] dt-bindings: phy: qcom, qmp-usb3-dp: Add dt bindings for USB3 DP PHY Date: Fri, 15 May 2020 08:09:16 +0530 Message-Id: <1589510358-3865-3-git-send-email-sanm@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589510358-3865-1-git-send-email-sanm@codeaurora.org> References: <1589510358-3865-1-git-send-email-sanm@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Split out the dt bindings for USB3 DP PHY from qcom,qmp bindings for modularity. Signed-off-by: Sandeep Maheswaram --- .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 51 +++----- .../bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 135 +++++++++++++++++++++ 2 files changed, 150 insertions(+), 36 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index dcdb014..973b2d1 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -27,21 +27,13 @@ properties: - qcom,sdm845-qhp-pcie-phy - qcom,sdm845-qmp-pcie-phy - qcom,sdm845-qmp-ufs-phy - - qcom,sdm845-qmp-usb3-phy - qcom,sdm845-qmp-usb3-uni-phy - qcom,sm8150-qmp-ufs-phy - qcom,sm8250-qmp-ufs-phy reg: - minItems: 1 items: - description: Address and length of PHY's common serdes block. - - description: Address and length of the DP_COM control block. - - reg-names: - items: - - const: reg-base - - const: dp_com "#clock-cells": enum: [ 1, 2 ] @@ -110,7 +102,6 @@ allOf: compatible: contains: enum: - - qcom,sdm845-qmp-usb3-phy - qcom,sdm845-qmp-usb3-uni-phy then: properties: @@ -284,51 +275,39 @@ allOf: reset-names: items: - const: phy - - if: - properties: - compatible: - contains: - const: qcom,sdm845-qmp-usb3-phy - then: - required: - - reg-names examples: - | #include - usb_1_qmpphy: phy-wrapper@88e9000 { - compatible = "qcom,sdm845-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x10>; - reg-names = "reg-base", "dp_com"; + usb_2_qmpphy: phy-wrapper@88eb000 { + compatible = "qcom,sdm845-qmp-usb3-uni-phy"; + reg = <0 0x088eb000 0 0x18c>; #clock-cells = <1>; #address-cells = <2>; #size-cells = <2>; - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >, <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; clock-names = "aux", "cfg_ahb", "ref", "com_aux"; - resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, - <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; reset-names = "phy", "common"; vdda-phy-supply = <&vdda_usb2_ss_1p2>; vdda-pll-supply = <&vdda_usb2_ss_core>; - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x128>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x218>, - <0 0x088e9600 0 0x128>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; + usb_2_ssphy: phy@88eb200 { + reg = <0 0x088eb200 0 0x128>, + <0 0x088eb400 0 0x1fc>, + <0 0x088eb800 0 0x218>, + <0 0x088eb600 0 0x70>; #clock-cells = <0>; #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; }; }; diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml new file mode 100644 index 0000000..6055786 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm QMP USB3 DP PHY controller + +maintainers: + - Manu Gautam + +properties: + compatible: + const: + qcom,sdm845-qmp-usb3-phy + reg: + items: + - description: Address and length of PHY's common serdes block. + - description: Address and length of the DP_COM control block. + + reg-names: + items: + - const: reg-base + - const: dp_com + + "#clock-cells": + enum: [ 1, 2 ] + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + clocks: + items: + - description: Phy aux clock. + - description: Phy config clock. + - description: 19.2 MHz ref clk. + - description: Phy common block aux clock. + + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: com_aux + + resets: + items: + - description: reset of phy block. + - description: phy common block reset. + + reset-names: + items: + - const: phy + - const: common + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + + vddp-ref-clk-supply: + description: + Phandle to a regulator supply to any specific refclk + pll block. + +#Required nodes: +patternProperties: + "^phy@[0-9a-f]+$": + type: object + description: + Each device node of QMP phy is required to have as many child nodes as + the number of lanes the PHY has. + +required: + - compatible + - reg + - reg-names + - "#clock-cells" + - "#address-cells" + - "#size-cells" + - clocks + - clock-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include + usb_1_qmpphy: phy-wrapper@88e9000 { + compatible = "qcom,sdm845-qmp-usb3-phy"; + reg = <0 0x088e9000 0 0x18c>, + <0 0x088e8000 0 0x10>; + reg-names = "reg-base", "dp_com"; + #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "com_aux"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + vdda-phy-supply = <&vdda_usb2_ss_1p2>; + vdda-pll-supply = <&vdda_usb2_ss_core>; + + usb_1_ssphy: phy@88e9200 { + reg = <0 0x088e9200 0 0x128>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x218>, + <0 0x088e9600 0 0x128>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; + #clock-cells = <0>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + }; From patchwork Fri May 15 02:39:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandeep Maheswaram X-Patchwork-Id: 189125 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39281C433E0 for ; Fri, 15 May 2020 02:40:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 18E06206D8 for ; Fri, 15 May 2020 02:40:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728027AbgEOCj7 (ORCPT ); Thu, 14 May 2020 22:39:59 -0400 Received: from alexa-out-blr-01.qualcomm.com ([103.229.18.197]:31861 "EHLO alexa-out-blr-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726176AbgEOCj6 (ORCPT ); Thu, 14 May 2020 22:39:58 -0400 Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by alexa-out-blr-01.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 May 2020 08:09:52 +0530 Received: from c-sanm-linux.qualcomm.com ([10.206.25.31]) by ironmsg01-blr.qualcomm.com with ESMTP; 15 May 2020 08:09:35 +0530 Received: by c-sanm-linux.qualcomm.com (Postfix, from userid 2343233) id 48B4A29A7; Fri, 15 May 2020 08:09:34 +0530 (IST) From: Sandeep Maheswaram To: Andy Gross , Bjorn Andersson , Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Stephen Boyd , Doug Anderson , Matthias Kaehlcke Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manu Gautam , Sandeep Maheswaram Subject: [PATCH v7 4/4] phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180 Date: Fri, 15 May 2020 08:09:18 +0530 Message-Id: <1589510358-3865-5-git-send-email-sanm@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589510358-3865-1-git-send-email-sanm@codeaurora.org> References: <1589510358-3865-1-git-send-email-sanm@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Adding QMP v3 USB3 PHY support for SC7180. Adding only usb phy reset in the list to avoid reset of DP block. Signed-off-by: Sandeep Maheswaram Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd --- drivers/phy/qualcomm/phy-qcom-qmp.c | 38 +++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 5942167..3504931 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -1578,6 +1578,10 @@ static const char * const msm8996_usb3phy_reset_l[] = { "phy", "common", }; +static const char * const sc7180_usb3phy_reset_l[] = { + "phy", +}; + static const char * const sdm845_pciephy_reset_l[] = { "phy", }; @@ -1791,6 +1795,37 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { .is_dual_lane_phy = true, }; +static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = qmp_v3_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), + .tx_tbl = qmp_v3_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), + .rx_tbl = qmp_v3_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), + .pcs_tbl = qmp_v3_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), + .clk_list = qmp_v3_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), + .reset_list = sc7180_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v3_usb3phy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, +}; + static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { .type = PHY_TYPE_USB3, .nlanes = 1, @@ -2680,6 +2715,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { .compatible = "qcom,ipq8074-qmp-pcie-phy", .data = &ipq8074_pciephy_cfg, }, { + .compatible = "qcom,sc7180-qmp-usb3-phy", + .data = &sc7180_usb3phy_cfg, + }, { .compatible = "qcom,sdm845-qhp-pcie-phy", .data = &sdm845_qhp_pciephy_cfg, }, {