From patchwork Mon Jun 15 21:05:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 188461 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25A3DC433E3 for ; Mon, 15 Jun 2020 21:07:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 02599207D3 for ; Mon, 15 Jun 2020 21:07:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="g5NacBgI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731644AbgFOVGV (ORCPT ); Mon, 15 Jun 2020 17:06:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731143AbgFOVGU (ORCPT ); Mon, 15 Jun 2020 17:06:20 -0400 Received: from mail-ej1-x643.google.com (mail-ej1-x643.google.com [IPv6:2a00:1450:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7EC8DC061A0E; Mon, 15 Jun 2020 14:06:19 -0700 (PDT) Received: by mail-ej1-x643.google.com with SMTP id q19so18970722eja.7; Mon, 15 Jun 2020 14:06:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ny7VFcxsvYKg4f+n4WOuXVu12FivhYhgkhTSalaSq1o=; b=g5NacBgIxdFzpLhC9wXirlN9cuKXhuOjymYkv9LCeup3ZKh2QUAo2TwiGXysGLXCXw t+hJ1LPooMx/mx4Amd741IhzdH0M+egeJaO8efrt+yjB1dRxKXmh88Weun7FYV/dDRgY oCkr24DCknaoAilnpE9abK7/7/E6oxmELUsplz0l04/UPAereIO1OCjSoveo3GnHG7UC yRq/6cahvTU03jKNb+jW2K+01FGm28MYo6mnWGI8H6Ni+SkVQwwygPC49Ko4qV6ye0Ng CwQHy/BIUZv3qJqfWaGMdI0gjE+B/yI/FuoYGLnp+qmJd8d+5nLaTMeuHncZ/ZBGVm0x 83Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ny7VFcxsvYKg4f+n4WOuXVu12FivhYhgkhTSalaSq1o=; b=LO9+6t2ekc7v8Yj76yXDuXa4y8MEZ8AowrRTTDC0FWiC7HwA7BjTc285GYqRjJdS02 kgWy5lNYFCdicftDSHemySizXdiF8zY8ddBRcARNfAkSnNObH74thETsvNNmHgroplZE Qq2sixfkkHZmuA+z3Uz0mmjjbKEfyewXBHFyEfnpv1XN8vFnRrLWpwTX6Q5Ob/Xrjg+x V///+zj/wD4/MLd7I8oEHtRivRpwYfDcxb3jyR8rxf+LXVYi1asz1iAwCfg3ScmjUT6e LR6ItBTsvDh9U6an3KNVV+qgVuf3taoeL0AWmQ4ekDiDcIaIhRcd0A6zQHyqjZ5koign GsbA== X-Gm-Message-State: AOAM533QGycr/cl4PcvjCEiKCi69uNDBDpnctMdIzza1ixtZmhqL1BzU oj5kVa3Bdv8W2Bht1F9bDDI= X-Google-Smtp-Source: ABdhPJx3ixPAnnbaJyJLkyhgJVkLG92eNr147cfvyRIh/mdS9RocY6L78KcsY5XqUsDPrshmJvKJIQ== X-Received: by 2002:a17:906:86c5:: with SMTP id j5mr28474078ejy.88.1592255178156; Mon, 15 Jun 2020 14:06:18 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-95-238-254-39.retail.telecomitalia.it. [95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:17 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 02/12] dt-bindings: PCI: qcom: Add missing clks Date: Mon, 15 Jun 2020 23:05:58 +0200 Message-Id: <20200615210608.21469-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document missing clks used in ipq8064 SoC. Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 981b4de12807..becdbdc0fffa 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -90,6 +90,8 @@ Definition: Should contain the following entries - "core" Clocks the pcie hw block - "phy" Clocks the pcie PHY block + - "aux" Clocks the pcie AUX block + - "ref" Clocks the pcie ref block - clock-names: Usage: required for apq8084/ipq4019 Value type: @@ -277,8 +279,10 @@ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc PCIE_A_CLK>, <&gcc PCIE_H_CLK>, - <&gcc PCIE_PHY_CLK>; - clock-names = "core", "iface", "phy"; + <&gcc PCIE_PHY_CLK>, + <&gcc PCIE_AUX_CLK>, + <&gcc PCIE_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; resets = <&gcc PCIE_ACLK_RESET>, <&gcc PCIE_HCLK_RESET>, <&gcc PCIE_POR_RESET>, From patchwork Mon Jun 15 21:06:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 188501 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8BDFC433E1 for ; Mon, 15 Jun 2020 21:07:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9F2C4207D3 for ; Mon, 15 Jun 2020 21:07:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QdvSU7m/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731646AbgFOVGZ (ORCPT ); Mon, 15 Jun 2020 17:06:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730995AbgFOVGY (ORCPT ); Mon, 15 Jun 2020 17:06:24 -0400 Received: from mail-ej1-x643.google.com (mail-ej1-x643.google.com [IPv6:2a00:1450:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71F32C061A0E; Mon, 15 Jun 2020 14:06:24 -0700 (PDT) Received: by mail-ej1-x643.google.com with SMTP id l12so18935508ejn.10; Mon, 15 Jun 2020 14:06:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rLX+AzNeSNEPYCUgq95CzUacvnfDy5NOCzXpFKlNSv0=; b=QdvSU7m/o8PSzkFMBdzi+WQ590JV93QfBttTYeOddMasPz3pOkKug7Oqqk93D8oMwq Y+eE2U1ruKyg9Z+MoNC6qPes4qjS12EKKKxuLrP+mnQlCzly+cvzndJftnBbjWvIA2TY 3E/LkCf5qviSZFH/fy77VzwXJU32Dtfg64Ylu9wHee+H8ADJq3W899JAOkI48OdHcx8o gwAiFjyJj4B1IQLUJJlb546GBoU/OMLn/snBe0eMFnV0vJq0YYdjXYIaxMTMtEJSe1un DiMuifKhdnB+ZEFIGcXuVlSNHF3kQscr6BzHIjGxR2KNQzyuJ5dBwz8vl0f6vCCEbzdN VUiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rLX+AzNeSNEPYCUgq95CzUacvnfDy5NOCzXpFKlNSv0=; b=UYPFppkRQB50BBh4rQV+oHFRc/d/MwQ2YGfV6D8ovTYf3o5ZxTtGVzDNh5yTJATth6 tRToVHSpANNIcQqgpbE98F/ZEhpMssu39U8xTtgbqJEgYztWzmJtU8NoVhUF9Zl7oaSV H0kQ4tZj64wpL7jxRvjpNDzy8svDNpqDRCJT3LdtZzx38rvk4OoQJ0SHhsMMuwzqUTKj deyNj7EhOzuVgXK80Zyw9wI3kZOXL0Lg1kzk1/ZI3WC03U3dvCqOTXg9uNjk4QiTEYDR pfTHO/IMH/sRqkYH+yHheqOenRoJ8vaQXEl90Dc0zBMzdom6CcusLEX/1zTVZHa70Ndj 5kBw== X-Gm-Message-State: AOAM533ZbX9Pj4DluG7IOXV0ZbJwCtJYXsA1XfvtIi/PJOSctPEDtSqT U39gMOfwbk7H8/lbm4sBLfKwAiqmxbzkRrrU X-Google-Smtp-Source: ABdhPJwz82xWf7NwCjghgzyWXaDjnoL3k8r/qHOrHkeKWlQX4yBINS8dRzmaBSJlG5yvNO1J6OHPtg== X-Received: by 2002:a17:906:7103:: with SMTP id x3mr24660149ejj.363.1592255183076; Mon, 15 Jun 2020 14:06:23 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-95-238-254-39.retail.telecomitalia.it. [95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:22 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Ansuel Smith , Sham Muthayyan , stable@vger.kernel.org, Rob Herring , Philipp Zabel , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 04/12] PCI: qcom: Add missing reset for ipq806x Date: Mon, 15 Jun 2020 23:06:00 +0200 Message-Id: <20200615210608.21469-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing ext reset used by ipq8064 SoC in PCIe qcom driver. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith Cc: stable@vger.kernel.org # v4.5+ Reviewed-by: Rob Herring Reviewed-by: Philipp Zabel --- drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4512c2c5f61c..4dab5ef630cc 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 { struct reset_control *ahb_reset; struct reset_control *por_reset; struct reset_control *phy_reset; + struct reset_control *ext_reset; struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; }; @@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->por_reset)) return PTR_ERR(res->por_reset); + res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext"); + if (IS_ERR(res->ext_reset)) + return PTR_ERR(res->ext_reset); + res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); return PTR_ERR_OR_ZERO(res->phy_reset); } @@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); + reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); @@ -343,6 +349,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_deassert_ahb; } + ret = reset_control_deassert(res->ext_reset); + if (ret) { + dev_err(dev, "cannot deassert ext reset\n"); + goto err_deassert_ahb; + } + /* enable PCIe clocks and resets */ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); val &= ~BIT(0); From patchwork Mon Jun 15 21:06:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 188502 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96B9BC433E3 for ; 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[95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:27 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 06/12] PCI: qcom: Use bulk clk api and assert on error Date: Mon, 15 Jun 2020 23:06:02 +0200 Message-Id: <20200615210608.21469-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rework 2.1.0 revision to use bulk clk api and fix missing assert on reset_control_deassert error. Signed-off-by: Ansuel Smith Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 131 +++++++++---------------- 1 file changed, 46 insertions(+), 85 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4dab5ef630cc..f2ea1ab6f584 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -84,12 +84,9 @@ #define DEVICE_TYPE_RC 0x4 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 +#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 struct qcom_pcie_resources_2_1_0 { - struct clk *iface_clk; - struct clk *core_clk; - struct clk *phy_clk; - struct clk *aux_clk; - struct clk *ref_clk; + struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; struct reset_control *pci_reset; struct reset_control *axi_reset; struct reset_control *ahb_reset; @@ -237,25 +234,21 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (ret) return ret; - res->iface_clk = devm_clk_get(dev, "iface"); - if (IS_ERR(res->iface_clk)) - return PTR_ERR(res->iface_clk); - - res->core_clk = devm_clk_get(dev, "core"); - if (IS_ERR(res->core_clk)) - return PTR_ERR(res->core_clk); - - res->phy_clk = devm_clk_get(dev, "phy"); - if (IS_ERR(res->phy_clk)) - return PTR_ERR(res->phy_clk); + res->clks[0].id = "iface"; + res->clks[1].id = "core"; + res->clks[2].id = "phy"; + res->clks[3].id = "aux"; + res->clks[4].id = "ref"; - res->aux_clk = devm_clk_get_optional(dev, "aux"); - if (IS_ERR(res->aux_clk)) - return PTR_ERR(res->aux_clk); + /* iface, core, phy are required */ + ret = devm_clk_bulk_get(dev, 3, res->clks); + if (ret < 0) + return ret; - res->ref_clk = devm_clk_get_optional(dev, "ref"); - if (IS_ERR(res->ref_clk)) - return PTR_ERR(res->ref_clk); + /* aux, ref are optional */ + ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3); + if (ret < 0) + return ret; res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); if (IS_ERR(res->pci_reset)) @@ -285,17 +278,13 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; - clk_disable_unprepare(res->phy_clk); + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); reset_control_assert(res->pci_reset); reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); - clk_disable_unprepare(res->iface_clk); - clk_disable_unprepare(res->core_clk); - clk_disable_unprepare(res->aux_clk); - clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -313,36 +302,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return ret; } - ret = reset_control_assert(res->ahb_reset); - if (ret) { - dev_err(dev, "cannot assert ahb reset\n"); - goto err_assert_ahb; - } - - ret = clk_prepare_enable(res->iface_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable iface clock\n"); - goto err_assert_ahb; - } - - ret = clk_prepare_enable(res->core_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_core; - } - - ret = clk_prepare_enable(res->aux_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); - goto err_clk_aux; - } - - ret = clk_prepare_enable(res->ref_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable ref clock\n"); - goto err_clk_ref; - } - ret = reset_control_deassert(res->ahb_reset); if (ret) { dev_err(dev, "cannot deassert ahb reset\n"); @@ -352,48 +311,46 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) ret = reset_control_deassert(res->ext_reset); if (ret) { dev_err(dev, "cannot deassert ext reset\n"); - goto err_deassert_ahb; + goto err_deassert_ext; } - /* enable PCIe clocks and resets */ - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); - val &= ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); - - /* enable external reference clock */ - val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); - val |= BIT(16); - writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); - ret = reset_control_deassert(res->phy_reset); if (ret) { dev_err(dev, "cannot deassert phy reset\n"); - return ret; + goto err_deassert_phy; } ret = reset_control_deassert(res->pci_reset); if (ret) { dev_err(dev, "cannot deassert pci reset\n"); - return ret; + goto err_deassert_pci; } ret = reset_control_deassert(res->por_reset); if (ret) { dev_err(dev, "cannot deassert por reset\n"); - return ret; + goto err_deassert_por; } ret = reset_control_deassert(res->axi_reset); if (ret) { dev_err(dev, "cannot deassert axi reset\n"); - return ret; + goto err_deassert_axi; } - ret = clk_prepare_enable(res->phy_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable phy clock\n"); - goto err_deassert_ahb; - } + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + if (ret) + goto err_clks; + + /* enable PCIe clocks and resets */ + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val &= ~BIT(0); + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + + /* enable external reference clock */ + val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); + val |= BIT(16); + writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); /* wait for clock acquisition */ usleep_range(1000, 1500); @@ -407,15 +364,19 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return 0; +err_clks: + reset_control_assert(res->axi_reset); +err_deassert_axi: + reset_control_assert(res->por_reset); +err_deassert_por: + reset_control_assert(res->pci_reset); +err_deassert_pci: + reset_control_assert(res->phy_reset); +err_deassert_phy: + reset_control_assert(res->ext_reset); +err_deassert_ext: + reset_control_assert(res->ahb_reset); err_deassert_ahb: - clk_disable_unprepare(res->ref_clk); -err_clk_ref: - clk_disable_unprepare(res->aux_clk); -err_clk_aux: - clk_disable_unprepare(res->core_clk); -err_clk_core: - clk_disable_unprepare(res->iface_clk); -err_assert_ahb: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); return ret; From patchwork Mon Jun 15 21:06:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 188503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7700FC433DF for ; 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[95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:34 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 09/12] PCI: qcom: Add ipq8064 rev2 variant Date: Mon, 15 Jun 2020 23:06:05 +0200 Message-Id: <20200615210608.21469-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Ipq8064-v2 have tx term offset set to 0. Introduce this variant to permit different offset based on the revision. Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 2cd6d1456210..259b627bf890 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -366,7 +366,8 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) val &= ~BIT(0); writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); - if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { + if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || + of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) | PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34), @@ -1464,6 +1465,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 }, { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 }, + { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 }, { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 }, { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 }, { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 }, From patchwork Mon Jun 15 21:06:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 188504 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75C6AC433E1 for ; Mon, 15 Jun 2020 21:06:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 51FFB2078E for ; Mon, 15 Jun 2020 21:06:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dkzP8Jq0" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731777AbgFOVG4 (ORCPT ); Mon, 15 Jun 2020 17:06:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731661AbgFOVGl (ORCPT ); Mon, 15 Jun 2020 17:06:41 -0400 Received: from mail-ej1-x643.google.com (mail-ej1-x643.google.com [IPv6:2a00:1450:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B885C061A0E; Mon, 15 Jun 2020 14:06:41 -0700 (PDT) Received: by mail-ej1-x643.google.com with SMTP id o15so18949132ejm.12; Mon, 15 Jun 2020 14:06:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qk9kJyl6xBs7NFHSty0oErpx4zGo0ReUFZlbaqRNYPs=; b=dkzP8Jq0x2fUTU2b/tFozk9+Wun/+haYoHAexmI0WJHmv809aW5/yvxZ1GypsufitD 3NlVoyV5/l61fORMPFRcytjQykeS5IAHtjgHdqgb8DNVhwiKGUWcsHOzex5bKPrELkmj lD1AzH70nmiAYLOF+Kmn6mL2NOXaIWX8xc5YCYpWUhFStBfMO96BovNv2rwBRjTSGo6r HnaxRnnkD/JyGYvYT15MQN8UNI8uL/9npOHFQH/NH0Uh9mteI+ayy+JT3gAQP7+TscCK HoSA6Lfu2WlKWkIsPhNwxULBoJH7Ixf4fVEwQVnkaKM6qpBWfsLbkw+lB1NTPrZdFrQF BOLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qk9kJyl6xBs7NFHSty0oErpx4zGo0ReUFZlbaqRNYPs=; b=t3PcV21CO6atk3WmJMEfPEl86rexizePn06bPnKPLEU/Vr6nRqk+fcBCTx1dPxHFcu nasgEPtLOoqSQbagE5cQy1EyWuFSAa7BU66A+rTvi8xdiO7vEXGu/4MawvI4+3+yDdMc VeMqvJrCbHAAKcsT/axGSr3rftxFeud6aFDActaFM5HJTb+wMuvIgyGms0cwyN+kV1Wm sninM8CNqCArn3VshSHxjg8oTdlthuFWX3Qv2i0uZrxiwUPUqrDYP5RRZfnWOhxOjswG DCHcVyWKwGysJgvPNYgZM/p3xIk1QSGW8z0X18H9u5KgA1hsPXXjgu0W7Jdg7kQFj4ad C7AA== X-Gm-Message-State: AOAM533t78lwLak31uj+EOLWNzFHrsF6yXWrPTJlfKzTWVUcgqZrg2pW HlXMWDjQbRIiqcFr7vWDdgw= X-Google-Smtp-Source: ABdhPJyc4yxO4q5FGFJ0IFqE2jFCbHKF/8kBv0fGSC41jRkaEwAla+s9I7WWysulTAldPZOp6frCsA== X-Received: by 2002:a17:906:2581:: with SMTP id m1mr8061904ejb.89.1592255199974; Mon, 15 Jun 2020 14:06:39 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-95-238-254-39.retail.telecomitalia.it. [95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:39 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Sham Muthayyan , Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 11/12] PCI: qcom: Support pci speed set for ipq806x Date: Mon, 15 Jun 2020 23:06:07 +0200 Message-Id: <20200615210608.21469-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sham Muthayyan Some SoC based on ipq8064/5 needs to be limited to pci GEN1 speed due to some hardware limitations. Add support for speed setting defined by the max-link-speed binding. If not defined the max speed is set to GEN2 by default. Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 259b627bf890..c40921589122 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -27,6 +27,7 @@ #include #include +#include "../../pci.h" #include "pcie-designware.h" #define PCIE20_PARF_SYS_CTRL 0x00 @@ -99,6 +100,8 @@ #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0 + #define DEVICE_TYPE_RC 0x4 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 @@ -195,6 +198,7 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; const struct qcom_pcie_ops *ops; + int gen; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -395,6 +399,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) /* wait for clock acquisition */ usleep_range(1000, 1500); + if (pcie->gen == 1) { + val = readl(pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); + val |= PCI_EXP_LNKSTA_CLS_2_5GB; + writel(val, pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); + } /* Set the Max TLP size to 2K, instead of using default of 4K */ writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K, @@ -1397,6 +1406,10 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } + pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node); + if (pcie->gen < 0) + pcie->gen = 2; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf"); pcie->parf = devm_ioremap_resource(dev, res); if (IS_ERR(pcie->parf)) { From patchwork Mon Jun 15 21:06:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 188505 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA4D7C433DF for ; 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[95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:41 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 12/12] PCI: qcom: Replace define with standard value Date: Mon, 15 Jun 2020 23:06:08 +0200 Message-Id: <20200615210608.21469-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Lots of define are actually already defined in pci_regs.h, directly use the standard defines. Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index c40921589122..a23d3d886479 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -40,11 +40,6 @@ #define L23_CLK_RMV_DIS BIT(2) #define L1_CLK_RMV_DIS BIT(1) -#define PCIE20_COMMAND_STATUS 0x04 -#define CMD_BME_VAL 0x4 -#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98 -#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10 - #define PCIE20_PARF_PHY_CTRL 0x40 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) @@ -73,8 +68,8 @@ #define CFG_BRIDGE_SB_INIT BIT(0) #define PCIE20_CAP 0x70 -#define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + 0xC) -#define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) | BIT(11)) +#define PCIE20_DEVICE_CONTROL2_STATUS2 (PCIE20_CAP + PCI_EXP_DEVCTL2) +#define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + PCI_EXP_LNKCAP) #define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14) #define PCIE_CAP_LINK1_VAL 0x2FD7F @@ -1095,15 +1090,15 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) pcie->parf + PCIE20_PARF_SYS_CTRL); writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH); - writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS); + writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG); writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1); val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); - val &= ~PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT; + val &= ~PCI_EXP_LNKCAP_ASPMS; writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); - writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base + + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + PCIE20_DEVICE_CONTROL2_STATUS2); return 0;