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Sat, 07 Jun 2025 18:03:44 -0700 (PDT) Received: from localhost ([2804:14d:7e39:88d6:8cb1:1e8e:e951:f687]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-530e6427ad8sm2969037e0c.43.2025.06.07.18.03.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jun 2025 18:03:44 -0700 (PDT) From: Thiago Jung Bauermann To: gdb-patches@sourceware.org Subject: [PATCH 1/8] bfd/aarch64-linux: Support reading and writing the GCS core file note Date: Sat, 7 Jun 2025 22:03:12 -0300 Message-ID: <20250608010338.2234530-2-thiago.bauermann@linaro.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250608010338.2234530-1-thiago.bauermann@linaro.org> References: <20250608010338.2234530-1-thiago.bauermann@linaro.org> MIME-Version: 1.0 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~patch=linaro.org@sourceware.org --- bfd/elf.c | 31 +++++++++++++++++++++++++++++++ include/elf/common.h | 3 +++ 2 files changed, 34 insertions(+) I just posted this patch to the binutils mailing list. I'm including it in this series for completeness. diff --git a/bfd/elf.c b/bfd/elf.c index 3073f860621f..6a6b3f1bb9ee 100644 --- a/bfd/elf.c +++ b/bfd/elf.c @@ -10629,6 +10629,15 @@ elfcore_grok_aarch_zt (bfd *abfd, Elf_Internal_Note *note) return elfcore_make_note_pseudosection (abfd, ".reg-aarch-zt", note); } +/* Convert NOTE into a bfd_section called ".reg-aarch-gcs". Return TRUE if + successful, otherwise return FALSE. */ + +static bool +elfcore_grok_aarch_gcs (bfd *abfd, Elf_Internal_Note *note) +{ + return elfcore_make_note_pseudosection (abfd, ".reg-aarch-gcs", note); +} + static bool elfcore_grok_arc_v2 (bfd *abfd, Elf_Internal_Note *note) { @@ -11372,6 +11381,12 @@ elfcore_grok_note (bfd *abfd, Elf_Internal_Note *note) else return true; + case NT_ARM_GCS: + if (note->namesz == 6 && strcmp (note->namedata, "LINUX") == 0) + return elfcore_grok_aarch_gcs (abfd, note); + else + return true; + case NT_GDB_TDESC: if (note->namesz == 4 && strcmp (note->namedata, "GDB") == 0) @@ -13042,6 +13057,20 @@ elfcore_write_aarch_zt (bfd *abfd, size); } +/* Write the buffer of GCS register values in AARCH_GCS (length SIZE) into + the note buffer BUF and update *BUFSIZ. ABFD is the bfd the note is being + written into. Return a pointer to the new start of the note buffer, to + replace BUF which may no longer be valid. */ + +static char * +elfcore_write_aarch_gcs (bfd *abfd, char *buf, int *bufsiz, + const void *aarch_gcs, int size) +{ + const char *note_name = "LINUX"; + return elfcore_write_note (abfd, buf, bufsiz, note_name, NT_ARM_GCS, + aarch_gcs, size); +} + char * elfcore_write_arc_v2 (bfd *abfd, char *buf, @@ -13231,6 +13260,8 @@ elfcore_write_register_note (bfd *abfd, return elfcore_write_aarch_za (abfd, buf, bufsiz, data, size); if (strcmp (section, ".reg-aarch-zt") == 0) return elfcore_write_aarch_zt (abfd, buf, bufsiz, data, size); + if (strcmp (section, ".reg-aarch-gcs") == 0) + return elfcore_write_aarch_gcs (abfd, buf, bufsiz, data, size); if (strcmp (section, ".reg-arc-v2") == 0) return elfcore_write_arc_v2 (abfd, buf, bufsiz, data, size); if (strcmp (section, ".gdb-tdesc") == 0) diff --git a/include/elf/common.h b/include/elf/common.h index fd032d1e03ed..f4b543b353ac 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -740,6 +740,9 @@ /* Note: name must be "LINUX". */ #define NT_ARM_ZT 0x40d /* AArch64 SME2 ZT registers. */ /* Note: name must be "LINUX". */ +#define NT_ARM_GCS 0x410 /* AArch64 Guarded Control Stack + registers. */ + /* Note name must be "LINUX". */ #define NT_ARC_V2 0x600 /* ARC HS accumulator/extra registers. */ /* note name must be "LINUX". */ #define NT_LARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ From patchwork Sun Jun 8 01:03:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thiago Jung Bauermann X-Patchwork-Id: 894803 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:ecd:b0:3a4:ee3f:8f15 with SMTP id ea13csp1175896wrb; Sat, 7 Jun 2025 18:07:09 -0700 (PDT) X-Forwarded-Encrypted: i=3; AJvYcCWp90A02np+kJ1yc+MOWGnWTPXMNTt9uunKzXLEaAjsuPj5EIr+N3CBrw7ps6eHiTk5hddAQg==@linaro.org X-Google-Smtp-Source: AGHT+IG00IEiaEm44hamPkyfa5JU3bCQ3b+/jojskkdNyFDBWx5CQ9J+OYeF7a6KObGKy9T9RDBb X-Received: by 2002:a05:620a:2688:b0:7ce:f14b:d7d9 with SMTP id af79cd13be357-7d22986ec69mr1568914785a.22.1749344829656; Sat, 07 Jun 2025 18:07:09 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1749344829; cv=pass; d=google.com; s=arc-20240605; b=SBHLuiszOqFVu3ob7BBNYo/y5W0E5ZPy7wp/U7QtFZzhmrOXHAZwzkf14f2WBaWRuu WJv1tlEp9faXZ0wPp72g5uY+XtMbUw2fO6cLWv9G/5IPBX5ygHVymdwYvtb8XLhpX2nL UzJ5+zq+e2C0pzwYWdTuyRCJ2Q8e18htBA5Z49NDkGrZkn+VAj1w64dlEmb81oG/Ihf3 smRNEIht71v1JZw1DIUX1R81IsQ9HBAyS3YKQRZyCSAOrfURGDhRv5HZu94m3IWATut1 BmUu1G4j2I2LTF5JitpxUJnhDEeLjn4l4UutVCsUw+nHR6CJI/LNDFEygh0YqJBXWwrS uZrA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:dkim-filter:arc-filter:dmarc-filter:delivered-to :dkim-filter; bh=wDu6MvCCOtd91FGS61CaECSwEA9ZPfjZTWyLJ53ko7Q=; fh=72kqq0iQhigvR9Vv/oqX5ebs3Yyyw7XhzWxOOEPdupI=; b=lUyrVK7CT5J+tWaFa1wNBzGNj7Xs5nyS3g6ZEzDUnXrSXQPvDdiYwb2dKXow1aOv0b 96AYFro/dFMBWxYtrvqOSMGhaby6x1Be6/8Pucm9PrPfMtqczCxVczWQTPfJp+qQgIYB CDs27VdQPTiO7FFlr/iI6IZ1VlllMrDUQEwlkcvCMx6qvSxCvk8S+HkLkfryVh7n8Tjy DwVUin7j2sv+Ty9mzJQDrdM6b6lR7/unkHTESsPU2IqplqtirRlQkSx43wJlvv69rneV eA/c0FdOF/Yz35rm/fQjCbNbn9qk5xMkWwMTG9xTzREBOANHTW/80tfizIiGzxr7tRK2 x6SQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SkluK42I; arc=pass (i=1); spf=pass (google.com: domain of gdb-patches-bounces~patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gdb-patches-bounces~patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. 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They all start with "AArch64", which IMHO is redundant information. 2. They all end with a period, which looks strange to me. Also, fix a couple of issues with their @cindex tags: 1. Some of them also end with a period, which I don't think is common practice. 2. Sometimes there are tags for the feature abbreviation, and sometimes there aren't. Add them if they're missing. Similarly, in the Target Description section, under the Standard Target Features subsection, the subsubsection titles for the AArch64 and ARM features have the word "feature" in the title and the AArch64 ones have the word "AArch64". Remove them. Reviewed-By: Eli Zaretskii --- gdb/doc/gdb.texinfo | 51 ++++++++++++++++++++++++--------------------- 1 file changed, 27 insertions(+), 24 deletions(-) diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index 6c67734fd046..c7b57cf22505 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -26630,8 +26630,9 @@ Show whether AArch64 debugging messages are displayed. @end table -@subsubsection AArch64 SVE. -@cindex AArch64 SVE. +@subsubsection Scalable Vector Extension +@cindex AArch64 SVE +@cindex AArch64 Scalable Vector Extension When @value{GDBN} is debugging the AArch64 architecture, if the Scalable Vector Extension (SVE) is present, then @value{GDBN} will provide the vector registers @@ -26670,7 +26671,7 @@ internally by @value{GDBN} and the Linux Kernel. @end itemize -@subsubsection AArch64 SME. +@subsubsection Scalable Matrix Extension @anchor{AArch64 SME} @cindex SME @cindex AArch64 SME @@ -26866,7 +26867,7 @@ incorrect values for SVE registers (when in streaming mode). This is the same limitation we have for the @acronym{SVE} registers, and there are plans to address this limitation going forward. -@subsubsection AArch64 SME2. +@subsubsection Scalable Matrix Extension 2 @anchor{AArch64 SME2} @cindex SME2 @cindex AArch64 SME2 @@ -26910,8 +26911,9 @@ For more information about @acronym{SME2}, please refer to the official @url{https://developer.arm.com/documentation/ddi0487/latest, architecture documentation}. -@subsubsection AArch64 Pointer Authentication. -@cindex AArch64 Pointer Authentication. +@subsubsection Pointer Authentication +@cindex AArch64 PAC +@cindex AArch64 Pointer Authentication @anchor{AArch64 PAC} When @value{GDBN} is debugging the AArch64 architecture, and the program is @@ -26921,8 +26923,9 @@ When GDB prints a backtrace, any addresses that required unmasking will be postfixed with the marker [PAC]. When using the MI, this is printed as part of the @code{addr_flags} field. -@subsubsection AArch64 Memory Tagging Extension. -@cindex AArch64 Memory Tagging Extension. +@subsubsection Memory Tagging Extension +@cindex AArch64 MTE +@cindex AArch64 Memory Tagging Extension When @value{GDBN} is debugging the AArch64 architecture, the program is using the v8.5-A feature Memory Tagging Extension (MTE) and there is support @@ -49368,7 +49371,7 @@ registers using the capitalization used in the description. @subsection AArch64 Features @cindex target descriptions, AArch64 features -@subsubsection AArch64 core registers feature +@subsubsection Core registers The @samp{org.gnu.gdb.aarch64.core} feature is required for AArch64 targets. It must contain the following: @@ -49396,7 +49399,7 @@ aarch64-core.xml file. Extra registers are allowed in this feature, but they will not affect @value{GDBN}. -@subsubsection AArch64 floating-point registers feature +@subsubsection Floating-point registers The @samp{org.gnu.gdb.aarch64.fpu} feature is optional. If present, it must contain the following registers: @@ -49422,7 +49425,7 @@ be found in the aarch64-fpu.xml file. Extra registers are allowed in this feature, but they will not affect @value{GDBN}. -@subsubsection AArch64 SVE registers feature +@subsubsection SVE registers The @samp{org.gnu.gdb.aarch64.sve} feature is optional. If present, it means the target supports the Scalable Vector Extension and must contain @@ -49476,7 +49479,7 @@ aarch64-sve.c file, and should match what is described in aarch64-fpu.xml. Extra registers are allowed in this feature, but they will not affect @value{GDBN}. -@subsubsection AArch64 Pointer Authentication registers feature +@subsubsection Pointer Authentication registers The @samp{org.gnu.gdb.aarch64.pauth} optional feature was introduced so @value{GDBN} could detect support for the Pointer Authentication @@ -49543,7 +49546,7 @@ Authentication support via the @samp{org.gnu.gdb.aarch64.pauth} feature string and also report additional registers the older @value{GDBN} does not know about, potentially leading to a crash. -@subsubsection AArch64 TLS registers feature +@subsubsection TLS registers The @samp{org.gnu.gdb.aarch64.tls} optional feature was introduced to expose the TLS registers to @value{GDBN}. If present, it must contain either one @@ -49579,7 +49582,7 @@ determined dynamically at runtime. Extra registers are allowed in this feature, but they will not affect @value{GDBN}. -@subsubsection AArch64 MTE registers feature +@subsubsection MTE registers The @samp{org.gnu.gdb.aarch64.mte} optional feature was introduced so @value{GDBN} could detect support for the Memory Tagging Extension and @@ -49600,7 +49603,7 @@ This restriction may be lifted in the future. Extra registers are allowed in this feature, but they will not affect @value{GDBN}. -@subsubsection AArch64 SME registers feature +@subsubsection SME registers The @samp{org.gnu.gdb.aarch64.sme} feature is optional. If present, it should contain registers @code{ZA}, @code{SVG} and @code{SVCR}. @@ -49634,7 +49637,7 @@ Extra registers are allowed in this feature, but they will not affect The @samp{org.gnu.gdb.aarch64.sme} feature is required when the target also reports support for the @samp{org.gnu.gdb.aarch64.sme2} feature. -@subsubsection AArch64 SME2 registers feature +@subsubsection SME2 registers The @samp{org.gnu.gdb.aarch64.sme2} feature is optional. If present, then the @samp{org.gnu.gdb.aarch64.sme} feature must also be present. The @@ -49762,7 +49765,7 @@ configurations that are meaningful to M-profiles. Extra registers are allowed in this feature, but they will not affect @value{GDBN}. -@subsubsection FPA registers feature (obsolete) +@subsubsection FPA registers (obsolete) The @samp{org.gnu.gdb.arm.fpa} feature is obsolete and should not be advertised by debugging stubs anymore. It used to advertise registers for @@ -49817,7 +49820,7 @@ contents. Extra registers are allowed in this feature, but they will not affect @value{GDBN}. -@subsubsection XScale iwMMXt feature +@subsubsection XScale iwMMXt The XScale @samp{org.gnu.gdb.xscale.iwmmxt} feature is optional. If present, it must contain the following: @@ -49851,7 +49854,7 @@ This feature should only be reported if the target is XScale. Extra registers are allowed in this feature, but they will not affect @value{GDBN}. -@subsubsection Vector Floating-Point (VFP) feature +@subsubsection Vector Floating-Point (VFP) The @samp{org.gnu.gdb.arm.vfp} feature is optional. If present, it should contain one of two possible sets of values depending on whether @@ -49886,7 +49889,7 @@ registers as pseudo-registers. Extra registers are allowed in this feature, but they will not affect @value{GDBN}. -@subsubsection NEON architecture feature +@subsubsection NEON architecture The @samp{org.gnu.gdb.arm.neon} feature is optional. It does not need to contain registers; it instructs @value{GDBN} to display the @@ -49898,7 +49901,7 @@ be present and include 32 double-precision registers. Extra registers are allowed in this feature, but they will not affect @value{GDBN}. -@subsubsection M-profile Pointer Authentication and Branch Target Identification feature +@subsubsection M-profile Pointer Authentication and Branch Target Identification The @samp{org.gnu.gdb.arm.m-profile-pacbti} feature is optional, and acknowledges support for the ARMv8.1-m PACBTI extensions. @@ -49915,7 +49918,7 @@ AArch64's PAC extension. Extra registers are allowed in this feature, but they will not affect @value{GDBN}. -@subsubsection M-profile system registers feature +@subsubsection M-profile system registers The @samp{org.gnu.gdb.arm.m-system} optional feature was introduced as a way to inform @value{GDBN} about additional system registers. @@ -49938,7 +49941,7 @@ sees this feature, it will attempt to track the values of @samp{msp} and Extra registers are allowed in this feature, but they will not affect @value{GDBN}. -@subsubsection M-profile Security Extensions feature +@subsubsection M-profile Security Extensions The @samp{org.gnu.gdb.arm.secext} optional feature was introduced so @value{GDBN} could better support the switching of stack pointers and @@ -49968,7 +49971,7 @@ unwinding when applications switch between security states. Extra registers are allowed in this feature, but they will not affect @value{GDBN}. -@subsubsection TLS registers feature +@subsubsection TLS registers The optional @samp{org.gnu.gdb.arm.tls} feature contains TLS registers. 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Sat, 07 Jun 2025 18:03:51 -0700 (PDT) Received: from localhost ([2804:14d:7e39:88d6:8cb1:1e8e:e951:f687]) by smtp.gmail.com with ESMTPSA id ada2fe7eead31-4e77391ee00sm3127237137.15.2025.06.07.18.03.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jun 2025 18:03:51 -0700 (PDT) From: Thiago Jung Bauermann To: gdb-patches@sourceware.org Subject: [PATCH 3/8] GDB, gdbserver: aarch64-linux: Initial Guarded Control Stack support Date: Sat, 7 Jun 2025 22:03:14 -0300 Message-ID: <20250608010338.2234530-4-thiago.bauermann@linaro.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250608010338.2234530-1-thiago.bauermann@linaro.org> References: <20250608010338.2234530-1-thiago.bauermann@linaro.org> MIME-Version: 1.0 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~patch=linaro.org@sourceware.org Add the org.gnu.gdb.aarch64.gcs feature with the GCSPR register, and the org.gnu.gdb.aarch64.gcs.linux feature with "registers" to represent the Linux kernel ptrace and prctl knobs that enable and lock specific GCS functionality. --- gdb/aarch64-linux-nat.c | 79 ++++++++++++++++++++++ gdb/aarch64-linux-tdep.c | 23 +++++++ gdb/aarch64-tdep.c | 101 +++++++++++++++++++++++++++++ gdb/aarch64-tdep.h | 14 ++++ gdb/arch/aarch64-gcs-linux.h | 44 +++++++++++++ gdb/arch/aarch64.c | 8 +++ gdb/arch/aarch64.h | 10 ++- gdb/doc/gdb.texinfo | 51 +++++++++++++++ gdb/features/Makefile | 2 + gdb/features/aarch64-gcs-linux.c | 21 ++++++ gdb/features/aarch64-gcs-linux.xml | 18 +++++ gdb/features/aarch64-gcs.c | 14 ++++ gdb/features/aarch64-gcs.xml | 11 ++++ gdbserver/linux-aarch64-low.cc | 46 +++++++++++++ 14 files changed, 441 insertions(+), 1 deletion(-) create mode 100644 gdb/arch/aarch64-gcs-linux.h create mode 100644 gdb/features/aarch64-gcs-linux.c create mode 100644 gdb/features/aarch64-gcs-linux.xml create mode 100644 gdb/features/aarch64-gcs.c create mode 100644 gdb/features/aarch64-gcs.xml diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c index d7869f42e825..0796b1e47955 100644 --- a/gdb/aarch64-linux-nat.c +++ b/gdb/aarch64-linux-nat.c @@ -51,6 +51,7 @@ #include "gdb_proc_service.h" #include "arch-utils.h" +#include "arch/aarch64-gcs-linux.h" #include "arch/aarch64-mte-linux.h" #include "nat/aarch64-mte-linux-ptrace.h" @@ -542,6 +543,67 @@ store_tlsregs_to_thread (struct regcache *regcache) perror_with_name (_("unable to store TLS register")); } +/* Fill GDB's register array with the GCS register values from + the current thread. */ + +static void +fetch_gcsregs_from_thread (struct regcache *regcache) +{ + aarch64_gdbarch_tdep *tdep + = gdbarch_tdep (regcache->arch ()); + + gdb_assert (tdep->gcs_reg_base != -1); + gdb_assert (tdep->gcs_linux_reg_base != -1); + + struct user_gcs user_gcs; + struct iovec iovec; + + iovec.iov_base = &user_gcs; + iovec.iov_len = sizeof (user_gcs); + + int tid = get_ptrace_pid (regcache->ptid ()); + if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_GCS, &iovec) != 0) + perror_with_name (_("unable to fetch GCS registers")); + + regcache->raw_supply (tdep->gcs_reg_base, &user_gcs.gcspr_el0); + regcache->raw_supply (tdep->gcs_linux_reg_base, &user_gcs.features_enabled); + regcache->raw_supply (tdep->gcs_linux_reg_base + 1, + &user_gcs.features_locked); +} + +/* Store to the current thread the valid GCS register set in the GDB's + register array. */ + +static void +store_gcsregs_to_thread (struct regcache *regcache) +{ + aarch64_gdbarch_tdep *tdep + = gdbarch_tdep (regcache->arch ()); + + gdb_assert (tdep->gcs_reg_base != -1); + gdb_assert (tdep->gcs_linux_reg_base != -1); + + if (REG_VALID != regcache->get_register_status (tdep->gcs_reg_base) + || REG_VALID != regcache->get_register_status (tdep->gcs_linux_reg_base) + || REG_VALID + != regcache->get_register_status (tdep->gcs_linux_reg_base + 1)) + return; + + struct user_gcs user_gcs; + regcache->raw_collect (tdep->gcs_reg_base, &user_gcs.gcspr_el0); + regcache->raw_collect (tdep->gcs_linux_reg_base, &user_gcs.features_enabled); + regcache->raw_collect (tdep->gcs_linux_reg_base + 1, + &user_gcs.features_locked); + + struct iovec iovec; + iovec.iov_base = &user_gcs; + iovec.iov_len = sizeof (user_gcs); + + int tid = get_ptrace_pid (regcache->ptid ()); + if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_GCS, &iovec) != 0) + perror_with_name (_("unable to store GCS registers")); +} + /* The AArch64 version of the "fetch_registers" target_ops method. Fetch REGNO from the target and place the result into REGCACHE. */ @@ -577,6 +639,9 @@ aarch64_fetch_registers (struct regcache *regcache, int regno) if (tdep->has_sme2 ()) fetch_zt_from_thread (regcache); + + if (tdep->has_gcs ()) + fetch_gcsregs_from_thread (regcache); } /* General purpose register? */ else if (regno < AARCH64_V0_REGNUM) @@ -609,6 +674,11 @@ aarch64_fetch_registers (struct regcache *regcache, int regno) && regno >= tdep->tls_regnum_base && regno < tdep->tls_regnum_base + tdep->tls_register_count) fetch_tlsregs_from_thread (regcache); + /* GCS register? */ + else if (tdep->has_gcs () + && (regno == tdep->gcs_reg_base || regno == tdep->gcs_linux_reg_base + || regno == tdep->gcs_linux_reg_base + 1)) + fetch_gcsregs_from_thread (regcache); } /* A version of the "fetch_registers" target_ops method used when running @@ -680,6 +750,9 @@ aarch64_store_registers (struct regcache *regcache, int regno) if (tdep->has_sme2 ()) store_zt_to_thread (regcache); + + if (tdep->has_gcs ()) + store_gcsregs_to_thread (regcache); } /* General purpose register? */ else if (regno < AARCH64_V0_REGNUM) @@ -706,6 +779,11 @@ aarch64_store_registers (struct regcache *regcache, int regno) && regno >= tdep->tls_regnum_base && regno < tdep->tls_regnum_base + tdep->tls_register_count) store_tlsregs_to_thread (regcache); + /* GCS register? */ + else if (tdep->has_gcs () + && (regno == tdep->gcs_reg_base || regno == tdep->gcs_linux_reg_base + || regno == tdep->gcs_linux_reg_base + 1)) + store_gcsregs_to_thread (regcache); /* PAuth registers are read-only. */ } @@ -881,6 +959,7 @@ aarch64_linux_nat_target::read_description () active or not. */ features.vq = aarch64_sve_get_vq (tid); features.pauth = hwcap & AARCH64_HWCAP_PACA; + features.gcs = features.gcs_linux = hwcap & HWCAP_GCS; features.mte = hwcap2 & HWCAP2_MTE; features.tls = aarch64_tls_register_count (tid); /* SME feature check. */ diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c index a194ac809c23..ce213bb482b9 100644 --- a/gdb/aarch64-linux-tdep.c +++ b/gdb/aarch64-linux-tdep.c @@ -50,6 +50,7 @@ #include "record-full.h" #include "linux-record.h" +#include "arch/aarch64-gcs-linux.h" #include "arch/aarch64-mte.h" #include "arch/aarch64-mte-linux.h" #include "arch/aarch64-scalable-linux.h" @@ -1604,6 +1605,27 @@ aarch64_linux_iterate_over_regset_sections (struct gdbarch *gdbarch, cb (".reg-aarch-tls", sizeof_tls_regset, sizeof_tls_regset, &aarch64_linux_tls_regset, "TLS register", cb_data); } + + /* Handle GCS registers. */ + if (tdep->has_gcs ()) + { + /* Create this on the fly in order to handle the variable regnums. */ + const struct regcache_map_entry gcs_regmap[] = + { + { 1, tdep->gcs_linux_reg_base, 8 }, /* features_enabled */ + { 1, tdep->gcs_linux_reg_base + 1, 8 }, /* features_locked */ + { 1, tdep->gcs_reg_base, 8 }, /* GCSPR */ + { 0 } + }; + + const struct regset aarch64_linux_gcs_regset = + { + gcs_regmap, regcache_supply_regset, regcache_collect_regset + }; + + cb (".reg-aarch-gcs", sizeof (struct user_gcs), sizeof (struct user_gcs), + &aarch64_linux_gcs_regset, "GCS registers", cb_data); + } } /* Implement the "core_read_description" gdbarch method. */ @@ -1628,6 +1650,7 @@ aarch64_linux_core_read_description (struct gdbarch *gdbarch, length. */ features.vq = aarch64_linux_core_read_vq_from_sections (gdbarch, abfd); features.pauth = hwcap & AARCH64_HWCAP_PACA; + features.gcs = features.gcs_linux = hwcap & HWCAP_GCS; features.mte = hwcap2 & HWCAP2_MTE; /* Handle the TLS section. */ diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 8d54e59f332a..d728f60e9e15 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -159,6 +159,18 @@ static const char *const aarch64_mte_register_names[] = "tag_ctl" }; +static const char *const aarch64_gcs_register_names[] = { + /* Guarded Control Stack Pointer Register. */ + "gcspr" +}; + +static const char *const aarch64_gcs_linux_register_names[] = { + /* Field in struct user_gcs. */ + "gcs_features_enabled", + /* Field in struct user_gcs. */ + "gcs_features_locked", +}; + static int aarch64_stack_frame_destroyed_p (struct gdbarch *, CORE_ADDR); /* AArch64 prologue cache structure. */ @@ -1875,6 +1887,39 @@ pass_in_v_vfp_candidate (struct gdbarch *gdbarch, struct regcache *regcache, } } +/* Push LR_VALUE to the Guarded Control Stack. */ + +static void +aarch64_push_gcs_entry (regcache *regs, CORE_ADDR lr_value) +{ + gdbarch *arch = regs->arch (); + aarch64_gdbarch_tdep *tdep = gdbarch_tdep (arch); + CORE_ADDR gcs_addr; + + enum register_status status = regs->cooked_read (tdep->gcs_reg_base, + &gcs_addr); + if (status != REG_VALID) + error ("Can't read $gcspr."); + + gcs_addr -= 8; + gdb_byte buf[8]; + store_integer (buf, gdbarch_byte_order (arch), lr_value); + if (target_write_memory (gcs_addr, buf, sizeof (buf)) != 0) + error ("Can't write to Guarded Control Stack."); + + /* Update GCSPR. */ + regcache_cooked_write_unsigned (regs, tdep->gcs_reg_base, gcs_addr); +} + +/* Implement the "shadow_stack_push" gdbarch method. */ + +static void +aarch64_shadow_stack_push (gdbarch *gdbarch, CORE_ADDR new_addr, + regcache *regcache) +{ + aarch64_push_gcs_entry (regcache, new_addr); +} + /* Implement the "push_dummy_call" gdbarch method. */ static CORE_ADDR @@ -4046,6 +4091,14 @@ aarch64_features_from_target_desc (const struct target_desc *tdesc) features.sme2 = (tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sme2") != nullptr); + /* Check for the GCS feature. */ + features.gcs = (tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.gcs") + != nullptr); + + /* Check for the GCS Linux feature. */ + features.gcs_linux = (tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.gcs.linux") + != nullptr); + return features; } @@ -4590,6 +4643,46 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) int first_w_regnum = num_pseudo_regs; num_pseudo_regs += 31; + const struct tdesc_feature *feature_gcs + = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.gcs"); + int first_gcs_regnum = -1; + /* Add the GCS registers. */ + if (feature_gcs != nullptr) + { + first_gcs_regnum = num_regs; + /* Validate the descriptor provides the mandatory GCS registers and + allocate their numbers. */ + for (i = 0; i < ARRAY_SIZE (aarch64_gcs_register_names); i++) + valid_p &= tdesc_numbered_register (feature_gcs, tdesc_data.get (), + first_gcs_regnum + i, + aarch64_gcs_register_names[i]); + + num_regs += i; + } + + if (!valid_p) + return nullptr; + + const struct tdesc_feature *feature_gcs_linux + = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.gcs.linux"); + int first_gcs_linux_regnum = -1; + /* Add the GCS Linux registers. */ + if (feature_gcs_linux != nullptr) + { + first_gcs_linux_regnum = num_regs; + /* Validate the descriptor provides the mandatory GCS Linux registers + and allocate their numbers. */ + for (i = 0; i < ARRAY_SIZE (aarch64_gcs_linux_register_names); i++) + valid_p &= tdesc_numbered_register (feature_gcs_linux, tdesc_data.get (), + first_gcs_linux_regnum + i, + aarch64_gcs_linux_register_names[i]); + + /* This feature depends on the GCS feature. */ + valid_p &= feature_gcs != nullptr; + + num_regs += i; + } + if (!valid_p) return nullptr; @@ -4611,6 +4704,8 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) tdep->mte_reg_base = first_mte_regnum; tdep->tls_regnum_base = first_tls_regnum; tdep->tls_register_count = tls_register_count; + tdep->gcs_reg_base = first_gcs_regnum; + tdep->gcs_linux_reg_base = first_gcs_linux_regnum; /* Set the SME register set details. The pseudo-registers will be adjusted later. */ @@ -4733,6 +4828,9 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_get_pc_address_flags (gdbarch, aarch64_get_pc_address_flags); + if (tdep->has_gcs ()) + set_gdbarch_shadow_stack_push (gdbarch, aarch64_shadow_stack_push); + tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); /* Fetch the updated number of registers after we're done adding all @@ -4905,6 +5003,9 @@ aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) pulongest (tdep->sme_tile_pseudo_base)); gdb_printf (file, _("aarch64_dump_tdep: sme_svq = %s\n"), pulongest (tdep->sme_svq)); + + gdb_printf (file, _ ("aarch64_dump_tdep: gcs_reg_base = %d\n"), + tdep->gcs_reg_base); } #if GDB_SELF_TEST diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h index 3b8dcc26545b..0332e80da7bc 100644 --- a/gdb/aarch64-tdep.h +++ b/gdb/aarch64-tdep.h @@ -182,6 +182,20 @@ struct aarch64_gdbarch_tdep : gdbarch_tdep_base { return sme2_zt0_regnum > 0; } + + /* First GCS register. This is -1 if no GCS registers are available. */ + int gcs_reg_base = -1; + + /* First GCS Linux-specific register. This is -1 if no GCS Linux feature is + available. */ + int gcs_linux_reg_base = -1; + + /* Returns true if the target supports GCS. */ + bool + has_gcs () const + { + return gcs_reg_base != -1; + } }; const target_desc *aarch64_read_description (const aarch64_features &features); diff --git a/gdb/arch/aarch64-gcs-linux.h b/gdb/arch/aarch64-gcs-linux.h new file mode 100644 index 000000000000..9366caa7289a --- /dev/null +++ b/gdb/arch/aarch64-gcs-linux.h @@ -0,0 +1,44 @@ +/* Common Linux target-dependent definitions for AArch64 GCS + + Copyright (C) 2025 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef ARCH_AARCH64_GCS_LINUX_H +#define ARCH_AARCH64_GCS_LINUX_H + +#include + +/* Feature check for Guarded Control Stack. */ +#ifndef HWCAP_GCS +#define HWCAP_GCS (1UL << 32) +#endif + +/* Make sure we only define these if the kernel header doesn't. */ +#ifndef GCS_MAGIC + +/* GCS state (NT_ARM_GCS). */ + +struct user_gcs +{ + uint64_t features_enabled; + uint64_t features_locked; + uint64_t gcspr_el0; +}; + +#endif /* GCS_MAGIC */ + +#endif /* ARCH_AARCH64_GCS_LINUX_H */ diff --git a/gdb/arch/aarch64.c b/gdb/arch/aarch64.c index 3e1ca0547340..dff2bc16003a 100644 --- a/gdb/arch/aarch64.c +++ b/gdb/arch/aarch64.c @@ -26,6 +26,8 @@ #include "../features/aarch64-sme.c" #include "../features/aarch64-sme2.c" #include "../features/aarch64-tls.c" +#include "../features/aarch64-gcs.c" +#include "../features/aarch64-gcs-linux.c" /* See arch/aarch64.h. */ @@ -65,6 +67,12 @@ aarch64_create_target_description (const aarch64_features &features) if (features.sme2) regnum = create_feature_aarch64_sme2 (tdesc.get (), regnum); + if (features.gcs) + regnum = create_feature_aarch64_gcs (tdesc.get (), regnum); + + if (features.gcs_linux) + regnum = create_feature_aarch64_gcs_linux (tdesc.get (), regnum); + return tdesc.release (); } diff --git a/gdb/arch/aarch64.h b/gdb/arch/aarch64.h index ee18b74b80f5..679d845df74e 100644 --- a/gdb/arch/aarch64.h +++ b/gdb/arch/aarch64.h @@ -51,6 +51,12 @@ struct aarch64_features /* Whether SME2 is supported. */ bool sme2 = false; + + /* Whether Guarded Control Stack is supported. */ + bool gcs = false; + + /* Whether Guarded Control Stack Linux features are supported. */ + bool gcs_linux = false; }; inline bool operator==(const aarch64_features &lhs, const aarch64_features &rhs) @@ -60,7 +66,9 @@ inline bool operator==(const aarch64_features &lhs, const aarch64_features &rhs) && lhs.mte == rhs.mte && lhs.tls == rhs.tls && lhs.svq == rhs.svq - && lhs.sme2 == rhs.sme2; + && lhs.sme2 == rhs.sme2 + && lhs.gcs == rhs.gcs + && lhs.gcs_linux == rhs.gcs_linux; } namespace std diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index c7b57cf22505..03f419e90436 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -26979,6 +26979,21 @@ information automatically from the core file, and will show one of the above messages depending on whether the synchronous or asynchronous mode is selected. @xref{Memory Tagging}. @xref{Memory}. +@subsubsection Guarded Control Stack +@cindex AArch64 GCS +@cindex AArch64 Guarded Control Stack + +When @value{GDBN} is debugging the AArch64 architecture, the program is +using the feature Guarded Control Stack (GCS) and there is support in the +kernel for GCS, @value{GDBN} will make a couple of special registers --- +@code{gcs_features_enabled} and @code{gcs_features_locked} --- available +through the @code{org.gnu.gdb.aarch64.gcs.linux} feature. These registers +expose some options that can be controlled at runtime and emulate the +@code{prctl} option @code{PR_SET_SHADOW_STACK_STATUS}. For further +information, see the +@uref{https://www.kernel.org/doc/html/latest/arch/arm64/gcs.html,ignored, +documentation} in the Linux kernel. + @node x86 @subsection x86 @@ -49655,6 +49670,42 @@ of bytes. Extra registers are allowed in this feature, but they will not affect @value{GDBN}. +@subsubsection GCS registers + +The @samp{org.gnu.gdb.aarch64.gcs} feature is optional. If present, it +means the target supports Guarded Control Stacks and must contain the +following register: + +@itemize @minus + +@item +@code{gcspr}, which points to the thread's Guarded Control Stack. It is 64 +bits in size and has a type of @samp{data_ptr}. + +@end itemize + +The @samp{org.gnu.gdb.aarch64.gcs.linux} feature is optional. If present, +then the @samp{org.gnu.gdb.aarch64.gcs} feature must also be present. The +@samp{org.gnu.gdb.aarch64.gcs.linux} feature represents facilities provided +by the Linux kernel for GCS support and should contain the following: + +@itemize @minus + +@item +@code{gcs_features_enabled} shows the features currently enabled via the +prctl or ptrace system calls. It is represented as if it were a 64-bit +register with a custom flags type. + +@item +@code{gcs_features_locked} shows the features currently locked via the +prctl or ptrace system calls. It is represented as if it were a 64-bit +register with a custom flags type. + +@end itemize + +Extra registers are allowed in these features, but they will not affect +@value{GDBN}. + @node ARC Features @subsection ARC Features @cindex target descriptions, ARC Features diff --git a/gdb/features/Makefile b/gdb/features/Makefile index 2afda1ccd00f..ed20a7537ffb 100644 --- a/gdb/features/Makefile +++ b/gdb/features/Makefile @@ -203,6 +203,8 @@ FEATURE_XMLFILES = aarch64-core.xml \ aarch64-fpu.xml \ aarch64-pauth.xml \ aarch64-mte.xml \ + aarch64-gcs.xml \ + aarch64-gcs-linux.xml \ arc/v1-core.xml \ arc/v1-aux.xml \ arc/v2-core.xml \ diff --git a/gdb/features/aarch64-gcs-linux.c b/gdb/features/aarch64-gcs-linux.c new file mode 100644 index 000000000000..6b0d25b4518c --- /dev/null +++ b/gdb/features/aarch64-gcs-linux.c @@ -0,0 +1,21 @@ +/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: + Original: aarch64-gcs-linux.xml */ + +#include "gdbsupport/tdesc.h" + +static int +create_feature_aarch64_gcs_linux (struct target_desc *result, long regnum) +{ + struct tdesc_feature *feature; + + feature = tdesc_create_feature (result, "org.gnu.gdb.aarch64.gcs.linux"); + tdesc_type_with_fields *type_with_fields; + type_with_fields = tdesc_create_flags (feature, "features_flags", 8); + tdesc_add_flag (type_with_fields, 0, "PR_SHADOW_STACK_ENABLE"); + tdesc_add_flag (type_with_fields, 1, "PR_SHADOW_STACK_WRITE"); + tdesc_add_flag (type_with_fields, 2, "PR_SHADOW_STACK_PUSH"); + + tdesc_create_reg (feature, "gcs_features_enabled", regnum++, 1, "system", 64, "features_flags"); + tdesc_create_reg (feature, "gcs_features_locked", regnum++, 1, "system", 64, "features_flags"); + return regnum; +} diff --git a/gdb/features/aarch64-gcs-linux.xml b/gdb/features/aarch64-gcs-linux.xml new file mode 100644 index 000000000000..8d9d2ceb9260 --- /dev/null +++ b/gdb/features/aarch64-gcs-linux.xml @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + diff --git a/gdb/features/aarch64-gcs.c b/gdb/features/aarch64-gcs.c new file mode 100644 index 000000000000..2b2caf29cc8c --- /dev/null +++ b/gdb/features/aarch64-gcs.c @@ -0,0 +1,14 @@ +/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: + Original: aarch64-gcs.xml */ + +#include "gdbsupport/tdesc.h" + +static int +create_feature_aarch64_gcs (struct target_desc *result, long regnum) +{ + struct tdesc_feature *feature; + + feature = tdesc_create_feature (result, "org.gnu.gdb.aarch64.gcs"); + tdesc_create_reg (feature, "gcspr", regnum++, 1, "system", 64, "data_ptr"); + return regnum; +} diff --git a/gdb/features/aarch64-gcs.xml b/gdb/features/aarch64-gcs.xml new file mode 100644 index 000000000000..bbee5e001722 --- /dev/null +++ b/gdb/features/aarch64-gcs.xml @@ -0,0 +1,11 @@ + + + + + + + diff --git a/gdbserver/linux-aarch64-low.cc b/gdbserver/linux-aarch64-low.cc index 2eb3af659ad1..9feb1914dbd6 100644 --- a/gdbserver/linux-aarch64-low.cc +++ b/gdbserver/linux-aarch64-low.cc @@ -39,6 +39,7 @@ #include "gdb_proc_service.h" #include "arch/aarch64.h" +#include "arch/aarch64-gcs-linux.h" #include "arch/aarch64-mte-linux.h" #include "arch/aarch64-scalable-linux.h" #include "linux-aarch32-tdesc.h" @@ -321,6 +322,42 @@ aarch64_store_tlsregset (struct regcache *regcache, const void *buf) supply_register (regcache, *regnum, tls_buf + sizeof (uint64_t)); } +/* Fill BUF with GCS register from the regcache. */ + +static void +aarch64_fill_gcsregset (struct regcache *regcache, void *buf) +{ + struct user_gcs *regset = (struct user_gcs *) buf; + int gcspr_regnum = find_regno (regcache->tdesc, "gcspr"); + int features_enabled_regnum = find_regno (regcache->tdesc, + "gcs_features_enabled"); + int features_locked_regnum = find_regno (regcache->tdesc, + "gcs_features_locked"); + + collect_register (regcache, gcspr_regnum, ®set->gcspr_el0); + collect_register (regcache, features_enabled_regnum, + ®set->features_enabled); + collect_register (regcache, features_locked_regnum, ®set->features_locked); +} + +/* Store GCS register to regcache. */ + +static void +aarch64_store_gcsregset (struct regcache *regcache, const void *buf) +{ + const struct user_gcs *regset = (const struct user_gcs *) buf; + int gcspr_regnum = find_regno (regcache->tdesc, "gcspr"); + int features_enabled_regnum = find_regno (regcache->tdesc, + "gcs_features_enabled"); + int features_locked_regnum = find_regno (regcache->tdesc, + "gcs_features_locked"); + + supply_register (regcache, gcspr_regnum, ®set->gcspr_el0); + supply_register (regcache, features_enabled_regnum, + ®set->features_enabled); + supply_register (regcache, features_locked_regnum, ®set->features_locked); +} + bool aarch64_target::low_supports_breakpoints () { @@ -846,6 +883,10 @@ static struct regset_info aarch64_regsets[] = { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TLS, 0, OPTIONAL_REGS, aarch64_fill_tlsregset, aarch64_store_tlsregset }, + /* Guarded Control Stack registers. */ + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_GCS, + 0, OPTIONAL_REGS, + aarch64_fill_gcsregset, aarch64_store_gcsregset }, NULL_REGSET }; @@ -909,6 +950,10 @@ aarch64_adjust_register_sets (const struct aarch64_features &features) if (features.sme2) regset->size = AARCH64_SME2_ZT0_SIZE; break; + case NT_ARM_GCS: + if (features.gcs_linux) + regset->size = sizeof (struct user_gcs); + break; default: gdb_assert_not_reached ("Unknown register set found."); } @@ -940,6 +985,7 @@ aarch64_target::low_arch_setup () /* A-profile MTE is 64-bit only. */ features.mte = linux_get_hwcap2 (pid, 8) & HWCAP2_MTE; features.tls = aarch64_tls_register_count (tid); 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Sat, 07 Jun 2025 18:03:54 -0700 (PDT) Received: from localhost ([2804:14d:7e39:88d6:8cb1:1e8e:e951:f687]) by smtp.gmail.com with ESMTPSA id ada2fe7eead31-4e7735e5172sm3248876137.0.2025.06.07.18.03.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jun 2025 18:03:54 -0700 (PDT) From: Thiago Jung Bauermann To: gdb-patches@sourceware.org Subject: [PATCH 4/8] GDB: aarch64-linux: GCS support in Linux signals Date: Sat, 7 Jun 2025 22:03:15 -0300 Message-ID: <20250608010338.2234530-5-thiago.bauermann@linaro.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250608010338.2234530-1-thiago.bauermann@linaro.org> References: <20250608010338.2234530-1-thiago.bauermann@linaro.org> MIME-Version: 1.0 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~patch=linaro.org@sourceware.org The signal frame can have a GCS context, so teach GDB how to use it. Also, there's a new SEGV sigcode when the inferior does an illegal memory access in the Guarded Control Stack, so display a message when that is the case. --- gdb/aarch64-linux-tdep.c | 83 ++++++++++++++++++++++++++++++++---- gdb/arch/aarch64-gcs-linux.h | 4 ++ gdb/doc/gdb.texinfo | 8 ++++ 3 files changed, 86 insertions(+), 9 deletions(-) diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c index ce213bb482b9..24fb151311c4 100644 --- a/gdb/aarch64-linux-tdep.c +++ b/gdb/aarch64-linux-tdep.c @@ -165,6 +165,7 @@ #define AARCH64_ZA_MAGIC 0x54366345 #define AARCH64_TPIDR2_MAGIC 0x54504902 #define AARCH64_ZT_MAGIC 0x5a544e01 +#define AARCH64_GCS_MAGIC 0x47435300 /* Defines for the extra_context that follows an AARCH64_EXTRA_MAGIC. */ #define AARCH64_EXTRA_DATAP_OFFSET 8 @@ -206,6 +207,11 @@ the signal context state. */ #define AARCH64_SME2_CONTEXT_REGS_OFFSET 16 +/* GCSPR register value offset in the GCS signal frame context. */ +#define AARCH64_GCS_CONTEXT_GCSPR_OFFSET 8 +/* features_enabled value offset in the GCS signal frame context. */ +#define AARCH64_GCS_CONTEXT_FEATURES_ENABLED_OFFSET 16 + /* Holds information about the signal frame. */ struct aarch64_linux_sigframe { @@ -246,6 +252,13 @@ struct aarch64_linux_sigframe bool za_payload = false; /* True if we have a ZT entry in the signal context, false otherwise. */ bool zt_available = false; + + /* True if we have a GCS entry in the signal context, false otherwise. */ + bool gcs_availabe = false; + /* The Guarded Control Stack Pointer Register. */ + uint64_t gcspr; + /* Flags indicating which GCS features are enabled for the thread. */ + uint64_t gcs_features_enabled; }; /* Read an aarch64_ctx, returning the magic value, and setting *SIZE to the @@ -526,6 +539,39 @@ aarch64_linux_read_signal_frame_info (const frame_info_ptr &this_frame, signal_frame.zt_section = section; signal_frame.zt_available = true; + section += size; + break; + } + case AARCH64_GCS_MAGIC: + { + gdb_byte buf[8]; + + /* Extract the GCSPR. */ + if (target_read_memory (section + AARCH64_GCS_CONTEXT_GCSPR_OFFSET, + buf, 8) != 0) + { + warning (_("Failed to read the GCSPR from the GCS signal frame" + " context.")); + section += size; + break; + } + + signal_frame.gcspr = extract_unsigned_integer (buf, byte_order); + + /* Extract the features_enabled field. */ + if (target_read_memory (section + + AARCH64_GCS_CONTEXT_FEATURES_ENABLED_OFFSET, + buf, sizeof (buf)) != 0) + { + warning (_("Failed to read the enabled features from the GCS" + " signal frame context.")); + section += size; + break; + } + + signal_frame.gcs_features_enabled + = extract_unsigned_integer (buf, byte_order); + signal_frame.gcs_availabe = true; section += size; break; } @@ -703,6 +749,19 @@ aarch64_linux_sigframe_init (const struct tramp_frame *self, + AARCH64_TPIDR2_CONTEXT_TPIDR2_OFFSET); } + /* Restore the GCS registers, if the target supports it and if there is + an entry for them. */ + if (signal_frame.gcs_availabe && tdep->has_gcs ()) + { + /* Restore GCSPR. */ + trad_frame_set_reg_value (this_cache, tdep->gcs_reg_base, + signal_frame.gcspr); + /* Restore gcs_features_enabled. */ + trad_frame_set_reg_value (this_cache, tdep->gcs_linux_reg_base, + signal_frame.gcs_features_enabled); + /* gcs_features_locked isn't present in the GCS signal context. */ + } + trad_frame_set_id (this_cache, frame_id_build (signal_frame.sp, func)); } @@ -2486,17 +2545,18 @@ aarch64_linux_report_signal_info (struct gdbarch *gdbarch, { aarch64_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - if (!tdep->has_mte () || siggnal != GDB_SIGNAL_SEGV) + if (!(tdep->has_mte () || tdep->has_gcs ()) || siggnal != GDB_SIGNAL_SEGV) return; CORE_ADDR fault_addr = 0; - long si_code = 0; + long si_code = 0, si_errno = 0; try { /* Sigcode tells us if the segfault is actually a memory tag violation. */ si_code = parse_and_eval_long ("$_siginfo.si_code"); + si_errno = parse_and_eval_long ("$_siginfo.si_errno"); fault_addr = parse_and_eval_long ("$_siginfo._sifields._sigfault.si_addr"); @@ -2507,13 +2567,18 @@ aarch64_linux_report_signal_info (struct gdbarch *gdbarch, return; } - /* If this is not a memory tag violation, just return. */ - if (si_code != SEGV_MTEAERR && si_code != SEGV_MTESERR) + const char *meaning; + + if (si_code == SEGV_MTEAERR || si_code == SEGV_MTESERR) + meaning = _("Memory tag violation"); + else if (si_code == SEGV_CPERR && si_errno == 0) + meaning = _("Guarded Control Stack error"); + else return; uiout->text ("\n"); - uiout->field_string ("sigcode-meaning", _("Memory tag violation")); + uiout->field_string ("sigcode-meaning", meaning); /* For synchronous faults, show additional information. */ if (si_code == SEGV_MTESERR) @@ -2539,7 +2604,7 @@ aarch64_linux_report_signal_info (struct gdbarch *gdbarch, uiout->field_string ("logical-tag", hex_string (ltag)); } } - else + else if (si_code != SEGV_CPERR) { uiout->text ("\n"); uiout->text (_("Fault address unavailable")); @@ -2838,9 +2903,6 @@ aarch64_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) /* Register a hook for checking if an address is tagged or not. */ set_gdbarch_tagged_address_p (gdbarch, aarch64_linux_tagged_address_p); - set_gdbarch_report_signal_info (gdbarch, - aarch64_linux_report_signal_info); - /* Core file helpers. */ /* Core file helper to create a memory tag section for a particular @@ -2857,6 +2919,9 @@ aarch64_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) aarch64_linux_decode_memtag_section); } + if (tdep->has_mte () || tdep->has_gcs ()) + set_gdbarch_report_signal_info (gdbarch, aarch64_linux_report_signal_info); + /* Initialize the aarch64_linux_record_tdep. */ /* These values are the size of the type that will be used in a system call. They are obtained from Linux Kernel source. */ diff --git a/gdb/arch/aarch64-gcs-linux.h b/gdb/arch/aarch64-gcs-linux.h index 9366caa7289a..853e748faf2d 100644 --- a/gdb/arch/aarch64-gcs-linux.h +++ b/gdb/arch/aarch64-gcs-linux.h @@ -41,4 +41,8 @@ struct user_gcs #endif /* GCS_MAGIC */ +#ifndef SEGV_CPERR +#define SEGV_CPERR 10 /* Control protection error. */ +#endif + #endif /* ARCH_AARCH64_GCS_LINUX_H */ diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index 03f419e90436..1b35fa029884 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -26994,6 +26994,14 @@ information, see the @uref{https://www.kernel.org/doc/html/latest/arch/arm64/gcs.html,ignored, documentation} in the Linux kernel. +To aid debugging, @value{GDBN} will note when SIGSEGV signals are generated +as a result of a Guarded Control Stack error: + +@smallexample +Program received signal SIGSEGV, Segmentation fault +Guarded Control Stack error. +@end smallexample + @node x86 @subsection x86 From patchwork Sun Jun 8 01:03:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thiago Jung Bauermann X-Patchwork-Id: 894807 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:ecd:b0:3a4:ee3f:8f15 with SMTP id ea13csp1177238wrb; Sat, 7 Jun 2025 18:12:56 -0700 (PDT) X-Forwarded-Encrypted: i=3; AJvYcCVdAgJ5VNsdh1k/IO8SJlMBu6fb+X3SxfQj9BWVORVVpu1Kse4d2Z6o1fMKSdinPuH/Wp0eAA==@linaro.org X-Google-Smtp-Source: AGHT+IEoGigUJzk1WoVQRiFwIgCLaTJ5AZrrPE9JajWQxbGN3aHf81w/oZfpz6CzwrnKo4FGuuDT X-Received: by 2002:a05:6214:c2f:b0:6f4:cdca:2a6e with SMTP id 6a1803df08f44-6fb0906fda5mr142228106d6.45.1749345176608; Sat, 07 Jun 2025 18:12:56 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1749345176; cv=pass; d=google.com; s=arc-20240605; b=NGK+k03OO/BXpp7difPuhKpPM7G9rVKnCvhN5fUaEK/lbqyOHyiROhxR2wSrIEcaz5 gIn8As0oPV8RILXWVwhEUrsNOyKLBA6JMyKzmy0tvglVlMYxiafOvglo3Hrjn1MNYmMW sZcYwbAkKXMnsWlzrgcJbWtxMetjLImeCb+9QHYse3NZUhGRUy2rCN+GV5817ZjKJpju aa4KFa+4FpVNvBeNmuK6JbkiBqPaqZigMwDzDolXZAiZGCL2/6lry8qW8XXO/3OGdUM6 vvlaQK6/elykY8lE6LaS49G+Me2aR+MY6bufP6z9/B6P6tbHUU2YtLyZwZwhmlOC/MPA tHtw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:dkim-filter:arc-filter:dmarc-filter:delivered-to :dkim-filter; bh=QP19AvrdeZh5N2+LhyeA749/sMr8NDEdjIDs0sp8lxs=; fh=72kqq0iQhigvR9Vv/oqX5ebs3Yyyw7XhzWxOOEPdupI=; b=REr4aUz4/eOSOfbeDpSn5/xMe1cT3mq6T7t+ydXIDEWKdx4fnhjb4Fo22pRKURXq2R EY64en+KPLYzHrBu3Brn9BLZYoIyJ3hlxc+OEqazdzlVk8HgWDB3Z7LsLeuNRIJ+mrl1 mtUVRf+YTwshS+yadM5Vl4mbM7IlM4bo7JxvEvUzWAJBQY63M/9rt+9bukUvvKv5Avgy BwfstfVtT0m27FH44NVefkZkibYTi+VBH+4Hety4C8TTZmxxJwZkJ6opDg0TUYhsdfBx FgGzZuJQI+4kLtXbH99HpUPYBNxYZLpKPAjKYcc2EAOwXiy9PJjadvKADG8r7gyk6HDe smNg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Zmgt/mhR"; arc=pass (i=1); spf=pass (google.com: domain of gdb-patches-bounces~patch=linaro.org@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gdb-patches-bounces~patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. 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Sat, 07 Jun 2025 18:03:58 -0700 (PDT) Received: from localhost ([2804:14d:7e39:88d6:8cb1:1e8e:e951:f687]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-87ec5da036fsm1985127241.18.2025.06.07.18.03.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jun 2025 18:03:57 -0700 (PDT) From: Thiago Jung Bauermann To: gdb-patches@sourceware.org Subject: [PATCH 5/8] GDB: aarch64-linux: Implement GCS support in displaced stepping Date: Sat, 7 Jun 2025 22:03:16 -0300 Message-ID: <20250608010338.2234530-6-thiago.bauermann@linaro.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250608010338.2234530-1-thiago.bauermann@linaro.org> References: <20250608010338.2234530-1-thiago.bauermann@linaro.org> MIME-Version: 1.0 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~patch=linaro.org@sourceware.org When doing displaced step on a branch and link instruction with the Guarded Control Stack enabled, it's necessary to manually push and pop the GCS entry for the function call since GDB writes a simple branch instruction rather than a branch and link instruction in the displaced step buffer. Reviewed-By: Eli Zaretskii --- gdb/NEWS | 3 +++ gdb/aarch64-linux-tdep.c | 30 +++++++++++++++++++++++++ gdb/aarch64-tdep.c | 47 +++++++++++++++++++++++++++++++++++----- gdb/linux-tdep.h | 7 ++++++ 4 files changed, 82 insertions(+), 5 deletions(-) diff --git a/gdb/NEWS b/gdb/NEWS index a82b7e3342c5..13a11134600f 100644 --- a/gdb/NEWS +++ b/gdb/NEWS @@ -48,6 +48,9 @@ * Add record full support for rv64gc architectures +* Debugging Linux programs that use AArch64 Guarded Control Stacks are now + supported. + * New commands maintenance check psymtabs diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c index 24fb151311c4..812486e0d250 100644 --- a/gdb/aarch64-linux-tdep.c +++ b/gdb/aarch64-linux-tdep.c @@ -2534,6 +2534,32 @@ aarch64_linux_tagged_address_p (struct gdbarch *gdbarch, CORE_ADDR address) return true; } +/* Implement the "get_shadow_stack_pointer" gdbarch method. */ + +static std::optional +aarch64_linux_get_shadow_stack_pointer (gdbarch *gdbarch, regcache *regcache, + bool &shadow_stack_enabled) +{ + aarch64_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + shadow_stack_enabled = false; + + if (!tdep->has_gcs ()) + return {}; + + uint64_t features_enabled; + enum register_status status = regcache->cooked_read (tdep->gcs_linux_reg_base, + &features_enabled); + if (status != REG_VALID) + error (_("Can't read $gcs_features_enabled.")); + + CORE_ADDR gcspr; + status = regcache->cooked_read (tdep->gcs_reg_base, &gcspr); + if (status != REG_VALID) + error (_("Can't read $gcspr.")); + + shadow_stack_enabled = features_enabled & PR_SHADOW_STACK_ENABLE; + return gcspr; +} /* AArch64 Linux implementation of the report_signal_info gdbarch hook. Displays information about possible memory tag violations. */ @@ -3103,6 +3129,10 @@ aarch64_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) sections. */ set_gdbarch_use_target_description_from_corefile_notes (gdbarch, aarch64_use_target_description_from_corefile_notes); + + if (tdep->has_gcs ()) + set_gdbarch_get_shadow_stack_pointer (gdbarch, + aarch64_linux_get_shadow_stack_pointer); } #if GDB_SELF_TEST diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index d728f60e9e15..4f204f2e4208 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -1911,6 +1911,24 @@ aarch64_push_gcs_entry (regcache *regs, CORE_ADDR lr_value) regcache_cooked_write_unsigned (regs, tdep->gcs_reg_base, gcs_addr); } +/* Remove the newest entry from the Guarded Control Stack. */ + +static void +aarch64_pop_gcs_entry (regcache *regs) +{ + gdbarch *arch = regs->arch (); + aarch64_gdbarch_tdep *tdep = gdbarch_tdep (arch); + CORE_ADDR gcs_addr; + + enum register_status status = regs->cooked_read (tdep->gcs_reg_base, + &gcs_addr); + if (status != REG_VALID) + error ("Can't read $gcspr."); + + /* Update GCSPR. */ + regcache_cooked_write_unsigned (regs, tdep->gcs_reg_base, gcs_addr + 8); +} + /* Implement the "shadow_stack_push" gdbarch method. */ static void @@ -3602,6 +3620,9 @@ struct aarch64_displaced_step_copy_insn_closure /* PC adjustment offset after displaced stepping. If 0, then we don't write the PC back, assuming the PC is already the right address. */ int32_t pc_adjust = 0; + + /* True if it's a branch instruction that saves the link register. */ + bool linked_branch = false; }; /* Data when visiting instructions for displaced stepping. */ @@ -3653,6 +3674,12 @@ aarch64_displaced_step_b (const int is_bl, const int32_t offset, /* Update LR. */ regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM, data->insn_addr + 4); + dsd->dsc->linked_branch = true; + bool gcs_is_enabled; + gdbarch_get_shadow_stack_pointer (dsd->regs->arch (), dsd->regs, + gcs_is_enabled); + if (gcs_is_enabled) + aarch64_push_gcs_entry (dsd->regs, data->insn_addr + 4); } } @@ -3811,6 +3838,12 @@ aarch64_displaced_step_others (const uint32_t insn, aarch64_emit_insn (dsd->insn_buf, insn & 0xffdfffff); regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM, data->insn_addr + 4); + dsd->dsc->linked_branch = true; + bool gcs_is_enabled; + gdbarch_get_shadow_stack_pointer (dsd->regs->arch (), dsd->regs, + gcs_is_enabled); + if (gcs_is_enabled) + aarch64_push_gcs_entry (dsd->regs, data->insn_addr + 4); } else aarch64_emit_insn (dsd->insn_buf, insn); @@ -3907,20 +3940,24 @@ aarch64_displaced_step_fixup (struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs, bool completed_p) { + aarch64_displaced_step_copy_insn_closure *dsc + = (aarch64_displaced_step_copy_insn_closure *) dsc_; CORE_ADDR pc = regcache_read_pc (regs); - /* If the displaced instruction didn't complete successfully then all we - need to do is restore the program counter. */ + /* If the displaced instruction didn't complete successfully then we need + to restore the program counter, and perhaps the Guarded Control Stack. */ if (!completed_p) { + bool gcs_is_enabled; + gdbarch_get_shadow_stack_pointer (gdbarch, regs, gcs_is_enabled); + if (dsc->linked_branch && gcs_is_enabled) + aarch64_pop_gcs_entry (regs); + pc = from + (pc - to); regcache_write_pc (regs, pc); return; } - aarch64_displaced_step_copy_insn_closure *dsc - = (aarch64_displaced_step_copy_insn_closure *) dsc_; - displaced_debug_printf ("PC after stepping: %s (was %s).", paddress (gdbarch, pc), paddress (gdbarch, to)); diff --git a/gdb/linux-tdep.h b/gdb/linux-tdep.h index 7083635b976c..21f46e2ef50d 100644 --- a/gdb/linux-tdep.h +++ b/gdb/linux-tdep.h @@ -26,6 +26,13 @@ struct inferior; struct regcache; +/* Flag which enables shadow stack in PR_SET_SHADOW_STACK_STATUS prctl. */ +#ifndef PR_SHADOW_STACK_ENABLE +#define PR_SHADOW_STACK_ENABLE (1UL << 0) +#define PR_SHADOW_STACK_WRITE (1UL << 1) +#define PR_SHADOW_STACK_PUSH (1UL << 2) +#endif + /* Enum used to define the extra fields of the siginfo type used by an architecture. */ enum linux_siginfo_extra_field_values From patchwork Sun Jun 8 01:03:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thiago Jung Bauermann X-Patchwork-Id: 894806 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:ecd:b0:3a4:ee3f:8f15 with SMTP id ea13csp1176819wrb; Sat, 7 Jun 2025 18:11:03 -0700 (PDT) X-Forwarded-Encrypted: i=3; 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Sat, 07 Jun 2025 18:04:01 -0700 (PDT) Received: from localhost ([2804:14d:7e39:88d6:8cb1:1e8e:e951:f687]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-87ebd194e03sm2994981241.2.2025.06.07.18.04.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jun 2025 18:04:01 -0700 (PDT) From: Thiago Jung Bauermann To: gdb-patches@sourceware.org Subject: [PATCH 6/8] GDB: testsuite: Add gdb.arch/aarch64-gcs.exp testcase Date: Sat, 7 Jun 2025 22:03:17 -0300 Message-ID: <20250608010338.2234530-7-thiago.bauermann@linaro.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250608010338.2234530-1-thiago.bauermann@linaro.org> References: <20250608010338.2234530-1-thiago.bauermann@linaro.org> MIME-Version: 1.0 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~patch=linaro.org@sourceware.org Also add allow_aarch64_gcs_tests procedure to determine whether Guarded Control Stack tests should run. --- gdb/testsuite/gdb.arch/aarch64-gcs.c | 168 +++++++++++++++++++++++++ gdb/testsuite/gdb.arch/aarch64-gcs.exp | 78 ++++++++++++ gdb/testsuite/lib/gdb.exp | 58 +++++++++ 3 files changed, 304 insertions(+) create mode 100644 gdb/testsuite/gdb.arch/aarch64-gcs.c create mode 100644 gdb/testsuite/gdb.arch/aarch64-gcs.exp diff --git a/gdb/testsuite/gdb.arch/aarch64-gcs.c b/gdb/testsuite/gdb.arch/aarch64-gcs.c new file mode 100644 index 000000000000..8e579de10cdb --- /dev/null +++ b/gdb/testsuite/gdb.arch/aarch64-gcs.c @@ -0,0 +1,168 @@ +/* This test program is part of GDB, the GNU debugger. + + Copyright 2025 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include +#include +#include +#include +#include +#include + +/* Feature check for Guarded Control Stack. */ +#ifndef HWCAP_GCS +#define HWCAP_GCS (1UL << 32) +#endif + +#ifndef PR_GET_SHADOW_STACK_STATUS +#define PR_GET_SHADOW_STACK_STATUS 74 +#define PR_SET_SHADOW_STACK_STATUS 75 +#define PR_SHADOW_STACK_ENABLE (1UL << 0) +#endif + +/* We need to use a macro to call prctl because after GCS is enabled, it's not + possible to return from the function which enabled it. This is because the + return address of the calling function isn't on the GCS. */ +#define my_syscall2(num, arg1, arg2) \ + ({ \ + register long _num __asm__("x8") = (num); \ + register long _arg1 __asm__("x0") = (long)(arg1); \ + register long _arg2 __asm__("x1") = (long)(arg2); \ + register long _arg3 __asm__("x2") = 0; \ + register long _arg4 __asm__("x3") = 0; \ + register long _arg5 __asm__("x4") = 0; \ + \ + __asm__ volatile("svc #0\n" \ + : "=r"(_arg1) \ + : "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), \ + "r"(_arg5), "r"(_num) \ + : "memory", "cc"); \ + _arg1; \ + }) + +#define get_gcspr(void) \ + ({ \ + unsigned long *gcspr; \ + \ + /* Get GCSPR_EL0. */ \ + asm volatile("mrs %0, S3_3_C2_C5_1" : "=r"(gcspr) : : "cc"); \ + \ + gcspr; \ + }) + +static unsigned long *handler_gcspr = 0; + +static void +handler (int sig) +{ + handler_gcspr = get_gcspr (); +} + +static int __attribute__ ((unused)) +called_from_gdb (int val) +{ + return val + 1; +} + +/* Corrupt the return address to see if GDB will report a SIGSEGV with the expected + $_siginfo.si_code. */ +static void __attribute__ ((noinline)) +normal_function2 (void) +{ + /* x30 holds the return address. */ + register unsigned long x30 __asm__("x30") __attribute__ ((unused)); + + /* Cause a GCS exception. */ + x30 = 0xbadc0ffee; + __asm__ volatile("ret\n"); +} + +static inline void __attribute__ ((__always_inline__)) +inline_function2 (void) +{ + normal_function2 (); +} + +/* Corrupt the return address to see if GDB will report a GCS error in this + function's frame . */ +static void __attribute__ ((noinline)) +normal_function1 (void) +{ + /* x30 holds the return address. */ + register unsigned long x30 __asm__ ("x30") __attribute__ ((unused)); + x30 = 0xbadc0ffee; + inline_function2 (); +} + +static inline void __attribute__ ((__always_inline__)) +inline_function1 (void) +{ + normal_function1 (); +} + +int +main (void) +{ + if (!(getauxval (AT_HWCAP) & HWCAP_GCS)) + { + fprintf (stderr, "GCS support not found in AT_HWCAP\n"); + return EXIT_FAILURE; + } + + /* Force shadow stacks on, our tests *should* be fine with or + without libc support and with or without this having ended + up tagged for GCS and enabled by the dynamic linker. We + can't use the libc prctl() function since we can't return + from enabling the stack. Also lock GCS if not already + locked so we can test behaviour when it's locked. */ + unsigned long gcs_mode; + int ret = my_syscall2 (__NR_prctl, PR_GET_SHADOW_STACK_STATUS, &gcs_mode); + if (ret) + { + fprintf (stderr, "Failed to read GCS state: %d\n", ret); + return EXIT_FAILURE; + } + + if (!(gcs_mode & PR_SHADOW_STACK_ENABLE)) + { + gcs_mode = PR_SHADOW_STACK_ENABLE; + ret = my_syscall2 (__NR_prctl, PR_SET_SHADOW_STACK_STATUS, gcs_mode); + if (ret) + { + fprintf (stderr, "Failed to configure GCS: %d\n", ret); + return EXIT_FAILURE; + } + } + + /* This is used by GDB. */ + __attribute__((unused)) unsigned long *gcspr = get_gcspr (); + + struct sigaction act = { 0 }; + + act.sa_handler = &handler; /* Break here. */ + if (sigaction (SIGUSR1, &act, NULL) == -1) + { + perror ("sigaction"); + exit (EXIT_FAILURE); + } + + raise (SIGUSR1); + + inline_function1 (); + + /* Avoid returning, in case libc doesn't understand GCS. */ + exit (EXIT_SUCCESS); +} diff --git a/gdb/testsuite/gdb.arch/aarch64-gcs.exp b/gdb/testsuite/gdb.arch/aarch64-gcs.exp new file mode 100644 index 000000000000..211fabf2f86b --- /dev/null +++ b/gdb/testsuite/gdb.arch/aarch64-gcs.exp @@ -0,0 +1,78 @@ +# Copyright 2025 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# Test a binary that uses a Guarded Control Stack. + +require allow_aarch64_gcs_tests + +standard_testfile + +if { [prepare_for_testing "failed to prepare" ${testfile} ${srcfile}] } { + return +} + +set linespec ${srcfile}:[gdb_get_line_number "Break here"] + +if ![runto ${linespec}] { + return +} + +gdb_test "print \$gcs_features_enabled" \ + [string_to_regexp { = [ PR_SHADOW_STACK_ENABLE ]}] \ + "GCS is enabled" + +gdb_test "print \$gcspr" ". = \\(void \\*\\) $hex" "GDB knows about gcspr" +gdb_test "print \$gcspr == gcspr" ". = 1" "GDB has the correct gcspr value" +gdb_test_no_output "set \$gcspr_in_main = \$gcspr" \ + "save gcspr value in main for later" + +# If the inferior function call fails, we don't want the tests following it +# to be affected. +gdb_test_no_output "set unwindonsignal on" +gdb_test "print called_from_gdb (41)" ". = 42" "call inferior function" + +gdb_test "break handler" "Breakpoint \[0-9\]+ .*aarch64-gcs.c, line \[0-9\]+\\." +gdb_test "handle SIGUSR1 nostop" \ + ".*\r\nSIGUSR1\\s+No\\s+Yes\\s+Yes\\s+User defined signal 1" \ + "let the inferior receive SIGUSR1 uninterrupted" +gdb_test "continue" \ + ".*\r\nBreakpoint \[0-9\]+, handler \\(sig=10\\) at .*aarch64-gcs.c.*handler_gcspr = get_gcspr \\(\\);" \ + "continue to signal handler" + +gdb_test_no_output "set \$gcspr_in_handler = \$gcspr" \ + "save gcspr value in handler for later" +# Select the frame above the frame, which makes GDB +# unwind the gcspr from the signal frame GCS context. +gdb_test "frame 2" "#2 ($hex in )?\\S+ \\(.*\\) (at|from) \\S+.*" \ + "reached frame 2" +gdb_test "print \$gcspr" ". = \\(void \\*\\) $hex" "gcspr in frame level 2" +gdb_test "print \$gcspr == \$gcspr_in_handler + 8" ". = 1" \ + "gcspr unwound from signal context is correct" + +gdb_test "continue" \ + [multi_line \ + "Continuing\\." \ + "" \ + "Program received signal SIGSEGV, Segmentation fault" \ + "Guarded Control Stack error\\." \ + "normal_function2 \\(\\) at .*aarch64-gcs.c:$decimal" \ + "${decimal}\\s+__asm__ volatile\\(\"ret\\\\n\"\\);"] \ + "continue to SIGSEGV" + +gdb_test "print \$_siginfo.si_code" ". = 10" \ + "test value of si_code when GCS SIGSEGV happens" +# The GCS grows down, and there are two real frames until main. +gdb_test "print \$gcspr == \$gcspr_in_main - 16" ". = 1" \ + "test value of gcspr when GCS SIGSEGV happens" diff --git a/gdb/testsuite/lib/gdb.exp b/gdb/testsuite/lib/gdb.exp index ea498c430405..2adfd4b1bcfe 100644 --- a/gdb/testsuite/lib/gdb.exp +++ b/gdb/testsuite/lib/gdb.exp @@ -5094,6 +5094,64 @@ gdb_caching_proc allow_aarch64_mops_tests {} { return $allow_mops_tests } +# Run a test on the target to see if it supports Aarch64 GCS extensions. +# Return 0 if so, 1 if it does not. Note this causes a restart of GDB. + +gdb_caching_proc allow_aarch64_gcs_tests {} { + global srcdir subdir gdb_prompt inferior_exited_re + + set me "allow_aarch64_gcs_tests" + + if { ![is_aarch64_target]} { + return 0 + } + + # Compile a program that tests the GCS feature. + set src { + #include + #include + + /* Feature check for Guarded Control Stack. */ + #ifndef HWCAP_GCS + #define HWCAP_GCS (1UL << 32) + #endif + + int main (void) { + bool gcs_supported = getauxval (AT_HWCAP) & HWCAP_GCS; + + /* Return success if GCS is supported. */ + return !gcs_supported; + } + } + + if {![gdb_simple_compile $me $src executable]} { + return 0 + } + + # Compilation succeeded so now run it via gdb. + clean_restart $obj + gdb_run_cmd + gdb_expect { + -re ".*$inferior_exited_re with code 01.*${gdb_prompt} $" { + verbose -log "\n$me gcs support not detected" + set allow_gcs_tests 0 + } + -re ".*$inferior_exited_re normally.*${gdb_prompt} $" { + verbose -log "\n$me: gcs support detected" + set allow_gcs_tests 1 + } + default { + warning "\n$me: default case taken" + set allow_gcs_tests 0 + } + } + gdb_exit + remote_file build delete $obj + + verbose "$me: returning $allow_gcs_tests" 2 + return $allow_gcs_tests +} + # A helper that compiles a test case to see if __int128 is supported. proc gdb_int128_helper {lang} { return [gdb_can_simple_compile "i128-for-$lang" { From patchwork Sun Jun 8 01:03:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thiago Jung Bauermann X-Patchwork-Id: 894808 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:ecd:b0:3a4:ee3f:8f15 with SMTP id ea13csp1177591wrb; Sat, 7 Jun 2025 18:14:39 -0700 (PDT) X-Forwarded-Encrypted: i=3; AJvYcCXODYLejKpwOBRknyxYFLeDtmtfWv3SefniceUAQD16oFedyJApWm2JB4iMpUmkt3xsxig3aA==@linaro.org X-Google-Smtp-Source: AGHT+IGMa9jEhAA4Z6VhvOTK8a8Nd9LncT1FgZZUcgtXZtRwQ4GTdMYqO5FeUXCxcMLkpABTnELv X-Received: by 2002:a05:6214:d0a:b0:6ed:df6:cdcd with SMTP id 6a1803df08f44-6fb08f6e27fmr140958196d6.21.1749345279721; Sat, 07 Jun 2025 18:14:39 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1749345279; cv=pass; d=google.com; s=arc-20240605; b=AuREg4SnQKgOkzhzXoSzeND79Kujv8xbvL+saHVIq2A5cUNSHCA3/unrPQCxZD4Rpe dQCukveug7+5MckkQIxmNIQyCNHa0JOPcNrlQp1p2VvdcLzpNfrXkjPsmY1HxRGaCCX4 eB+yiWkgruxktDZnfBcQn1FaYMkS3j1YXNMbNnnvzcQ1yRYEs6saj+PYBMM7w6a2g7/w luTVT1KY849ODLGW3Gvs94VuC6zDyLx0iRjKMbxVbhTEgT+dqhl1D9hdnFqjxaXvuqU7 dZDxZcgqxl3IxdpM0rJq723lV+FTVqJD15lUHEpZLe80Ch9TbETPNoqk5iVj2DH2kez8 f7sw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:dkim-filter:arc-filter:dmarc-filter:delivered-to :dkim-filter; bh=UUDIpZQEuR/3Vkym4M05JsegAxbJWfIO4yDqHYzoInw=; fh=72kqq0iQhigvR9Vv/oqX5ebs3Yyyw7XhzWxOOEPdupI=; b=Q4rfFohDNgMJ+w2nFVxo9Jw5OUsyq8bOxdhGKxKCOzJu7XSuBp2/cCex355mdZYDv3 tzAepKV8/n9vwe17wNYMrvIEcNo/xRmlBDtdDmckCYa5wWTXZ7XFM3yG1rEo2i706a6v dzuTFv9XBItWYqLyQRHcA4ze9+BVtUjDRSR9J53MBeb39qCCcDBPc8QfVMd3WjrfUkgH e/HCtWjqp716fzO7rLzLcY+1OJ44AqsonnGMPm54pb93NimZV5UyYQsd+hDE8/xBE8eH 7WESITmoEvGRYfd+8xsgdwU8UQk+9De5VdANgDDPId8CXx7zr2lffKS+sSoXCbn8cg/R 8++Q==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aBEAE5H7; arc=pass (i=1); spf=pass (google.com: domain of gdb-patches-bounces~patch=linaro.org@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gdb-patches-bounces~patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. 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Sat, 07 Jun 2025 18:04:04 -0700 (PDT) Received: from localhost ([2804:14d:7e39:88d6:8cb1:1e8e:e951:f687]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-87ece19b65esm921570241.9.2025.06.07.18.04.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jun 2025 18:04:04 -0700 (PDT) From: Thiago Jung Bauermann To: gdb-patches@sourceware.org Subject: [PATCH 7/8] GDB: testsuite: Add gdb.arch/aarch64-gcs-core.exp testcase Date: Sat, 7 Jun 2025 22:03:18 -0300 Message-ID: <20250608010338.2234530-8-thiago.bauermann@linaro.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250608010338.2234530-1-thiago.bauermann@linaro.org> References: <20250608010338.2234530-1-thiago.bauermann@linaro.org> MIME-Version: 1.0 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~patch=linaro.org@sourceware.org It tests both gcore and OS-generated core files. --- gdb/testsuite/gdb.arch/aarch64-gcs-core.c | 124 ++++++++++++++++++++ gdb/testsuite/gdb.arch/aarch64-gcs-core.exp | 105 +++++++++++++++++ gdb/testsuite/lib/gdb.exp | 4 +- 3 files changed, 231 insertions(+), 2 deletions(-) create mode 100644 gdb/testsuite/gdb.arch/aarch64-gcs-core.c create mode 100644 gdb/testsuite/gdb.arch/aarch64-gcs-core.exp diff --git a/gdb/testsuite/gdb.arch/aarch64-gcs-core.c b/gdb/testsuite/gdb.arch/aarch64-gcs-core.c new file mode 100644 index 000000000000..d04bd76e0799 --- /dev/null +++ b/gdb/testsuite/gdb.arch/aarch64-gcs-core.c @@ -0,0 +1,124 @@ +/* This test program is part of GDB, the GNU debugger. + + Copyright 2025 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include +#include +#include +#include +#include + +/* Feature check for Guarded Control Stack. */ +#ifndef HWCAP_GCS +#define HWCAP_GCS (1UL << 32) +#endif + +#ifndef PR_GET_SHADOW_STACK_STATUS +#define PR_GET_SHADOW_STACK_STATUS 74 +#define PR_SET_SHADOW_STACK_STATUS 75 +#define PR_SHADOW_STACK_ENABLE (1UL << 0) +#endif + +/* We need to use a macro to call prctl because after GCS is enabled, it's not + possible to return from the function which enabled it. This is because the + return address of the calling function isn't on the GCS. */ +#define my_syscall2(num, arg1, arg2) \ + ({ \ + register long _num __asm__("x8") = (num); \ + register long _arg1 __asm__("x0") = (long)(arg1); \ + register long _arg2 __asm__("x1") = (long)(arg2); \ + register long _arg3 __asm__("x2") = 0; \ + register long _arg4 __asm__("x3") = 0; \ + register long _arg5 __asm__("x4") = 0; \ + \ + __asm__ volatile("svc #0\n" \ + : "=r"(_arg1) \ + : "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), \ + "r"(_arg5), "r"(_num) \ + : "memory", "cc"); \ + _arg1; \ + }) + +#define get_gcspr(void) \ + ({ \ + unsigned long *gcspr; \ + \ + /* Get GCSPR_EL0. */ \ + asm volatile("mrs %0, S3_3_C2_C5_1" : "=r"(gcspr) : : "cc"); \ + \ + gcspr; \ + }) + +/* Corrupt the return address to see if GDB will report a SIGSEGV with the + expected + $_siginfo.si_code. */ +static void __attribute__ ((noinline)) +function (unsigned long *gcspr) +{ + /* x30 holds the return address. */ + register long x30 __asm__("x30") __attribute__ ((unused)); + + /* Print GCSPR to stdout so that the testcase can capture it. */ + printf ("%p\n", get_gcspr ()); + fflush (stdout); + + /* Cause a GCS exception. */ + x30 = 0xbadc0ffee; + __asm__ volatile("ret\n"); +} + +int +main (void) +{ + if (!(getauxval (AT_HWCAP) & HWCAP_GCS)) + { + fprintf (stderr, "GCS support not found in AT_HWCAP\n"); + return EXIT_FAILURE; + } + + /* Force shadow stacks on, our tests *should* be fine with or + without libc support and with or without this having ended + up tagged for GCS and enabled by the dynamic linker. We + can't use the libc prctl() function since we can't return + from enabling the stack. Also lock GCS if not already + locked so we can test behaviour when it's locked. */ + unsigned long gcs_mode; + int ret = my_syscall2 (__NR_prctl, PR_GET_SHADOW_STACK_STATUS, &gcs_mode); + if (ret) + { + fprintf (stderr, "Failed to read GCS state: %d\n", ret); + return EXIT_FAILURE; + } + + if (!(gcs_mode & PR_SHADOW_STACK_ENABLE)) + { + gcs_mode = PR_SHADOW_STACK_ENABLE; + ret = my_syscall2 (__NR_prctl, PR_SET_SHADOW_STACK_STATUS, gcs_mode); + if (ret) + { + fprintf (stderr, "Failed to configure GCS: %d\n", ret); + return EXIT_FAILURE; + } + } + + unsigned long *gcspr = get_gcspr (); + + /* Pass gscpr to function just so it's used for something. */ + function (gcspr); /* Break here. */ + + /* Avoid returning, in case libc doesn't understand GCS. */ + exit (EXIT_SUCCESS); +} diff --git a/gdb/testsuite/gdb.arch/aarch64-gcs-core.exp b/gdb/testsuite/gdb.arch/aarch64-gcs-core.exp new file mode 100644 index 000000000000..17bbb5e4ded9 --- /dev/null +++ b/gdb/testsuite/gdb.arch/aarch64-gcs-core.exp @@ -0,0 +1,105 @@ +# Copyright 2025 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# Test reading and writing the core dump of a binary that uses a Guarded +# Control Stack. + +require allow_aarch64_gcs_tests + +standard_testfile + +if { [prepare_for_testing "failed to prepare" $testfile $srcfile] } { + return +} + +set linespec ${srcfile}:[gdb_get_line_number "Break here"] + +if ![runto $linespec] { + return +} + +# Continue until a crash. The line with the hex number is optional because +# it's printed by the test program, and doesn't appear in the Expect buffer +# when testing a remote target. +gdb_test "continue" \ + [multi_line \ + "Continuing\\." \ + "($hex\r\n)?" \ + "Program received signal SIGSEGV, Segmentation fault" \ + "Guarded Control Stack error\\." \ + "function \\(gcspr=$hex\\) at .*aarch64-gcs-core.c:$decimal" \ + {.*__asm__ volatile\("ret\\n"\);}] \ + "continue to SIGSEGV" + +set gcspr_in_gcore [get_valueof "/x" "\$gcspr" "*unknown*"] + +# Generate the gcore core file. +set gcore_filename [standard_output_file "${testfile}.gcore"] +set gcore_generated [gdb_gcore_cmd "$gcore_filename" "generate gcore file"] + +# Obtain an OS-generated core file. +set core_filename [core_find $binfile {} {} "${binfile}.out"] +set core_generated [expr {$core_filename != ""}] +set os_core_name "${binfile}.core" +remote_exec build "mv $core_filename $os_core_name" +set core_filename $os_core_name + +# At this point we have a couple of core files, the gcore one generated by +# GDB and the one generated by the operating system. Make sure GDB can +# read both correctly. + +proc check_core_file {core_filename saved_gcspr} { + global decimal hex + + # Load the core file. + if [gdb_test "core $core_filename" \ + [multi_line \ + "Core was generated by .*\\." \ + "Program terminated with signal SIGSEGV, Segmentation fault" \ + "Guarded Control Stack error\\." \ + "#0 function \\(gcspr=$hex\\) at .*aarch64-gcs-core.c:$decimal" \ + "$decimal.*__asm__ volatile\\(\"ret\\\\n\"\\);"] \ + "load core file"] { + return -1 + } + + # Check the value of GCSPR in the core file. + gdb_test "print/x \$gcspr" "\\$\[0-9\]+ = $saved_gcspr" \ + "gcspr contents from core file" +} + +if {$gcore_generated} { + clean_restart $binfile + + with_test_prefix "gcore corefile" { + check_core_file $gcore_filename $gcspr_in_gcore + } +} else { + fail "gcore corefile not generated" +} + +if {$core_generated} { + clean_restart $binfile + + with_test_prefix "OS corefile" { + set out_id [open ${binfile}.out "r"] + set gcspr_in_core [gets $out_id] + + close $out_id + check_core_file $core_filename $gcspr_in_core + } +} else { + untested "OS corefile not generated" +} diff --git a/gdb/testsuite/lib/gdb.exp b/gdb/testsuite/lib/gdb.exp index 2adfd4b1bcfe..cf0b7cb9562d 100644 --- a/gdb/testsuite/lib/gdb.exp +++ b/gdb/testsuite/lib/gdb.exp @@ -9408,7 +9408,7 @@ proc remove_core {pid {test ""}} { } } -proc core_find {binfile {deletefiles {}} {arg ""}} { +proc core_find {binfile {deletefiles {}} {arg ""} {output_file "/dev/null"}} { global objdir subdir set destcore "$binfile.core" @@ -9430,7 +9430,7 @@ proc core_find {binfile {deletefiles {}} {arg ""}} { set found 0 set coredir [standard_output_file coredir.[getpid]] file mkdir $coredir - catch "system \"(cd ${coredir}; ulimit -c unlimited; ${binfile} ${arg}; true) >/dev/null 2>&1\"" + catch "system \"(cd ${coredir}; ulimit -c unlimited; ${binfile} ${arg}; true) >${output_file} 2>&1\"" # remote_exec host "${binfile}" foreach i "${coredir}/core ${coredir}/core.coremaker.c ${binfile}.core" { if [remote_file build exists $i] { From patchwork Sun Jun 8 01:03:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thiago Jung Bauermann X-Patchwork-Id: 894809 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:ecd:b0:3a4:ee3f:8f15 with SMTP id ea13csp1177925wrb; Sat, 7 Jun 2025 18:16:06 -0700 (PDT) X-Forwarded-Encrypted: i=3; AJvYcCXX0HnmOt8lQ7/gwgnqDHF1VG904GItE+IecRuC+njoFMNynm7YHY1loJhcfQRapRKmrdj7Lw==@linaro.org X-Google-Smtp-Source: AGHT+IHi+4nsCk1//B9JaEtXybj/PfQMqwIQgRT2SyWg6lyNKctDVCfXYKIdrAh/n9lSWMIMENz1 X-Received: by 2002:a05:620a:1987:b0:7c5:d888:7098 with SMTP id af79cd13be357-7d2298db637mr1382709885a.44.1749345366175; Sat, 07 Jun 2025 18:16:06 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1749345366; cv=pass; d=google.com; s=arc-20240605; b=WgJw+q/QKdvenAvoUYdvJuXYG9pkWwZLCm04hFTCZTFkwr0I9McHH1bX+pHhzVYoD6 fA+SGxxZFDsOAllxpX/7aO/cWDsR3RgnrqEv/J3BieZUWbJApSOEAqlWcnuI20K/H8/A cGwTPzT8kxzbaode2cj33TzU7aRoMJN7LIasrLhpsUDVLtgBuLVx/BgJWeNea8zqnf/c 95GXsZ2Uqz3kXGUTvXGyrbfjtgnRwTZqe6bVDIrBGeHXjIRF/QlAGxe6yR86ZjoHbzvr qfQfQ+67089z1+uCqhhA/ZYIqyDuOtAKb8PsRwy/Eo4+XpQ7Ns7cDFhm1i75lwtqFh0X jvGg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:dkim-filter:arc-filter:dmarc-filter:delivered-to :dkim-filter; bh=cbk+8QpY5sEVKFfP3xJwVJZCtGobl1/PKtxfghKaX1I=; fh=72kqq0iQhigvR9Vv/oqX5ebs3Yyyw7XhzWxOOEPdupI=; b=Pyt3XMBJNvkh6jGlIHY5W5WrLhn2oopDNVpPPzU/IgTBIv/PgZSKMwKAqb8b9dfLId GwlEqOQlJwLzzqD5/hyvIBTAumuXStYUXFgXtT/lzM53uhfAhyPzPHMDGAjFqZLAjS4b bfYkBGF/RXe/A89ccaFB9pMIHmNGs/2RelX5wesWKQyn3oq3o4PuQ9KvilCsY+FwkPtr lXKbrh/BcMn2HW+rEcNII4sEJqun5/9BerLdPQDUy70OJUoiMVH3vzJ//wOvn0qHkCME gSggWZfakGjZyXkBgvXxYZkYbNPMhAWMU4W6A0dBSy5F47l8Pf0LIrqdA+GCWadVF8ab 4gAw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mb9CRdqH; arc=pass (i=1); spf=pass (google.com: domain of gdb-patches-bounces~patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gdb-patches-bounces~patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. 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Sat, 07 Jun 2025 18:04:07 -0700 (PDT) Received: from localhost ([2804:14d:7e39:88d6:8cb1:1e8e:e951:f687]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-530e62f0c78sm3013947e0c.20.2025.06.07.18.04.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jun 2025 18:04:07 -0700 (PDT) From: Thiago Jung Bauermann To: gdb-patches@sourceware.org Subject: [PATCH 8/8] GDB: testsuite: Add gdb.arch/aarch64-gcs-disp-step.exp testcase Date: Sat, 7 Jun 2025 22:03:19 -0300 Message-ID: <20250608010338.2234530-9-thiago.bauermann@linaro.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250608010338.2234530-1-thiago.bauermann@linaro.org> References: <20250608010338.2234530-1-thiago.bauermann@linaro.org> MIME-Version: 1.0 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~patch=linaro.org@sourceware.org It exercises GCS with displaced stepping by putting the breakpoint on the bl instruction to force GDB to copy it to the displaced stepping buffer. In this case GDB needs to manually manage the Guarded Control Stack. --- .../gdb.arch/aarch64-gcs-disp-step.c | 140 ++++++++++++++++++ .../gdb.arch/aarch64-gcs-disp-step.exp | 90 +++++++++++ 2 files changed, 230 insertions(+) create mode 100644 gdb/testsuite/gdb.arch/aarch64-gcs-disp-step.c create mode 100644 gdb/testsuite/gdb.arch/aarch64-gcs-disp-step.exp diff --git a/gdb/testsuite/gdb.arch/aarch64-gcs-disp-step.c b/gdb/testsuite/gdb.arch/aarch64-gcs-disp-step.c new file mode 100644 index 000000000000..3d895350ae42 --- /dev/null +++ b/gdb/testsuite/gdb.arch/aarch64-gcs-disp-step.c @@ -0,0 +1,140 @@ +/* This test program is part of GDB, the GNU debugger. + + Copyright 2025 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include +#include +#include +#include +#include + +/* Feature check for Guarded Control Stack. */ +#ifndef HWCAP_GCS +#define HWCAP_GCS (1UL << 32) +#endif + +#ifndef PR_GET_SHADOW_STACK_STATUS +#define PR_GET_SHADOW_STACK_STATUS 74 +#define PR_SET_SHADOW_STACK_STATUS 75 +#define PR_SHADOW_STACK_ENABLE (1UL << 0) +#endif + +/* We need to use a macro to call prctl because after GCS is enabled, it's not + possible to return from the function which enabled it. This is because the + return address of the calling function isn't on the GCS. */ +#define my_syscall2(num, arg1, arg2) \ + ({ \ + register long _num __asm__("x8") = (num); \ + register long _arg1 __asm__("x0") = (long)(arg1); \ + register long _arg2 __asm__("x1") = (long)(arg2); \ + register long _arg3 __asm__("x2") = 0; \ + register long _arg4 __asm__("x3") = 0; \ + register long _arg5 __asm__("x4") = 0; \ + \ + __asm__ volatile("svc #0\n" \ + : "=r"(_arg1) \ + : "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), \ + "r"(_arg5), "r"(_num) \ + : "memory", "cc"); \ + _arg1; \ + }) + +#define get_gcspr(void) \ + ({ \ + unsigned long *gcspr; \ + \ + /* Get GCSPR_EL0. */ \ + asm volatile("mrs %0, S3_3_C2_C5_1" : "=r"(gcspr) : : "cc"); \ + \ + gcspr; \ + }) + +static int __attribute__ ((noinline)) +function2 (void) +{ + return EXIT_SUCCESS; +} + +/* Put branch and link instructions being tested into their own functions so + that the program returns one level up in the stack after the displaced + stepped instruction. This tests that GDB doesn't leave the GCS out of sync + with the regular stack. */ + +static int __attribute__ ((noinline)) +function_bl (void) +{ + register int x0 __asm__("x0"); + + __asm__ ("bl function2\n" + : "=r"(x0) + : + : "x30"); + + return x0; +} + +static int __attribute__ ((noinline)) +function_blr (void) +{ + register int x0 __asm__("x0"); + + __asm__ ("blr %1\n" + : "=r"(x0) + : "r"(&function2) + : "x30"); + + return x0; +} + +int +main (void) +{ + if (!(getauxval (AT_HWCAP) & HWCAP_GCS)) + { + fprintf (stderr, "GCS support not found in AT_HWCAP\n"); + return EXIT_FAILURE; + } + + /* Force shadow stacks on, our tests *should* be fine with or + without libc support and with or without this having ended + up tagged for GCS and enabled by the dynamic linker. We + can't use the libc prctl() function since we can't return + from enabling the stack. */ + unsigned long gcs_mode; + int ret = my_syscall2 (__NR_prctl, PR_GET_SHADOW_STACK_STATUS, &gcs_mode); + if (ret) + { + fprintf (stderr, "Failed to read GCS state: %d\n", ret); + return EXIT_FAILURE; + } + + if (!(gcs_mode & PR_SHADOW_STACK_ENABLE)) + { + gcs_mode = PR_SHADOW_STACK_ENABLE; + ret = my_syscall2 (__NR_prctl, PR_SET_SHADOW_STACK_STATUS, gcs_mode); + if (ret) + { + fprintf (stderr, "Failed to configure GCS: %d\n", ret); + return EXIT_FAILURE; + } + } + + int ret1 = function_bl (); + int ret2 = function_blr (); + + /* Avoid returning, in case libc doesn't understand GCS. */ + exit (ret1 + ret2); +} diff --git a/gdb/testsuite/gdb.arch/aarch64-gcs-disp-step.exp b/gdb/testsuite/gdb.arch/aarch64-gcs-disp-step.exp new file mode 100644 index 000000000000..10b09a4d980e --- /dev/null +++ b/gdb/testsuite/gdb.arch/aarch64-gcs-disp-step.exp @@ -0,0 +1,90 @@ +# Copyright 2025 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# Test displaced stepping in a program that uses a Guarded Control Stack. + +require allow_aarch64_gcs_tests + +standard_testfile + +if { [prepare_for_testing "failed to prepare" ${testfile} ${srcfile}] } { + return +} + +if ![runto_main] { + return +} + +gdb_test_no_output "set breakpoint auto-hw off" +gdb_test_no_output "set displaced-stepping on" + +# Get address of the branch and link instructions of interest. +set addr_bl 0 +set test "get address of bl instruction" +gdb_test_multiple "disassemble function_bl" $test -lbl { + -re "\r\n\\s+($hex) <\\+${decimal}>:\\s+bl\\s+${hex} (?=\r\n)" { + set addr_bl $expect_out(1,string) + exp_continue + } + -re "$::gdb_prompt \$" { + gdb_assert { $addr_bl != 0 } $test + } +} + +set addr_blr 0 +set test "get address of blr instruction" +gdb_test_multiple "disassemble function_blr" $test -lbl { + -re "\r\n\\s+($hex) <\\+${decimal}>:\\s+blr\\s+x${decimal}(?=\r\n)" { + set addr_blr $expect_out(1,string) + exp_continue + } + -re "$::gdb_prompt \$" { + gdb_assert { $addr_blr != 0 } $test + } +} + +if { $addr_bl == 0 || $addr_blr == 0 } { + return +} + +gdb_test "break *$addr_bl" \ + "Breakpoint $decimal at $hex: file .*aarch64-gcs-disp-step.c, line ${decimal}." \ + "set breakpoint at bl instruction" + +gdb_test "break *$addr_blr" \ + "Breakpoint $decimal at $hex: file .*aarch64-gcs-disp-step.c, line ${decimal}." \ + "set breakpoint at blr instruction" + +gdb_test "continue" \ + [multi_line \ + {Continuing\.} \ + "" \ + "Breakpoint $decimal, function_bl \\(\\) at .*aarch64-gcs-disp-step.c:${decimal}(?: \\\[GCS error\\\])?" \ + {[^\r\n]+"bl function2\\n"}] \ + "continue to breakpoint at bl" + +gdb_test "continue" \ + [multi_line \ + {Continuing\.} \ + "" \ + "Breakpoint $decimal, $hex in function_blr \\(\\) at .*aarch64-gcs-disp-step.c:${decimal}(?: \\\[GCS error\\\])?" \ + {[^\r\n]+"blr %1\\n"}] \ + "continue to breakpoint at blr" + +gdb_test "continue" \ + [multi_line \ + "Continuing\\." \ + "\\\[Inferior 1 \\(process $decimal\\) exited normally\\\]"] \ + "continue until inferior exits"