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Bottomley" , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 1/3] scsi: ufs: qcom: Check gear against max gear in vop freq_to_gear() Date: Thu, 22 May 2025 10:15:35 +0800 Message-Id: <20250522021537.999107-2-quic_ziqichen@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250522021537.999107-1-quic_ziqichen@quicinc.com> References: <20250522021537.999107-1-quic_ziqichen@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIyMDAyMCBTYWx0ZWRfXw4u6hhgSoeVk LonC4+DnUzo7HUa07hiyFx6vSPhrRnrD3R7V6myQvHSN6eizpQ3h86P9/k//ScB6K9Nzt0iEaqa Mx6kAi00nGC5Um1NDRxXJ6f/JYntqP3c87N19OLDSFOTDE8b2aDgOAP5wrKJgp/YpDDga31Su9a jbtym6f3Q9j97cJKagd6onh43W+MpgZfc4p+RvPud5eueeshFrll3+KC9rEb+07j4Z7r/gM4Pud RkOU0huU4TH1fq94qky2nkj0487cFovJbDtVk9T/6JifQWdCTVjXKMG+MjuAU0raFV3s0K/9vAf WCRTK2iuZtiW7iWQ+n8hgRFiWwZvFwUrFC2xROA9EzJHR907TqC52PCGtv/K5EjqSAmLKnkLQc7 a0HF2VNikqiOnCgwYOnQUB7k40DeLg7zCMBacrSqPPeUaNfycEbjlEtU1De9AjTOMYR/cqc9 X-Authority-Analysis: v=2.4 cv=XeWJzJ55 c=1 sm=1 tr=0 ts=682e88d2 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=PY6Zn8H8AAAA:8 a=EUspDBNiAAAA:8 a=ufAJUjbdAAAA:8 a=9iMbsSLhhSMDkuc5M44A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 a=ySS05r0LPNlNiX1MMvNp:22 a=rB1ygNaI0PWiOa_UD5GD:22 X-Proofpoint-GUID: swtxMd67nYfxyR7XzWPg_Jz4WNzkGH28 X-Proofpoint-ORIG-GUID: swtxMd67nYfxyR7XzWPg_Jz4WNzkGH28 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-22_01,2025-05-20_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 bulkscore=0 spamscore=0 suspectscore=0 impostorscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505220020 The vop freq_to_gear() may return a gear greater than the negotiated max gear, return the negotiated max gear if the mapped gear is greater than it. Fixes: c02fe9e222d1 ("scsi: ufs: qcom: Implement the freq_to_gear_speed() vop") Signed-off-by: Ziqi Chen Reported-by: Neil Armstrong Closes: https://lore.kernel.org/all/c7f2476a-943a-4d73-ad80-802c91e5f880@linaro.org/ Tested-by: Neil Armstrong Reviewed-by: Bean Huo Tested-by: Loïc Minier --- v1 -> v2: 1. Instead of return 'gear', return '0' directly if didn't find mapped gear 2. Derectly return min_t(gear,max_gear) instead assign to 'gear' then return it. v2 -> v3: Replace hard code '0' with enum 'UFS_HS_DONT_CHANGE'. v3 -> v4: Rebased to 6.15/scsi-queue which the relevant patch applied to. --- drivers/ufs/host/ufs-qcom.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index d03a07402223..a97fe8eee27a 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1880,7 +1880,7 @@ static int ufs_qcom_config_esi(struct ufs_hba *hba) static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) { - u32 gear = 0; + u32 gear = UFS_HS_DONT_CHANGE; switch (freq) { case 403000000: @@ -1902,10 +1902,10 @@ static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) break; default: dev_err(hba->dev, "%s: Unsupported clock freq : %lu\n", __func__, freq); - break; + return UFS_HS_DONT_CHANGE; } - return gear; + return min_t(u32, gear, hba->max_pwr_info.info.gear_rx); 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Bottomley" , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 2/3] scsi: ufs: qcom: Map devfreq OPP freq to UniPro Core Clock freq Date: Thu, 22 May 2025 10:15:36 +0800 Message-Id: <20250522021537.999107-3-quic_ziqichen@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250522021537.999107-1-quic_ziqichen@quicinc.com> References: <20250522021537.999107-1-quic_ziqichen@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: NEguqf7Qb_xqT9fZnSh0WKeXn454ncDg X-Proofpoint-ORIG-GUID: NEguqf7Qb_xqT9fZnSh0WKeXn454ncDg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIyMDAyMCBTYWx0ZWRfXz5xnwWcAEHoU hZybGLV3ETRM9+1yLvuAs6vJc0INaHP71WdFk/hUy3TXXbEzpYSk9bratMpnAvq53jEgU1J7eEu Np53A96I1hfcPeF7YgDd/CepeE2r7LEtsy7U4YnBf4y5++XvmpWj9dZbuE0ouYB4eM3Wkh3Y41l q2XZLu00Z+HGeloA/ju4R5Z79QPN/KsVnR0zroIL/avnRGy7XumsdLtjwhihsvFuCWPxZUu1Asm 0uiOseQDr8lLq72IjofRdXbu2sbL+Plk+XoSc1qvW2dkie3BVPXuN9Z5XdzJKlOgdjX0zfjET0c Hnchn3OZor3V4yXKwzFOnLm61GM1TUv1KIbHWBbMok4YmM8H0Ee38KbfWVx0t2bfug7fT0C16LD SjXQfFkMipd6GTCKj59HTd3ihAMSJCJ1oHhyBWt3yfXmH/pponMrX19wwJmjwkUIPXsJVaGO X-Authority-Analysis: v=2.4 cv=R7UDGcRX c=1 sm=1 tr=0 ts=682e88d3 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VwQbUJbxAAAA:8 a=6H0WHjuAAAAA:8 a=COk6AnOGAAAA:8 a=PY6Zn8H8AAAA:8 a=EUspDBNiAAAA:8 a=fTclbksgIu1b3d37_U8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=Soq9LBFxuPC4vsCAQt-j:22 a=TjNXssC_j7lpFel5tvFf:22 a=ySS05r0LPNlNiX1MMvNp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-22_01,2025-05-20_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 mlxlogscore=999 priorityscore=1501 spamscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 mlxscore=0 impostorscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505220020 From: Can Guo On some platforms, the devfreq OPP freq may be different than the unipro core clock freq. Implement ufs_qcom_opp_freq_to_clk_freq() and use it to find the unipro core clk freq. Fixes: c02fe9e222d1 ("scsi: ufs: qcom: Implement the freq_to_gear_speed() vop") Signed-off-by: Can Guo Co-developed-by: Ziqi Chen Signed-off-by: Ziqi Chen Reported-by: Luca Weiss Closes: https://lore.kernel.org/linux-arm-msm/D9FZ9U3AEXW4.1I12FX3YQ3JPW@fairphone.com/ Tested-by: Luca Weiss Reviewed-by: Bean Huo Tested-by: Loïc Minier --- V2 -> V3: 1. Skip calling ufs_qcom_opp_freq_to_clk_freq() if freq is ULONG_MAX to avoid usless error prints. 2. Correct indentation size to follow Linux kernel coding style. v3 -> v4: Rebased to 6.15/scsi-queue which the relevant patch applied to. --- drivers/ufs/host/ufs-qcom.c | 81 ++++++++++++++++++++++++++++++++----- 1 file changed, 71 insertions(+), 10 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index a97fe8eee27a..0f30f057b870 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -99,7 +99,9 @@ static const struct __ufs_qcom_bw_table { }; static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); -static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq); +static unsigned long ufs_qcom_opp_freq_to_clk_freq(struct ufs_hba *hba, + unsigned long freq, char *name); +static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up, unsigned long freq); static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) { @@ -597,7 +599,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, return -EINVAL; } - err = ufs_qcom_set_core_clk_ctrl(hba, ULONG_MAX); + err = ufs_qcom_set_core_clk_ctrl(hba, true, ULONG_MAX); if (err) dev_err(hba->dev, "cfg core clk ctrl failed\n"); /* @@ -1316,29 +1318,46 @@ static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba, return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); } -static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq) +static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up, unsigned long freq) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); struct list_head *head = &hba->clk_list_head; struct ufs_clk_info *clki; u32 cycles_in_1us = 0; u32 core_clk_ctrl_reg; + unsigned long clk_freq; int err; + if (hba->use_pm_opp && freq != ULONG_MAX) { + clk_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk_unipro"); + if (clk_freq) { + cycles_in_1us = ceil(clk_freq, HZ_PER_MHZ); + goto set_core_clk_ctrl; + } + } + list_for_each_entry(clki, head, list) { if (!IS_ERR_OR_NULL(clki->clk) && !strcmp(clki->name, "core_clk_unipro")) { - if (!clki->max_freq) + if (!clki->max_freq) { cycles_in_1us = 150; /* default for backwards compatibility */ - else if (freq == ULONG_MAX) + break; + } + + if (freq == ULONG_MAX) { cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); - else - cycles_in_1us = ceil(freq, HZ_PER_MHZ); + break; + } + if (is_scale_up) + cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); + else + cycles_in_1us = ceil(clk_get_rate(clki->clk), HZ_PER_MHZ); break; } } +set_core_clk_ctrl: err = ufshcd_dme_get(hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), &core_clk_ctrl_reg); @@ -1381,7 +1400,7 @@ static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba, unsigned long f return ret; } /* set unipro core clock attributes and clear clock divider */ - return ufs_qcom_set_core_clk_ctrl(hba, freq); + return ufs_qcom_set_core_clk_ctrl(hba, true, freq); } static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) @@ -1413,7 +1432,7 @@ static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba, unsigned long freq) { /* set unipro core clock attributes and clear clock divider */ - return ufs_qcom_set_core_clk_ctrl(hba, freq); + return ufs_qcom_set_core_clk_ctrl(hba, false, freq); } static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up, @@ -1878,11 +1897,53 @@ static int ufs_qcom_config_esi(struct ufs_hba *hba) return ret; } +static unsigned long ufs_qcom_opp_freq_to_clk_freq(struct ufs_hba *hba, + unsigned long freq, char *name) +{ + struct ufs_clk_info *clki; + struct dev_pm_opp *opp; + unsigned long clk_freq; + int idx = 0; + bool found = false; + + opp = dev_pm_opp_find_freq_exact_indexed(hba->dev, freq, 0, true); + if (IS_ERR(opp)) { + dev_err(hba->dev, "Failed to find OPP for exact frequency %lu\n", freq); + return 0; + } + + list_for_each_entry(clki, &hba->clk_list_head, list) { + if (!strcmp(clki->name, name)) { + found = true; + break; + } + + idx++; + } + + if (!found) { + dev_err(hba->dev, "Failed to find clock '%s' in clk list\n", name); + dev_pm_opp_put(opp); + return 0; + } + + clk_freq = dev_pm_opp_get_freq_indexed(opp, idx); + + dev_pm_opp_put(opp); + + return clk_freq; +} + static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) { u32 gear = UFS_HS_DONT_CHANGE; + unsigned long unipro_freq; + + if (!hba->use_pm_opp) + return gear; - switch (freq) { + unipro_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk_unipro"); + switch (unipro_freq) { case 403000000: gear = UFS_HS_G5; break; From patchwork Thu May 22 02:15:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ziqi Chen X-Patchwork-Id: 891990 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62EEA126BF7; Thu, 22 May 2025 02:16:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747880179; cv=none; b=LpDjneGsRJTETU/sSf5rIZrmOjcP6suw7GeYNaMFG6aNzBvKkqvmn5PtpALFHpE1siT/AlnLVI5uBvo4/kpTsAlplz8toHNoePMBLl2gbzLtEjoexXTIffNK2lncAfdEqOshKQq+zvUVfgoYtzq/D5Hq60Opozf5+m/oaYaX4Jg= ARC-Message-Signature: i=1; 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Bottomley" , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 3/3] scsi: ufs: qcom: Call ufs_qcom_cfg_timers() in clock scaling path Date: Thu, 22 May 2025 10:15:37 +0800 Message-Id: <20250522021537.999107-4-quic_ziqichen@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250522021537.999107-1-quic_ziqichen@quicinc.com> References: <20250522021537.999107-1-quic_ziqichen@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: MOzyEFJxL0xakzpp8YEljGb59O844RP8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIyMDAyMCBTYWx0ZWRfX1GnKnlcU8xdq Bc3pAtKiOnLLufQIou9I9W+8Hd9qZeFhAsCwsUcsUd8Es3Cf9t2zEC3J6utB3sRauAQzDuFfwli yfoDN09gOoqA9ShwNM6sHeshQym1bgxtyn188KIV++gy96LccENDr5SvjC4HdxfQ+Fs4rScyj2D VLFBG81rohMGvCPwl5lOvlJchA/PnrvP7QenZNeQcxwKqGt7O9JIRSsbuPXrGwPGF7UgPSMZhSG d8lHI/aZbuY8OkRqWik66yCPadE+H8+vYe+XUylp2IKmW0MhI1g8zcUv60Bf+RlV7biNCVzGJnm uLjRoso0nxkiHCRV8otGnIM3MUgiT3OIKa1pPpbgmYJ8WMNn74eMhCmUOpZli1EgSwfYXb+yv/H OAl8hpILeuBFRCjKU65oN487bMpN5M9/hV2XeuBgx/v2BZuId5cNNpUGb/LK+TnMCxyAgRnp X-Proofpoint-GUID: MOzyEFJxL0xakzpp8YEljGb59O844RP8 X-Authority-Analysis: v=2.4 cv=dLCmmPZb c=1 sm=1 tr=0 ts=682e88d5 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VwQbUJbxAAAA:8 a=6H0WHjuAAAAA:8 a=COk6AnOGAAAA:8 a=PY6Zn8H8AAAA:8 a=EUspDBNiAAAA:8 a=x4qbwuVvB1nHrQTLSukA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=Soq9LBFxuPC4vsCAQt-j:22 a=TjNXssC_j7lpFel5tvFf:22 a=ySS05r0LPNlNiX1MMvNp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-22_01,2025-05-20_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 adultscore=0 bulkscore=0 phishscore=0 suspectscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505220020 From: Can Guo ufs_qcom_cfg_timers() is clock freq dependent like ufs_qcom_set_core_clk_ ctrl(), hence move ufs_qcom_cfg_timers() call to clock scaling path. In addition, do not assume the devfreq OPP freq is always the 'core_clock' freq although 'core_clock' is the first clock phandle in device tree, use ufs_qcom_opp_freq_to_clk_freq() to find the core clk freq. Signed-off-by: Can Guo Co-developed-by: Ziqi Chen Signed-off-by: Ziqi Chen Reported-by: Luca Weiss Closes: https://lore.kernel.org/linux-arm-msm/D9FZ9U3AEXW4.1I12FX3YQ3JPW@fairphone.com/ Tested-by: Luca Weiss Reviewed-by: Bean Huo Tested-by: Loïc Minier --- V2 -> V3: Skip calling ufs_qcom_opp_freq_to_clk_freq() if freq is ULONG_MAX to avoid usless error prints. v3 -> v4: Rebased to 6.15/scsi-queue which the relevant patch applied to. --- drivers/ufs/host/ufs-qcom.c | 49 ++++++++++++++++++++++--------------- 1 file changed, 29 insertions(+), 20 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 0f30f057b870..8c93de8f8de2 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -540,13 +540,14 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, * * @hba: host controller instance * @is_pre_scale_up: flag to check if pre scale up condition. + * @freq: target opp freq * Return: zero for success and non-zero in case of a failure. */ -static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up) +static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up, unsigned long freq) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); struct ufs_clk_info *clki; - unsigned long core_clk_rate = 0; + unsigned long clk_freq = 0; u32 core_clk_cycles_per_us; /* @@ -558,22 +559,34 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up) if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba)) return 0; + if (hba->use_pm_opp && freq != ULONG_MAX) { + clk_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk"); + if (clk_freq) + goto cfg_timers; + } + list_for_each_entry(clki, &hba->clk_list_head, list) { if (!strcmp(clki->name, "core_clk")) { + if (freq == ULONG_MAX) { + clk_freq = clki->max_freq; + break; + } + if (is_pre_scale_up) - core_clk_rate = clki->max_freq; + clk_freq = clki->max_freq; else - core_clk_rate = clk_get_rate(clki->clk); + clk_freq = clk_get_rate(clki->clk); break; } } +cfg_timers: /* If frequency is smaller than 1MHz, set to 1MHz */ - if (core_clk_rate < DEFAULT_CLK_RATE_HZ) - core_clk_rate = DEFAULT_CLK_RATE_HZ; + if (clk_freq < DEFAULT_CLK_RATE_HZ) + clk_freq = DEFAULT_CLK_RATE_HZ; - core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC; + core_clk_cycles_per_us = clk_freq / USEC_PER_SEC; if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); /* @@ -593,7 +606,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, switch (status) { case PRE_CHANGE: - if (ufs_qcom_cfg_timers(hba, false)) { + if (ufs_qcom_cfg_timers(hba, false, ULONG_MAX)) { dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__); return -EINVAL; @@ -849,17 +862,6 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, } break; case POST_CHANGE: - if (ufs_qcom_cfg_timers(hba, false)) { - dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", - __func__); - /* - * we return error code at the end of the routine, - * but continue to configure UFS_PHY_TX_LANE_ENABLE - * and bus voting as usual - */ - ret = -EINVAL; - } - /* cache the power mode parameters to use internally */ memcpy(&host->dev_req_params, dev_req_params, sizeof(*dev_req_params)); @@ -1394,7 +1396,7 @@ static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba, unsigned long f { int ret; - ret = ufs_qcom_cfg_timers(hba, true); + ret = ufs_qcom_cfg_timers(hba, true, freq); if (ret) { dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__); return ret; @@ -1431,6 +1433,13 @@ static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba, unsigned long freq) { + int ret; + + ret = ufs_qcom_cfg_timers(hba, false, freq); + if (ret) { + dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__); + return ret; + } /* set unipro core clock attributes and clear clock divider */ return ufs_qcom_set_core_clk_ctrl(hba, false, freq); }