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(unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id 1F95D3F7061; Tue, 20 May 2025 06:07:43 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , CC: Bharat Bhushan , Subject: [PATCH 1/4 v2] crypto: octeontx2: add timeout for load_fvc completion poll Date: Tue, 20 May 2025 18:37:34 +0530 Message-ID: <20250520130737.4181994-2-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250520130737.4181994-1-bbhushan2@marvell.com> References: <20250520130737.4181994-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIwMDEwNSBTYWx0ZWRfX7WNo3O7QzqXi fmx7NW0n8TJwzZZwy+NNweC7oyTSPFIriHviAu2Xcs17vn+n3ED/YmnhacmFilSEoPRkzGb5Qx0 aVHWV2iwhnx5Q1e91e/MsFNXP1nJMZtx07rqHatLGA9zVGayirt7Fzg1FPBVeVz/sLc5db1OvYb x8lhcaY9jROFd2vou5PY4+Q88oFvYyhWayGJZN7IIhQEa4tw2Fw+W76cAfoBxVA327TafGKP8R+ mm+LZJnZar8PqrLF5YI45rj8v5mIxq0bSx70VWUHBe8eA8HkKiWk0cEJeBa+a3xsst8rWkyZduB OP1Huoz21wjzEpkch+6i7Kk7BDlogthK9wyhnO7hdi7BU8SEfWzL3qho6fzzBy7BklIbM0ya8u4 uJmD920o4dCGS8KbDrE72aFXeSSyi6vUBpHSyfJe8EBPwovHMFZlMHEY1Ttf6+2ZP2xW2nCf X-Proofpoint-ORIG-GUID: KGc0KakT1Kx4ITyKx8BNaovJEtDRJ1t2 X-Authority-Analysis: v=2.4 cv=BqCdwZX5 c=1 sm=1 tr=0 ts=682c7ea5 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=VwQbUJbxAAAA:8 a=dP9LQboaRqI6G61vZ2MA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: KGc0KakT1Kx4ITyKx8BNaovJEtDRJ1t2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-20_05,2025-05-16_03,2025-03-28_01 Adds timeout to exit from possible infinite loop, which polls on CPT instruction(load_fvc) completion. Signed-off-by: Srujana Challa Signed-off-by: Bharat Bhushan Cc: #v6.5+ --- v1->v2: - No Change .../crypto/marvell/octeontx2/otx2_cptpf_ucode.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c index 78367849c3d5..9095dea2748d 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c @@ -1494,6 +1494,7 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_cptpf_dev *cptpf) dma_addr_t rptr_baddr; struct pci_dev *pdev; u32 len, compl_rlen; + int timeout = 10000; int ret, etype; void *rptr; @@ -1554,16 +1555,27 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_cptpf_dev *cptpf) etype); otx2_cpt_fill_inst(&inst, &iq_cmd, rptr_baddr); lfs->ops->send_cmd(&inst, 1, &cptpf->lfs.lf[0]); + timeout = 10000; while (lfs->ops->cpt_get_compcode(result) == - OTX2_CPT_COMPLETION_CODE_INIT) + OTX2_CPT_COMPLETION_CODE_INIT) { cpu_relax(); + udelay(1); + timeout--; + if (!timeout) { + ret = -ENODEV; + cptpf->is_eng_caps_discovered = false; + dev_warn(&pdev->dev, "Timeout on CPT load_fvc completion poll\n"); + goto error_no_response; + } + } cptpf->eng_caps[etype].u = be64_to_cpup(rptr); } - dma_unmap_single(&pdev->dev, rptr_baddr, len, DMA_BIDIRECTIONAL); cptpf->is_eng_caps_discovered = true; +error_no_response: + dma_unmap_single(&pdev->dev, rptr_baddr, len, DMA_BIDIRECTIONAL); free_result: kfree(result); lf_cleanup: From patchwork Tue May 20 13:07:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bharat Bhushan X-Patchwork-Id: 891379 Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5293A22D78D; Tue, 20 May 2025 13:08:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747746489; cv=none; b=IkfciPF3awQiPJ1wp2svQXd6oEl97Ulijv2tKBhDQQH7hKQHgLuonGV9Oznsf555tYLSPGXA1vVS5RPuqafmuOyX/sDPXE+wS1SOMNRRR5k4l4DVIrRD/0hNgfPqoRA/UlKfFBIshrgoYNtHm9H1bJPtQOW/LQnra1XU23E9EFE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747746489; c=relaxed/simple; bh=tEfLy6FVHZcie3IKvuRy6JFSYbRIvA56lw1COPPC9YE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QYEKvHpimnFhtbLTqQomA9IDDC4kcfiKsTzI7FRnvdng1hGOejMR3iuEC5rJsAtYFDIxegVO4GkojW9hiGuHXMtMT0TmtTIKVwvdTwperOCPdhjh5XZpy7vm5QPgjhKQXnI5RY/vJRFl9EQAQ7SU1aYCtzEeNN+YjF5OaXuqwM8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=NLU0gPOn; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="NLU0gPOn" Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54JNT7x3011159; Tue, 20 May 2025 06:08:01 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=S SLmtUS3te1snL6BRGN9tN+VKR2hhu6soJQA9DTvbOk=; b=NLU0gPOnOO8hKqZJa d4tW09qj5zMJlGSGiVi07ED2ji4qNzCWD5BOEYndxutiwpFhfln0vno9BjDJH5Ns wccJEWtyGV3Qg4CGUbJXt+FktuXmlOl6lWkq4uJ62ryLlNGe45k2MuMiJdKQ9M4/ lzDWp86P96Vxp9WjnWFuXJCTB1SB4pD2Uo2vlWQDLTiTEbQn4ER6eS5JbkvRL9LU 4vlygBGg17E9FcuBppwcRz1OxgEB6R58UPswlojSSCAWQIetCrPc8jNpG07Ku+Fp gdynt6NkkHM9447M+X7mEYIgqZg47gXTYkpPTRXVVALCLiVqPkypI0e2pw60VHxJ L3adg== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 46rebt18km-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 May 2025 06:08:01 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 20 May 2025 06:08:00 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 20 May 2025 06:08:00 -0700 Received: from bharat-OptiPlex-Tower-Plus-7020.. (unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id 741103F7065; Tue, 20 May 2025 06:07:56 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , CC: Bharat Bhushan , Subject: [PATCH 4/4 v2] crypto: octeontx2: Fix address alignment on CN10KB and CN10KA-B0 Date: Tue, 20 May 2025 18:37:37 +0530 Message-ID: <20250520130737.4181994-5-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250520130737.4181994-1-bbhushan2@marvell.com> References: <20250520130737.4181994-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIwMDEwNSBTYWx0ZWRfX4Qele+icYLbn bGwFnBW59MWjNUb1iyVH+awXF9oMoVopckc4kilRcpAXlvXbsyQWFg3Mmq2rmVHYg0Gy54vmRqm MD9lFOz0AgphQxX/MG10FrrOtyHQRumEnR+JTgXh/kJaTMx91lKd4h8QhMAd7/9J/aA1nmV0WQy 0xOmxvFbrZkEHWVHZTJsncFdvm0/yuansFrIQH6bCj+XQzi8YK6nhoe0ujZpyUONKGECSV+D9VR GT14nyAtdFYNpSbz3DDYdZnhMV5T+xHkVLVWUFYVVKmnCehRiLAs/Y9v/loNVWnn67m79H10WcR 7qTlfRqGYTo6Nxufo4k8FI7MLD8YoDII4VMnhrMBlaqHfwir/wRkmUUKbUXCRnRpiPIzim8olZY n/6yNHf4jwOzrcrVSZUbB4Vqj/A1Ha7rfAfkBXUf/2NbTUNfZccY1tCyv3xyKlUh89BHmEFV X-Proofpoint-ORIG-GUID: NVCHJ3yVRSytzNs950JmBf8zBc1HMC8y X-Authority-Analysis: v=2.4 cv=BqCdwZX5 c=1 sm=1 tr=0 ts=682c7eb1 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=VwQbUJbxAAAA:8 a=BhrP5AWxFkdJNdVQK0QA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: NVCHJ3yVRSytzNs950JmBf8zBc1HMC8y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-20_05,2025-05-16_03,2025-03-28_01 octeontx2 crypto driver allocates memory using kmalloc/kzalloc, and uses this memory for dma (does dma_map_single()). It assumes that kmalloc/kzalloc will return 128-byte aligned address. But kmalloc/kzalloc returns 8-byte aligned address after below changes: "9382bc44b5f5 arm64: allow kmalloc() caches aligned to the smaller cache_line_size() Memory allocated are used for following purpose: - Input data or scatter list address - 8-Byte alignment - Output data or gather list address - 8-Byte alignment - Completion address - 32-Byte alignment. This patch ensures all addresses are aligned as mentioned above. Signed-off-by: Bharat Bhushan Cc: #v6.8+ --- v1->v2: - Fixed memory padding size calculation as per review comment .../marvell/octeontx2/otx2_cpt_reqmgr.h | 59 ++++++++++++++----- 1 file changed, 44 insertions(+), 15 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h index bb4e067ae826..766fa63fb075 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h @@ -350,22 +350,47 @@ static inline struct otx2_cpt_inst_info * cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req, gfp_t gfp) { - u32 dlen = 0, g_len, sg_len, info_len; - int align = OTX2_CPT_DMA_MINALIGN; + u32 dlen = 0, g_len, s_len, sg_len, info_len; struct otx2_cpt_inst_info *info; - u16 g_sz_bytes, s_sz_bytes; u32 total_mem_len; int i; - g_sz_bytes = ((req->in_cnt + 2) / 3) * - sizeof(struct cn10kb_cpt_sglist_component); - s_sz_bytes = ((req->out_cnt + 2) / 3) * - sizeof(struct cn10kb_cpt_sglist_component); + /* Allocate memory to meet below alignment requirement: + * ---------------------------------- + * | struct otx2_cpt_inst_info | + * | (No alignment required) | + * | -----------------------------| + * | | padding for 8B alignment | + * |----------------------------------| + * | SG List Gather/Input memory | + * | Length = multiple of 32Bytes | + * | Alignment = 8Byte | + * |----------------------------------| + * | SG List Scatter/Output memory | + * | Length = multiple of 32Bytes | + * | Alignment = 8Byte | + * | (padding for below alignment) | + * | -----------------------------| + * | | padding for 32B alignment | + * |----------------------------------| + * | Result response memory | + * ---------------------------------- + */ - g_len = ALIGN(g_sz_bytes, align); - sg_len = ALIGN(g_len + s_sz_bytes, align); - info_len = ALIGN(sizeof(*info), align); - total_mem_len = sg_len + info_len + sizeof(union otx2_cpt_res_s); + info_len = sizeof(*info); + + g_len = ((req->in_cnt + 2) / 3) * + sizeof(struct cn10kb_cpt_sglist_component); + s_len = ((req->out_cnt + 2) / 3) * + sizeof(struct cn10kb_cpt_sglist_component); + sg_len = g_len + s_len; + + /* Allocate extra memory for SG and response address alignment */ + total_mem_len = ALIGN(info_len, OTX2_CPT_DPTR_RPTR_ALIGN) + sg_len; + total_mem_len = ALIGN(total_mem_len, OTX2_CPT_DPTR_RPTR_ALIGN); + total_mem_len += (OTX2_CPT_RES_ADDR_ALIGN - 1) & + ~(OTX2_CPT_DPTR_RPTR_ALIGN - 1); + total_mem_len += sizeof(union otx2_cpt_res_s); info = kzalloc(total_mem_len, gfp); if (unlikely(!info)) @@ -375,7 +400,9 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req, dlen += req->in[i].size; info->dlen = dlen; - info->in_buffer = (u8 *)info + info_len; + info->in_buffer = PTR_ALIGN((u8 *)info + info_len, + OTX2_CPT_DPTR_RPTR_ALIGN); + info->out_buffer = info->in_buffer + g_len; info->gthr_sz = req->in_cnt; info->sctr_sz = req->out_cnt; @@ -387,7 +414,7 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req, } if (sgv2io_components_setup(pdev, req->out, req->out_cnt, - &info->in_buffer[g_len])) { + info->out_buffer)) { dev_err(&pdev->dev, "Failed to setup scatter list\n"); goto destroy_info; } @@ -404,8 +431,10 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req, * Get buffer for union otx2_cpt_res_s response * structure and its physical address */ - info->completion_addr = info->in_buffer + sg_len; - info->comp_baddr = info->dptr_baddr + sg_len; + info->completion_addr = PTR_ALIGN((info->in_buffer + sg_len), + OTX2_CPT_RES_ADDR_ALIGN); + info->comp_baddr = ALIGN((info->dptr_baddr + sg_len), + OTX2_CPT_RES_ADDR_ALIGN); return info;