From patchwork Mon May 19 15:41:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 891500 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8186627932B; Mon, 19 May 2025 15:50:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747669827; cv=none; b=g3m8/psOG9MGo5Q0ha3i60EGo5KAi0XutOt7Ud+d5ziR0uBhAGFkpTfDvI9ozeXzoJw5OUmFaG6CWHnPGgMcEiehtKvg0UkDS0aL6Lu6i4OqPlhn2NJu9f081zTFUl0dPfw8hVddJyfXqX2xIhjRwTEbB+XT89oPnZ0wnOAoLwo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747669827; c=relaxed/simple; bh=HI59+3VsZAHzDG2lW8mj78HPsyNMQFBt0V6LHST9s0s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PbyWe9wEAaAJCZctE0E4KnE6XUtCx5yxUflSqZyg/jpVvgfeUTM2gBGzQjeA0VmicVZGrgdemffajk8VWTyP8E7dt8SSg7U5zE0vC2AaUcaCcQMmpGHsFYxYjV7D2xq0TvpoqjaJ6y2bfYSiFKcrsHFi7TYK10OJHGjblKZNBl4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=paaJkUuC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="paaJkUuC" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0065DC4CEEF; Mon, 19 May 2025 15:50:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747669827; bh=HI59+3VsZAHzDG2lW8mj78HPsyNMQFBt0V6LHST9s0s=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=paaJkUuCOgZ/lTYECQK4/sJW9HVQkjdamkMUCsXktyqg8rG4z95O95HJUIfvDCsMc jvxw4pRebTglUJGNmYOfXWkXbR87fUw3orp1PUepI8AmUMo1oE95BywMM0TBUE2Isp iDp8zpmC4aJ2r+xLhQ7mhQp15/tpMTsGV6719/aWHxjDuzwf3X8Bo3NCRts0ZUNS+w sw+jA4aY/WbpsB/77gyoK3jbjTTGKtfBnhhg9jjPP6YKYjkrxqMsby4VgCMxhyDITP KocEM/rK7SsRTO0XHpFz9Mgos6aVr4VPFeE/OX97FjjLqY7Suk/wYkUwgqHZhGu+dS acP4+lXtUCtrQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2E49C3DA6D; Mon, 19 May 2025 15:50:26 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Mon, 19 May 2025 16:41:06 +0100 Subject: [PATCH v6 1/7] clk: clk-axi-clkgen: fix fpfd_max frequency for zynq Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250519-dev-axi-clkgen-limits-v6-1-bc4b3b61d1d4@analog.com> References: <20250519-dev-axi-clkgen-limits-v6-0-bc4b3b61d1d4@analog.com> In-Reply-To: <20250519-dev-axi-clkgen-limits-v6-0-bc4b3b61d1d4@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org, dmaengine@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-spi@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Vinod Koul , Jean Delvare , Guenter Roeck , Michael Hennerich , Jonathan Cameron , Trevor Gamblin , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , David Lechner , Mark Brown , Mike Turquette X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747669828; l=999; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=5+y858CS+pLM6RSN4Bbzxos5w9xYK0rwoYDgzKAlxLk=; b=tamk4aw8ooIO0KwzFlKfPlcNPp2PXXfkMN/Cp7GtTJDwJODKTUzreO//ExrX9abFq0s9J259V C1H9qMaWDpNAoF7h5Be+x9rcMqgxoy+qLjWmdI8lGydQDfDisC5KQ0e X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá The fpfd_max frequency should be set to 450 MHz instead of 300 MHz. Well, it actually depends on the platform speed grade but we are being conservative for ultrascale so let's be consistent. In a following change we will set these limits at runtime. Fixes: 0e646c52cf0e ("clk: Add axi-clkgen driver") Signed-off-by: Nuno Sá --- drivers/clk/clk-axi-clkgen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 934e53a96dddac8ed61dd109cfc188f3a2a0539a..00bf799964c61a3efc042b0f3a9ec3bc8625c9da 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -118,7 +118,7 @@ static const struct axi_clkgen_limits axi_clkgen_zynqmp_default_limits = { static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = { .fpfd_min = 10000, - .fpfd_max = 300000, + .fpfd_max = 450000, .fvco_min = 600000, .fvco_max = 1200000, }; From patchwork Mon May 19 15:41:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 891263 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8180326C3B8; Mon, 19 May 2025 15:50:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747669827; cv=none; b=Lg0Q2HQAwNFoYYDGOhQcMfuDW4ir3jjuugTfiMJgS4aDLVDSJBKLkBtbBXiB3/cot2D2L20O+mWmJmg9KILIeUylyQMeK/DNzSsdFPi528nyycYkQbZluPLJC6UGblSaEXtNeEjjcnJPQYzkwoNqS5PLt6nj3inPAdf8hjYn4AU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747669827; c=relaxed/simple; bh=Lc+0ipnOsOyMrbnE9ygCUwscmE7Y6WD4G1olrBmxHzk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Q/+qcORqQhUoeGkLFlY6Ag/pPHYEAJXAESirFbqRjvMmXoDXJIZPAlp8HenTjUNjHBN8Uuf4DCn++JipezmBMuOc3xx3M+rV6vXV+uc9CzCIRrd6Vi/QKsVUryGVwldVEugjzr/AUAm47JfXnwgp/Y4ZyMN8lGl8unyyEagzF3I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KIsZt0VZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KIsZt0VZ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0EF3FC4CEE9; Mon, 19 May 2025 15:50:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747669827; bh=Lc+0ipnOsOyMrbnE9ygCUwscmE7Y6WD4G1olrBmxHzk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=KIsZt0VZO6IOlVN6Mwqw1i/Pubpi2mkILfAsucLYiHLoc7xJSK/IH+Hyo6KecTDvb D5UScGmpqPlGF8/Mtp3dWtojHVx/kwFpyqze3Dp5E72VU0xvek0J1ePS+dvB1B3+Oq o0cvSwsISKq3f3FP7wAKQ9vexstdOyeYzMkZQwhOu6JQ99oJrkrckBRBQt3FWPGGoF zE5+NZHjljEZBxWYivMxQ3zkklQJjw63CpPuPQ2ageVGN7dgt2kIvHGUqw9Bc2SJby P+rJ3xyG+8mMfraEQfh1wbopzzLvvAZGVuylNfhaOzsgo/zHkYoElnWPio1jjJudbK rghfS0SugoIYg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F12E8C54795; Mon, 19 May 2025 15:50:26 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Mon, 19 May 2025 16:41:07 +0100 Subject: [PATCH v6 2/7] clk: clk-axi-clkgen: make sure to include mod_devicetable.h Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250519-dev-axi-clkgen-limits-v6-2-bc4b3b61d1d4@analog.com> References: <20250519-dev-axi-clkgen-limits-v6-0-bc4b3b61d1d4@analog.com> In-Reply-To: <20250519-dev-axi-clkgen-limits-v6-0-bc4b3b61d1d4@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org, dmaengine@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-spi@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Vinod Koul , Jean Delvare , Guenter Roeck , Michael Hennerich , Jonathan Cameron , Trevor Gamblin , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , David Lechner , Mark Brown , Mike Turquette X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747669828; l=659; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=/HIQW7i7xy9rSNcN8n33vnPmXH+zPymhP7sV+jmjYCI=; b=jTfKe41+s39+r1n7FIUdDysTMeQd2qLmCSO1f7t2QqjsJoy2IwxMao0suEh7xk7RpCa7ZDxJN fGi/KcK4OpCB/8Q4whhkL8PTmI7udp70ZunzveDo21hnyxvhrf8v3Aw X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá The mod_devicetable header is the one to be used for struct of_device_id. Signed-off-by: Nuno Sá --- drivers/clk/clk-axi-clkgen.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 00bf799964c61a3efc042b0f3a9ec3bc8625c9da..2a95f9b220234a1245024a821c50e1eb9c104ac9 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #define AXI_CLKGEN_V2_REG_RESET 0x40 From patchwork Mon May 19 15:41:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 891501 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8178B257AFE; Mon, 19 May 2025 15:50:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747669827; cv=none; b=a0njPlbFg5jY00W9/Z1LOVSgCwtZ3zggnOGvYBEYSAwTPTfsLaFeWQl1aH1iCqJjL2WgGY3y2ReKIizd93yEyvFE8DPhzf/r7xs0z7YrrUDQggSbG2AUVtqPDW3yM/rBxLVPpbdfy148E+sZ+OZuZVEV39bkCtn+VfDNzaDYCMo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747669827; c=relaxed/simple; bh=IXbjRp0/6WB1BFu4fmqObyr9iAMWgyU/iRnztOSrl4g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rD8K7mJBcqE1a1SRen4osN270aFfrX1+M2veddm0e7cMRVR2kA7C9hU7oWMX8ctuWBhl99cvtNusXrF169pXoQCi42OP9njRpisA95m+DvSKWELLdXYVosY4fPhgHWFS2Vv3FihvdGpkJiL2uIGZrGmsGYi3/J7Ew0cnXYz6t5M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TWuXfJyd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TWuXfJyd" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1BFF4C4CEF3; Mon, 19 May 2025 15:50:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747669827; bh=IXbjRp0/6WB1BFu4fmqObyr9iAMWgyU/iRnztOSrl4g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=TWuXfJydEo1RdsXTJu97jfvvK/GwLlhEpBA6Y7uQgDmFXjuEZzS+rBnMoU4TO9kPN B86DFDYQyckdemrGh1JOaGpfkyA3qFeAp7fPNUqMP33ZjI2bsYT6LwW1+GijYHEvfT XSr6CAb5oNekKkHhHov5f1hN3VSkYzXwn5crXY4cUG1ZFHKIWKuOOJse9ZBFWeOYTB n2lnBFMsPxVkKMogu0Q/ZQln9xNFzMjMyCoGGf49w/JFfGGBNIRPIDDY/u18Igoj+j 0MBpYrPMOtlcp2dpzMqGL9rxdMOyxwp0Qzc25N6XEhZ4Xn7MjKJPKQw3V04E1M0b93 RMT3C8EqWyd6Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C3B9C3ABDD; Mon, 19 May 2025 15:50:27 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Mon, 19 May 2025 16:41:08 +0100 Subject: [PATCH v6 3/7] include: linux: move adi-axi-common.h out of fpga Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250519-dev-axi-clkgen-limits-v6-3-bc4b3b61d1d4@analog.com> References: <20250519-dev-axi-clkgen-limits-v6-0-bc4b3b61d1d4@analog.com> In-Reply-To: <20250519-dev-axi-clkgen-limits-v6-0-bc4b3b61d1d4@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org, dmaengine@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-spi@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Vinod Koul , Jean Delvare , Guenter Roeck , Michael Hennerich , Jonathan Cameron , Trevor Gamblin , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , David Lechner , Mark Brown , Mike Turquette , Xu Yilun , Jonathan Cameron X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747669828; l=4776; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=3mknuHZvN3Y6WPrZbTnuDXmG6PM4kA/iUzppWD7grjI=; b=TkRSD7gA6XE4pcE9aSWJBo+QVfd1UmPfOyrCS688zjI0BQpzte51vNtgGdoxyEFn1b2qxoAZM ZjNfFQeUKb/CY55cCPyY53/TKDaoqPXAACb92/GR0b6HPa6ASPxYdWK X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá The adi-axi-common.h header has some common defines used in various ADI IPs. However they are not specific for any fpga manager so it's questionable for the header to live under include/linux/fpga. Hence let's just move one directory up and update all users. Suggested-by: Xu Yilun Acked-by: Xu Yilun Acked-by: Jonathan Cameron # for IIO Signed-off-by: Nuno Sá --- drivers/dma/dma-axi-dmac.c | 2 +- drivers/hwmon/axi-fan-control.c | 2 +- drivers/iio/adc/adi-axi-adc.c | 3 +-- drivers/iio/dac/adi-axi-dac.c | 2 +- drivers/pwm/pwm-axi-pwmgen.c | 2 +- drivers/spi/spi-axi-spi-engine.c | 2 +- include/linux/{fpga => }/adi-axi-common.h | 0 7 files changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c index 36943b0c6d603cbe38606b0d7bde02535f529a9a..5b06b0dc67ee12017c165bf815fb7c0e1bf5abd8 100644 --- a/drivers/dma/dma-axi-dmac.c +++ b/drivers/dma/dma-axi-dmac.c @@ -6,6 +6,7 @@ * Author: Lars-Peter Clausen */ +#include #include #include #include @@ -22,7 +23,6 @@ #include #include #include -#include #include diff --git a/drivers/hwmon/axi-fan-control.c b/drivers/hwmon/axi-fan-control.c index 35c862eb158b0909dac64c2e9f51f0f9f0e8bf72..b7bb325c3ad966ed2a93be4dfbf4e20661568509 100644 --- a/drivers/hwmon/axi-fan-control.c +++ b/drivers/hwmon/axi-fan-control.c @@ -4,9 +4,9 @@ * * Copyright 2019 Analog Devices Inc. */ +#include #include #include -#include #include #include #include diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index c7357601f0f869e57636f00bb1e26c059c3ab15c..87fa18f1ec96782556bdfad08bedb5e7549fb93d 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -6,6 +6,7 @@ * Copyright 2012-2020 Analog Devices Inc. */ +#include #include #include #include @@ -20,8 +21,6 @@ #include #include -#include - #include #include #include diff --git a/drivers/iio/dac/adi-axi-dac.c b/drivers/iio/dac/adi-axi-dac.c index b143f7ed6847277aeb49094627d90e5d95eed71c..581a2fe55a7fb35f1a03f96f3a0e95421d1583e7 100644 --- a/drivers/iio/dac/adi-axi-dac.c +++ b/drivers/iio/dac/adi-axi-dac.c @@ -5,6 +5,7 @@ * * Copyright 2016-2024 Analog Devices Inc. */ +#include #include #include #include @@ -23,7 +24,6 @@ #include #include -#include #include #include #include diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c index 4259a0db9ff45808eecae28680473292d165d1f6..e720191e74558d15f1b04fa18cf2984299f88809 100644 --- a/drivers/pwm/pwm-axi-pwmgen.c +++ b/drivers/pwm/pwm-axi-pwmgen.c @@ -18,10 +18,10 @@ * - Supports normal polarity. Does not support changing polarity. * - On disable, the PWM output becomes low (inactive). */ +#include #include #include #include -#include #include #include #include diff --git a/drivers/spi/spi-axi-spi-engine.c b/drivers/spi/spi-axi-spi-engine.c index 7c252126b33ea83fe6a6e80c6cb87499243069f5..d498132f1ff6adf20639bf4a21f1687903934bec 100644 --- a/drivers/spi/spi-axi-spi-engine.c +++ b/drivers/spi/spi-axi-spi-engine.c @@ -5,9 +5,9 @@ * Author: Lars-Peter Clausen */ +#include #include #include -#include #include #include #include diff --git a/include/linux/fpga/adi-axi-common.h b/include/linux/adi-axi-common.h similarity index 100% rename from include/linux/fpga/adi-axi-common.h rename to include/linux/adi-axi-common.h From patchwork Mon May 19 15:41:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 891264 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8171715D1; Mon, 19 May 2025 15:50:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747669827; cv=none; b=ReWMDU5/eW94kn4W7FdlWYVnUqJS/DWCacvRKtV3yf/e/ZBbEJqczaEVXWd9NgVmgpa86/8v66NR5oUVwIqjtvTH+7u0GS3Cz0hVOph8BZYq44z4UsAh3ze3gMMlzGoiqx/UAKn/X+L9fo2WTbNjbrclkkmCv2jRVBI7K9XAYXc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747669827; c=relaxed/simple; bh=CuLVQhdgIPjvHv0rQT6Dmcn56lz0D7swUmu5t+yoFYo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HRRVRbxJo2dGoYFtJt/Pk1rgrGrheLEohYBY/qRISP+4mT4d1CO9EuZQgIEK0Npwcx5wCEOlorT0r6pqf2W4rojRCV3qI2klXuWdq+2yLbFTc9G9t4znG9jfdeSg+gZB4Zovld/q5fOvBlfbLhzmOJ4Xp9wG+AkPT09Y613pxi4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SX8JyjWT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SX8JyjWT" Received: by smtp.kernel.org (Postfix) with ESMTPS id 25960C4CEF6; Mon, 19 May 2025 15:50:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747669827; bh=CuLVQhdgIPjvHv0rQT6Dmcn56lz0D7swUmu5t+yoFYo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=SX8JyjWT3S0h7mCaXdKxpfHrHcrb2ofxUT9B6/aRtz1ChymPQ/e3Q3jm2WTC+nWS6 2rjv+vXS1z4hjEnXIeiJSJdy77dIk5cmqcQZX+g2rIyfSXqOm7hadog46igXq1QJ8f 0UCtRBQWfnlraww1bVQ/7i2TCubso9MKA0Nc/5WsZijxMWB7YCfcQnrop36dsBC9RT kVScusZ3feralvtCvB6JzlW0zKnLzrrBnLU/aFco0hnnKUPyjeJ4bmW6eRVZVzHkVj lztBNuswTI+II6UyMWG8Mc0auzsBJ0JukwAWwshkInMgzqFZ7jrE+U3h5O3odhk8LQ 9rmlvoaRE9qbA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B20DC54799; Mon, 19 May 2025 15:50:27 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Mon, 19 May 2025 16:41:09 +0100 Subject: [PATCH v6 4/7] include: adi-axi-common: add new helper macros Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250519-dev-axi-clkgen-limits-v6-4-bc4b3b61d1d4@analog.com> References: <20250519-dev-axi-clkgen-limits-v6-0-bc4b3b61d1d4@analog.com> In-Reply-To: <20250519-dev-axi-clkgen-limits-v6-0-bc4b3b61d1d4@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org, dmaengine@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-spi@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Vinod Koul , Jean Delvare , Guenter Roeck , Michael Hennerich , Jonathan Cameron , Trevor Gamblin , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , David Lechner , Mark Brown , Mike Turquette X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747669828; l=1930; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=F9rmW1Daru1sdf4SDLslhcn5FXhJbwH5zOEXykHR5J4=; b=B7JGsfdbl+6++EvZGpKy68lHIc+iswr64DD1+xlRa98r3EpBWFgIhI3HlE4S+Y2jY8T8sHwjO 6V9zHqs4G+cAEAD2Hxp21lNU1/8r0NFRlfiDmuCvdAo67xU5SvYa1P4 X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá Add new helper macros and enums to help identifying the platform and some characteristics of it at runtime. Signed-off-by: Nuno Sá --- include/linux/adi-axi-common.h | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/include/linux/adi-axi-common.h b/include/linux/adi-axi-common.h index 141ac3f251e6f256526812b9d55cd440a2a46e76..f64f4ad4bedae312ec450bd5fed09ceaedd5397e 100644 --- a/include/linux/adi-axi-common.h +++ b/include/linux/adi-axi-common.h @@ -12,6 +12,7 @@ #define ADI_AXI_COMMON_H_ #define ADI_AXI_REG_VERSION 0x0000 +#define ADI_AXI_REG_FPGA_INFO 0x001C #define ADI_AXI_PCORE_VER(major, minor, patch) \ (((major) << 16) | ((minor) << 8) | (patch)) @@ -20,4 +21,36 @@ #define ADI_AXI_PCORE_VER_MINOR(version) (((version) >> 8) & 0xff) #define ADI_AXI_PCORE_VER_PATCH(version) ((version) & 0xff) +#define ADI_AXI_INFO_FPGA_TECH(info) (((info) >> 24) & 0xff) +#define ADI_AXI_INFO_FPGA_FAMILY(info) (((info) >> 16) & 0xff) +#define ADI_AXI_INFO_FPGA_SPEED_GRADE(info) (((info) >> 8) & 0xff) + +enum adi_axi_fpga_technology { + ADI_AXI_FPGA_TECH_UNKNOWN = 0, + ADI_AXI_FPGA_TECH_SERIES7, + ADI_AXI_FPGA_TECH_ULTRASCALE, + ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS, +}; + +enum adi_axi_fpga_family { + ADI_AXI_FPGA_FAMILY_UNKNOWN = 0, + ADI_AXI_FPGA_FAMILY_ARTIX, + ADI_AXI_FPGA_FAMILY_KINTEX, + ADI_AXI_FPGA_FAMILY_VIRTEX, + ADI_AXI_FPGA_FAMILY_ZYNQ, +}; + +enum adi_axi_fpga_speed_grade { + ADI_AXI_FPGA_SPEED_UNKNOWN = 0, + ADI_AXI_FPGA_SPEED_1 = 10, + ADI_AXI_FPGA_SPEED_1L = 11, + ADI_AXI_FPGA_SPEED_1H = 12, + ADI_AXI_FPGA_SPEED_1HV = 13, + ADI_AXI_FPGA_SPEED_1LV = 14, + ADI_AXI_FPGA_SPEED_2 = 20, + ADI_AXI_FPGA_SPEED_2L = 21, + ADI_AXI_FPGA_SPEED_2LV = 22, + ADI_AXI_FPGA_SPEED_3 = 30, +}; + #endif /* ADI_AXI_COMMON_H_ */ From patchwork Mon May 19 15:41:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 891499 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF30528643F; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AHFink7z" Received: by smtp.kernel.org (Postfix) with ESMTPS id 35E0AC4CEF9; Mon, 19 May 2025 15:50:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747669827; bh=+cK0fBqHccIiGa9CGO2qeuLfPzALRqohpfOHgcdKD4c=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=AHFink7zK8PdU07hXd212oDs5RDlqwTyz1jheSNzuH03EZFrIzOifHzV+lGjR17ng gKTISFTBKZWrKoU0HJRiEjagA63iHNYjtlVdbjN80LSupA7umU50uYytXxswqxhlQL FMXgieVF8qtxNsXQuqp2h7K5sKJ4x6oyno5eI+PkcSerz3SwOtP3ZsocBpXVIuRvjX GCj0fBiq5xSeIt3IJVrLJP2ICSXXIxYX9LphOuQP4256iB2Vq+S/gLXguvAQevSMB1 4jXKsxJXB5NqsG8WEuXJG3JhOnC2jpBf695BoE3qUVspMD9u+ee3q0mDtWnMce+c/Z 4rK9PTZfm6+0A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B059C2D0CD; Mon, 19 May 2025 15:50:27 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Mon, 19 May 2025 16:41:10 +0100 Subject: [PATCH v6 5/7] clk: clk-axi-clkgen: detect axi_clkgen_limits at runtime Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250519-dev-axi-clkgen-limits-v6-5-bc4b3b61d1d4@analog.com> References: <20250519-dev-axi-clkgen-limits-v6-0-bc4b3b61d1d4@analog.com> In-Reply-To: <20250519-dev-axi-clkgen-limits-v6-0-bc4b3b61d1d4@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org, dmaengine@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-spi@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Vinod Koul , Jean Delvare , Guenter Roeck , Michael Hennerich , Jonathan Cameron , Trevor Gamblin , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , David Lechner , Mark Brown , Mike Turquette X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747669828; l=3981; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=nuqSxH2DcFb0n5Cp5hJrZPhnAul6ayJrJavTFUfm6W8=; b=EP72A+xNs6i9+2wLrCQGiIpOvsX6aWdoj+MYtyGoxio5Ru2sYulayB6MJJdLSXy0TxcM37Oyf QpmRecRdZ82AshSfJiWGNzP3hAwy9LTVbc3BNjswZeYAyoKJUWe6Av9 X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá This patch adds support for setting the limits in struct axi_clkgen_limits in accordance with fpga speed grade, voltage, technology and family. This new information is extracted from two new registers implemented in the ip core that are only available for core versions higher or equal to 4. Signed-off-by: Nuno Sá --- drivers/clk/clk-axi-clkgen.c | 65 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 2a95f9b220234a1245024a821c50e1eb9c104ac9..f4e96394e9c25c817b09ee0c08751147083f19b7 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -6,6 +6,8 @@ * Author: Lars-Peter Clausen */ +#include +#include #include #include #include @@ -29,6 +31,9 @@ #define AXI_CLKGEN_V2_DRP_STATUS_BUSY BIT(16) +#define ADI_CLKGEN_REG_FPGA_VOLTAGE 0x0140 +#define ADI_CLKGEN_INFO_FPGA_VOLTAGE(val) ((val) & GENMASK(15, 0)) + #define MMCM_REG_CLKOUT5_2 0x07 #define MMCM_REG_CLKOUT0_1 0x08 #define MMCM_REG_CLKOUT0_2 0x09 @@ -497,6 +502,54 @@ static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw) return parent; } +static int axi_clkgen_setup_limits(struct axi_clkgen *axi_clkgen, + struct device *dev) +{ + unsigned int tech, family, speed_grade, reg_value; + + axi_clkgen_read(axi_clkgen, ADI_AXI_REG_FPGA_INFO, ®_value); + tech = ADI_AXI_INFO_FPGA_TECH(reg_value); + family = ADI_AXI_INFO_FPGA_FAMILY(reg_value); + speed_grade = ADI_AXI_INFO_FPGA_SPEED_GRADE(reg_value); + + axi_clkgen->limits.fpfd_min = 10000; + axi_clkgen->limits.fvco_min = 600000; + + switch (speed_grade) { + case ADI_AXI_FPGA_SPEED_1 ... ADI_AXI_FPGA_SPEED_1LV: + axi_clkgen->limits.fvco_max = 1200000; + axi_clkgen->limits.fpfd_max = 450000; + break; + case ADI_AXI_FPGA_SPEED_2 ... ADI_AXI_FPGA_SPEED_2LV: + axi_clkgen->limits.fvco_max = 1440000; + axi_clkgen->limits.fpfd_max = 500000; + if (family == ADI_AXI_FPGA_FAMILY_KINTEX || family == ADI_AXI_FPGA_FAMILY_ARTIX) { + axi_clkgen_read(axi_clkgen, ADI_CLKGEN_REG_FPGA_VOLTAGE, + ®_value); + if (ADI_CLKGEN_INFO_FPGA_VOLTAGE(reg_value) < 950) { + axi_clkgen->limits.fvco_max = 1200000; + axi_clkgen->limits.fpfd_max = 450000; + } + } + break; + case ADI_AXI_FPGA_SPEED_3: + axi_clkgen->limits.fvco_max = 1600000; + axi_clkgen->limits.fpfd_max = 550000; + break; + default: + return dev_err_probe(dev, -ENODEV, "Unknown speed grade %d\n", + speed_grade); + }; + + /* Overwrite vco limits for ultrascale+ */ + if (tech == ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS) { + axi_clkgen->limits.fvco_max = 1600000; + axi_clkgen->limits.fvco_min = 800000; + } + + return 0; +} + static const struct clk_ops axi_clkgen_ops = { .recalc_rate = axi_clkgen_recalc_rate, .determine_rate = axi_clkgen_determine_rate, @@ -511,6 +564,7 @@ static int axi_clkgen_probe(struct platform_device *pdev) { const struct axi_clkgen_limits *dflt_limits; struct axi_clkgen *axi_clkgen; + unsigned int pcore_version; struct clk_init_data init; const char *parent_names[2]; const char *clk_name; @@ -556,7 +610,16 @@ static int axi_clkgen_probe(struct platform_device *pdev) return -EINVAL; } - memcpy(&axi_clkgen->limits, dflt_limits, sizeof(axi_clkgen->limits)); + axi_clkgen_read(axi_clkgen, ADI_AXI_REG_VERSION, &pcore_version); + + if (ADI_AXI_PCORE_VER_MAJOR(pcore_version) > 0x04) { + ret = axi_clkgen_setup_limits(axi_clkgen, &pdev->dev); + if (ret) + return ret; + } else { + memcpy(&axi_clkgen->limits, dflt_limits, + sizeof(axi_clkgen->limits)); + } clk_name = pdev->dev.of_node->name; of_property_read_string(pdev->dev.of_node, "clock-output-names", From patchwork Mon May 19 15:41:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 891261 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6CAA286888; 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a=ed25519-sha256; t=1747669828; l=1495; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=vaKvm3+kPhk+H/SniKdwBonmjuu4MP+U2YF5ZE5OI/U=; b=/EuM5y8wZSRzx1k08B2WByFVhjxno3tJ+9m7SOwG8g5uPF1aqFc/N3zw24YW7E50ZgNfdV1Mm A4v/G8+reXvD8ElDBwJcOruFvd/NA3Xg6Ce4WSkSyYpCdPYlAYt8aPC X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá Instead of using the type versions of min/max(), use the plain ones as now they are perfectly capable of handling different types like unsigned and non negative integers that are compiletime constant. Signed-off-by: Nuno Sá --- drivers/clk/clk-axi-clkgen.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index f4e96394e9c25c817b09ee0c08751147083f19b7..63951209c460f26ed3940879da536e31ae530188 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -147,15 +147,15 @@ static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits, *best_m = 0; *best_dout = 0; - d_min = max_t(unsigned long, DIV_ROUND_UP(fin, limits->fpfd_max), 1); - d_max = min_t(unsigned long, fin / limits->fpfd_min, 80); + d_min = max(DIV_ROUND_UP(fin, limits->fpfd_max), 1); + d_max = min(fin / limits->fpfd_min, 80); again: fvco_min_fract = limits->fvco_min << fract_shift; fvco_max_fract = limits->fvco_max << fract_shift; - m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1); - m_max = min_t(unsigned long, fvco_max_fract * d_max / fin, 64 << fract_shift); + m_min = max(DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1); 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b=RFc5MKht3zyZ7Iglw/prYgFryVKKAGCGAmh96k1Nz+YQ2Vuo0CFfSTEFSbSBDpuwS xpmBfy0186OIdHwVYr/zKWW7lcnr+2L9I9MpK8GSzo8oxKCF+cqZ7OjuSrWSZVtdkh 4J+XUc9+S0WxjfXpLGwqJyYzU8G72P3yyya4hIFGz0Ic8IDCk5h4bPqvq7kycsZSjJ SMWeKZ3fxLr2jHXy7vXQV0+NYiXYD7kA3SsoXhviquoYesx/vndWGYpxyR4+RR6vE2 f1WR81Mx5kJ72fJLrxHt7QJnMvD2xxU7MhEBwyIyEkgfef3BJ9eX5T8gLb+En+6mf6 F3U5WBu9kHMqQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A905C54795; Mon, 19 May 2025 15:50:27 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Mon, 19 May 2025 16:41:12 +0100 Subject: [PATCH v6 7/7] clk: clk-axi-clkgen: fix coding style issues Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250519-dev-axi-clkgen-limits-v6-7-bc4b3b61d1d4@analog.com> References: <20250519-dev-axi-clkgen-limits-v6-0-bc4b3b61d1d4@analog.com> In-Reply-To: <20250519-dev-axi-clkgen-limits-v6-0-bc4b3b61d1d4@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org, dmaengine@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-spi@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Vinod Koul , Jean Delvare , Guenter Roeck , Michael Hennerich , Jonathan Cameron , Trevor Gamblin , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , David Lechner , Mark Brown , Mike Turquette X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747669828; l=8868; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=m/rE/6vHjXW3C/GGkPERYRMWfXU0zKnfzDzbTCbnR1M=; b=VwjNPfF0/wo6wH5wbvUSsY4a9GOrS9Ki4gE4Bqchk2/4bMxKB4YZvBMOnHplnD2ugC5fulA0N tIMJzruVJ8ZCLpqhjOk8a3wRW8uEBmHPvuGa+zjeSZ7qijt4pyMiyo0 X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá This is just cosmetics and so no functional changes intended. While at it, sort header in alphabetical order. Signed-off-by: Nuno Sá --- drivers/clk/clk-axi-clkgen.c | 81 ++++++++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 40 deletions(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 63951209c460f26ed3940879da536e31ae530188..2bb52c4dc7be5167380c1d158d96c7618d16c558 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -8,15 +8,15 @@ #include #include -#include #include #include -#include +#include #include -#include #include #include -#include +#include +#include +#include #define AXI_CLKGEN_V2_REG_RESET 0x40 #define AXI_CLKGEN_V2_REG_CLKSEL 0x44 @@ -96,7 +96,7 @@ static uint32_t axi_clkgen_lookup_filter(unsigned int m) } } -static const uint32_t axi_clkgen_lock_table[] = { +static const u32 axi_clkgen_lock_table[] = { 0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8, 0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8, 0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339, @@ -108,7 +108,7 @@ static const uint32_t axi_clkgen_lock_table[] = { 0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113, }; -static uint32_t axi_clkgen_lookup_lock(unsigned int m) +static u32 axi_clkgen_lookup_lock(unsigned int m) { if (m < ARRAY_SIZE(axi_clkgen_lock_table)) return axi_clkgen_lock_table[m]; @@ -130,8 +130,9 @@ static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = { }; static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits, - unsigned long fin, unsigned long fout, - unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout) + unsigned long fin, unsigned long fout, + unsigned int *best_d, unsigned int *best_m, + unsigned int *best_dout) { unsigned long d, d_min, d_max, _d_min, _d_max; unsigned long m, m_min, m_max; @@ -198,9 +199,9 @@ struct axi_clkgen_div_params { }; static void axi_clkgen_calc_clk_params(unsigned int divider, - unsigned int frac_divider, struct axi_clkgen_div_params *params) + unsigned int frac_divider, + struct axi_clkgen_div_params *params) { - memset(params, 0x0, sizeof(*params)); if (divider == 1) { @@ -228,7 +229,7 @@ static void axi_clkgen_calc_clk_params(unsigned int divider, if (params->edge == 0 || frac_divider == 1) params->low--; if (((params->edge == 0) ^ (frac_divider == 1)) || - (divider == 2 && frac_divider == 1)) + (divider == 2 && frac_divider == 1)) params->frac_wf_f = 1; params->frac_phase = params->edge * 4 + frac_divider / 2; @@ -236,13 +237,13 @@ static void axi_clkgen_calc_clk_params(unsigned int divider, } static void axi_clkgen_write(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int val) + unsigned int reg, unsigned int val) { writel(val, axi_clkgen->base + reg); } static void axi_clkgen_read(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int *val) + unsigned int reg, unsigned int *val) { *val = readl(axi_clkgen->base + reg); } @@ -263,7 +264,7 @@ static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen) } static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int *val) + unsigned int reg, unsigned int *val) { unsigned int reg_val; int ret; @@ -287,7 +288,8 @@ static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen, } static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int val, unsigned int mask) + unsigned int reg, unsigned int val, + unsigned int mask) { unsigned int reg_val = 0; int ret; @@ -308,8 +310,7 @@ static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen, return 0; } -static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen, - bool enable) +static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen, bool enable) { unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE; @@ -325,31 +326,31 @@ static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw) } static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen, - unsigned int reg1, unsigned int reg2, unsigned int reg3, - struct axi_clkgen_div_params *params) + unsigned int reg1, unsigned int reg2, + unsigned int reg3, + struct axi_clkgen_div_params *params) { axi_clkgen_mmcm_write(axi_clkgen, reg1, - (params->high << 6) | params->low, 0xefff); + (params->high << 6) | params->low, 0xefff); axi_clkgen_mmcm_write(axi_clkgen, reg2, - (params->frac << 12) | (params->frac_en << 11) | - (params->frac_wf_r << 10) | (params->edge << 7) | - (params->nocount << 6), 0x7fff); + (params->frac << 12) | (params->frac_en << 11) | + (params->frac_wf_r << 10) | (params->edge << 7) | + (params->nocount << 6), 0x7fff); if (reg3 != 0) { axi_clkgen_mmcm_write(axi_clkgen, reg3, - (params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00); + (params->frac_phase << 11) | (params->frac_wf_f << 10), + 0x3c00); } } -static int axi_clkgen_set_rate(struct clk_hw *clk_hw, - unsigned long rate, unsigned long parent_rate) +static int axi_clkgen_set_rate(struct clk_hw *clk_hw, unsigned long rate, + unsigned long parent_rate) { struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); const struct axi_clkgen_limits *limits = &axi_clkgen->limits; unsigned int d, m, dout; struct axi_clkgen_div_params params; - uint32_t power = 0; - uint32_t filter; - uint32_t lock; + u32 power = 0, filter, lock; if (parent_rate == 0 || rate == 0) return -EINVAL; @@ -369,22 +370,22 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw, axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, ¶ms); axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2, - MMCM_REG_CLKOUT5_2, ¶ms); + MMCM_REG_CLKOUT5_2, ¶ms); axi_clkgen_calc_clk_params(d, 0, ¶ms); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV, - (params.edge << 13) | (params.nocount << 12) | - (params.high << 6) | params.low, 0x3fff); + (params.edge << 13) | (params.nocount << 12) | + (params.high << 6) | params.low, 0x3fff); axi_clkgen_calc_clk_params(m >> 3, m & 0x7, ¶ms); axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2, - MMCM_REG_CLKOUT6_2, ¶ms); + MMCM_REG_CLKOUT6_2, ¶ms); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2, - (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff); + (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3, - (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff); + (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900); @@ -413,7 +414,7 @@ static int axi_clkgen_determine_rate(struct clk_hw *hw, } static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen, - unsigned int reg1, unsigned int reg2) + unsigned int reg1, unsigned int reg2) { unsigned int val1, val2; unsigned int div; @@ -440,7 +441,7 @@ static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen, } static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw, - unsigned long parent_rate) + unsigned long parent_rate) { struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); unsigned int d, m, dout; @@ -448,9 +449,9 @@ static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw, unsigned int val; dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1, - MMCM_REG_CLKOUT0_2); + MMCM_REG_CLKOUT0_2); m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1, - MMCM_REG_CLK_FB2); + MMCM_REG_CLK_FB2); axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val); if (val & MMCM_CLK_DIV_NOCOUNT) @@ -623,7 +624,7 @@ static int axi_clkgen_probe(struct platform_device *pdev) clk_name = pdev->dev.of_node->name; of_property_read_string(pdev->dev.of_node, "clock-output-names", - &clk_name); + &clk_name); init.name = clk_name; init.ops = &axi_clkgen_ops;