From patchwork Fri May 16 13:32:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 890851 Received: from riemann.telenet-ops.be (riemann.telenet-ops.be [195.130.137.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F12FD78F5E for ; Fri, 16 May 2025 13:32:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.137.80 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402365; cv=none; b=K8XfZ/UwHL/1QucHKg66PGs48c8iO4MHC4Nz+McMMiWeWJSy4WYD6vfUG/Xp/sZVVA3fjZTroC/o9M/9USTgWgVQbI1ufpkxeeEWzMdFZxMUCXKs883P6LPsO53tr/rRmFPBbpUlSHRMGhhqQTxnUEOWrvUUxlx9+5eIRllzTEE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402365; c=relaxed/simple; bh=mvpjcX/5a0oFb846ghe+MQ7JRUNpQqkMZ0y8uI1l3Rc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bcwwvMaiyirT+Kj9+lP/Pj9PFkw4ohv0wuSU5XefVy6ciYuuxYQPL9YqdpvCzNR7KQrOD0IbIECfH+tK7HA2Tv4uSPFA0GcFNA/JxeVzzekBfyQkNXKiH3cNybH7sW0raGKlxPY+18pf/8bl8nqH9PujOojwDGqOt6YXrsVa/MM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.137.80 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from albert.telenet-ops.be (albert.telenet-ops.be [IPv6:2a02:1800:110:4::f00:1a]) by riemann.telenet-ops.be (Postfix) with ESMTPS id 4ZzSgP3wVNz4xBlh for ; Fri, 16 May 2025 15:32:33 +0200 (CEST) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:b0d6:ccd4:58dc:70fd]) by albert.telenet-ops.be with cmsmtp id ppYX2E00B3S8nz406pYXww; Fri, 16 May 2025 15:32:33 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1uFvAi-000000020iV-11f3; Fri, 16 May 2025 15:32:31 +0200 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1uFvAt-0000000152L-2erg; Fri, 16 May 2025 15:32:31 +0200 From: Geert Uytterhoeven To: Mark Brown , Kuninori Morimoto , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Koji Matsuoka , Wolfram Sang Cc: linux-spi@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 05/22] spi: sh-msiof: Use bool for boolean flags Date: Fri, 16 May 2025 15:32:08 +0200 Message-ID: <35cd51bdfb3c810911a5be757e0ce5bb29dcc755.1747401908.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use bools instead of integers for boolean flags, which allows us to remove the "!!" idiom from several expressions. Signed-off-by: Geert Uytterhoeven --- v2: - No changes. --- drivers/spi/spi-sh-msiof.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 367622985fea2a04..11ef5c0a498d7c1f 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -348,11 +348,11 @@ static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p) } static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss, - u32 cpol, u32 cpha, - u32 tx_hi_z, u32 lsb_first, u32 cs_high) + bool cpol, bool cpha, bool tx_hi_z, + bool lsb_first, bool cs_high) { + bool edge; u32 tmp; - int edge; /* * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG @@ -587,7 +587,8 @@ static int sh_msiof_prepare_message(struct spi_controller *ctlr, { struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr); const struct spi_device *spi = msg->spi; - u32 ss, cs_high; + bool cs_high; + u32 ss; /* Configure pins before asserting CS */ if (spi_get_csgpiod(spi, 0)) { @@ -595,12 +596,11 @@ static int sh_msiof_prepare_message(struct spi_controller *ctlr, cs_high = p->native_cs_high; } else { ss = spi_get_chipselect(spi, 0); - cs_high = !!(spi->mode & SPI_CS_HIGH); + cs_high = spi->mode & SPI_CS_HIGH; } - sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL), - !!(spi->mode & SPI_CPHA), - !!(spi->mode & SPI_3WIRE), - !!(spi->mode & SPI_LSB_FIRST), cs_high); + sh_msiof_spi_set_pin_regs(p, ss, spi->mode & SPI_CPOL, + spi->mode & SPI_CPHA, spi->mode & SPI_3WIRE, + spi->mode & SPI_LSB_FIRST, cs_high); return 0; } From patchwork Fri May 16 13:32:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 890846 Received: from xavier.telenet-ops.be (xavier.telenet-ops.be [195.130.132.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0249D824A3 for ; Fri, 16 May 2025 13:32:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402368; cv=none; b=qZH0zOUZzmHR2rpRYrUehik2LHkEXqbZ5baBJ/AHq/YSi+5MQTm8/O6oJrbBvu9DZ3wvHhbHVJXSlXbfzquG4IASRUdJ7fBdIt98QTKqRSB3yUW3Q8bDnJ6FGy8HKuDAhjUbhjodNvreKn93f4PrhIqQ5Km7H/Nc06bI7+1KLxs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402368; c=relaxed/simple; bh=sl8eYgz9s0IQIIJJMg+RvgU0Wqv5wzmfjFIixU3FWao=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=S948qCbSe6EL4oxBGZTglEeUwERnakMASiF+NWVXJ+xURBB3UVavggE30mjpCk+SO9+bDlEcHxMr7WfOlzamIhFVcibPMe/wX49ylSk2aDaqzGIGetqtnTn8Sw63ZzovmZGCoJ4lUGU6Sqwf9QVGNVlDbEXWWcl0YtKYGCk4py8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.132.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:b0d6:ccd4:58dc:70fd]) by xavier.telenet-ops.be with cmsmtp id ppYX2E00G3S8nz401pYXap; Fri, 16 May 2025 15:32:33 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1uFvAi-000000020ia-18Mp; Fri, 16 May 2025 15:32:31 +0200 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1uFvAt-0000000152R-2mIN; Fri, 16 May 2025 15:32:31 +0200 From: Geert Uytterhoeven To: Mark Brown , Kuninori Morimoto , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Koji Matsuoka , Wolfram Sang Cc: linux-spi@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 06/22] spi: sh-msiof: Make words/bits unsigned in sh_msiof_spi_txrx_once() Date: Fri, 16 May 2025 15:32:09 +0200 Message-ID: <30eff1052642a4bcb0f1bc4bed7aae25d355a7dc.1747401908.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Make the words and bits parameters of sh_msiof_spi_txrx_once() unsigned, as that matches what is passed by the caller. This allows us to replace min_t() by the safer min(). Signed-off-by: Geert Uytterhoeven --- v2: - No changes. --- drivers/spi/spi-sh-msiof.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 11ef5c0a498d7c1f..fdb13dbc175249c4 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -677,16 +677,16 @@ static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int), const void *tx_buf, void *rx_buf, - int words, int bits) + unsigned int words, unsigned int bits) { int fifo_shift; int ret; /* limit maximum word transfer to rx/tx fifo size */ if (tx_buf) - words = min_t(int, words, p->tx_fifo_size); + words = min(words, p->tx_fifo_size); if (rx_buf) - words = min_t(int, words, p->rx_fifo_size); + words = min(words, p->rx_fifo_size); /* the fifo contents need shifting */ fifo_shift = 32 - bits; From patchwork Fri May 16 13:32:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 890844 Received: from weierstrass.telenet-ops.be (weierstrass.telenet-ops.be [195.130.137.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1C6C288B1 for ; Fri, 16 May 2025 13:32:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.137.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402368; cv=none; b=nN8Lwfg0fawPwAPhFox+PVYELl/8D9jsMK6PwTA7Ug3apGwFvAqL/xpu45fGU06mKAzG2IOuvL93QtpghA0D4IdSOu1Nnotfu0A31h7vizbzKoy8t0PYO6IjZRWkU9/Mt/ymFiL82at+jalkKwkFklDWYO6bu11PGqN9ZviY18c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402368; c=relaxed/simple; bh=NR9rZ3I3bj8QVK3gQZOn4ao8ltgkGFtn5GDgRLDfGx4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=m1o/irm85m++2+wWJw0mLT5bP3rn8FK3DwnGLcMwTbMtdENHwsIMAXaIjt5vWxI0yvJIOGclslEcY0DKE4k6Sk0DJvwLz1po4vJfxPYzX0GTNBidT8aRrhV+/aOUSgYDoLufyWimhF8ZCtkfbBojsgr+dq+6DTIuWrihR9AHAZI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.137.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from andre.telenet-ops.be (andre.telenet-ops.be [IPv6:2a02:1800:120:4::f00:15]) by weierstrass.telenet-ops.be (Postfix) with ESMTPS id 4ZzSgX4DW5z4x7nf for ; Fri, 16 May 2025 15:32:40 +0200 (CEST) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:b0d6:ccd4:58dc:70fd]) by andre.telenet-ops.be with cmsmtp id ppYX2E00E3S8nz401pYXf1; Fri, 16 May 2025 15:32:33 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1uFvAi-000000020ip-1TdN; Fri, 16 May 2025 15:32:31 +0200 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1uFvAt-0000000152g-37fM; Fri, 16 May 2025 15:32:31 +0200 From: Geert Uytterhoeven To: Mark Brown , Kuninori Morimoto , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Koji Matsuoka , Wolfram Sang Cc: linux-spi@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 09/22] spi: sh-msiof: SITMDR2 and SIRMDR2 bitfield conversion Date: Fri, 16 May 2025 15:32:12 +0200 Message-ID: <135b92d010a71e2c224feab3a5792724b4e60ff1.1747401908.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Convert MSIOF Transmit and Receive Mode Register 2 field accesses to use the FIELD_PREP() bitfield access macro. This gets rid of explicit shifts and custom field preparation macros. Signed-off-by: Geert Uytterhoeven --- v2: - No changes. --- drivers/spi/spi-sh-msiof.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index fb83b049690e0207..51a9e89364756af0 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -100,8 +100,8 @@ struct sh_msiof_spi_priv { /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */ /* SITMDR2 and SIRMDR2 */ -#define SIMDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ -#define SIMDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ +#define SIMDR2_BITLEN1 GENMASK(28, 24) /* Data Size (8-32 bits) */ +#define SIMDR2_WDLEN1 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */ #define SIMDR2_GRPMASK1 BIT(0) /* Group Output Mask 1 (SH, A1) */ /* SITSCR and SIRSCR */ @@ -397,7 +397,8 @@ static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, const void *tx_buf, void *rx_buf, u32 bits, u32 words) { - u32 dr2 = SIMDR2_BITLEN1(bits) | SIMDR2_WDLEN1(words); + u32 dr2 = FIELD_PREP(SIMDR2_BITLEN1, bits - 1) | + FIELD_PREP(SIMDR2_WDLEN1, words - 1); if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX)) sh_msiof_write(p, SITMDR2, dr2); @@ -931,6 +932,7 @@ static int sh_msiof_transfer_one(struct spi_controller *ctlr, struct spi_transfer *t) { struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr); + unsigned int max_wdlen = FIELD_MAX(SIMDR2_WDLEN1) + 1; void (*copy32)(u32 *, const u32 *, unsigned int); void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, unsigned int, unsigned int); @@ -940,7 +942,6 @@ static int sh_msiof_transfer_one(struct spi_controller *ctlr, void *rx_buf = t->rx_buf; unsigned int len = t->len; unsigned int bits = t->bits_per_word; - unsigned int max_wdlen = 256; unsigned int bytes_per_word; unsigned int words; int n; From patchwork Fri May 16 13:32:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 890845 Received: from albert.telenet-ops.be (albert.telenet-ops.be [195.130.137.90]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC80672619 for ; Fri, 16 May 2025 13:32:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.137.90 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402368; cv=none; b=ZO3GKa8nRlshdsmOsBNoG39iVPQ/3r5I8LdMTRlpEzhVF0uUSjHQbgUNhOBVyKeQ1YhqjSYUpGuGctDUOul9W1ddXWSpOAO/NnUm1khYJacxfyWAnrrdvEle/GgRziKYs9ecAH/xP/NlfrJP6UmBe/QqwradDP0qRoy2muv5abs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402368; c=relaxed/simple; bh=OCAbSjmSLPBTKg4S/+30tDY7Ef6+bvyxjGLe725Pq9Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aA6PEF8dgRD4x0wTkKvDakDVLa5mcAoKUouf/Ltz2LPIavr/G0XxhhfTR6jC746N75b9XRlhsDo/zecmch+UJioN3BDQH2jllsJRxxxbmdJrpW2jAKciSD9ag5Ro153rlOp+h43wM6/8SHdIsdQbu5hco+f+nqLVsUdqOaVFONM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.137.90 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:b0d6:ccd4:58dc:70fd]) by albert.telenet-ops.be with cmsmtp id ppYX2E00M3S8nz406pYXx2; Fri, 16 May 2025 15:32:33 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1uFvAi-000000020iu-1aZ7; Fri, 16 May 2025 15:32:31 +0200 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1uFvAt-0000000152m-3Dct; Fri, 16 May 2025 15:32:31 +0200 From: Geert Uytterhoeven To: Mark Brown , Kuninori Morimoto , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Koji Matsuoka , Wolfram Sang Cc: linux-spi@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 10/22] spi: sh-msiof: SITSCR/SIRSCR bitfield conversion Date: Fri, 16 May 2025 15:32:13 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Convert MSIOF Transmit and Receive Clock Select Register field accesses to use the FIELD_PREP() bitfield access macro. This gets rid of explicit shifts and custom field preparation macros. Signed-off-by: Geert Uytterhoeven --- v2: - No changes. --- drivers/spi/spi-sh-msiof.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 51a9e89364756af0..9bddf85dd9c7f2a1 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -105,15 +105,14 @@ struct sh_msiof_spi_priv { #define SIMDR2_GRPMASK1 BIT(0) /* Group Output Mask 1 (SH, A1) */ /* SITSCR and SIRSCR */ -#define SISCR_BRPS_MASK GENMASK(12, 8) /* Prescaler Setting (1-32) */ -#define SISCR_BRPS(i) (((i) - 1) << 8) -#define SISCR_BRDV_MASK GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */ -#define SISCR_BRDV_DIV_2 0 -#define SISCR_BRDV_DIV_4 1 -#define SISCR_BRDV_DIV_8 2 -#define SISCR_BRDV_DIV_16 3 -#define SISCR_BRDV_DIV_32 4 -#define SISCR_BRDV_DIV_1 7 +#define SISCR_BRPS GENMASK(12, 8) /* Prescaler Setting (1-32) */ +#define SISCR_BRDV GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */ +#define SISCR_BRDV_DIV_2 0U +#define SISCR_BRDV_DIV_4 1U +#define SISCR_BRDV_DIV_8 2U +#define SISCR_BRDV_DIV_16 3U +#define SISCR_BRDV_DIV_32 4U +#define SISCR_BRDV_DIV_1 7U /* SICTR */ #define SICTR_TSCKIZ_MASK GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */ @@ -299,7 +298,8 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, t->effective_speed_hz = parent_rate / (brps << div_pow); - scr = sh_msiof_spi_div_array[div_pow] | SISCR_BRPS(brps); + scr = FIELD_PREP(SISCR_BRDV, sh_msiof_spi_div_array[div_pow]) | + FIELD_PREP(SISCR_BRPS, brps - 1); sh_msiof_write(p, SITSCR, scr); if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX)) sh_msiof_write(p, SIRSCR, scr); From patchwork Fri May 16 13:32:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 890853 Received: from baptiste.telenet-ops.be (baptiste.telenet-ops.be [195.130.132.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49B6C2E40B for ; Fri, 16 May 2025 13:32:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402358; cv=none; b=iDPRUJsdERa2c3CTVj2SpD6+jAS4jP+9lCeUTfsY98ZPf+xjyJVuQZn0FbyKpfebTY4SNs1YOwFXKDNR0B9b1iczY8sAob0OwdJn8uSXZ/mIYufBIa1nhY/YKbuKTdjYkfqV3KlPl/QyfOJgsyilDldhofZ0OmBjBcKJmTGc548= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402358; c=relaxed/simple; bh=ym1GoUTCYkN02Tub7Wp0X2XBhRpUMwaHua2LRoJKlb0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XOm2jOsKVp81uNki/KJ6jaa+G0S+fEVo/pXhUQpB3lS//5gHtSh+9hnp/VSNOBf/vbZlMm+MHNGVqLWBpGcLV4O3sxrchs0WzFFSgU2VGaMWNpk9KcFyAsRef6/3JEW4Kv8/WoeD0YgrvVN1RwUP8MaS6y0U9KpzysAsBVR1Tb4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.132.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:b0d6:ccd4:58dc:70fd]) by baptiste.telenet-ops.be with cmsmtp id ppYX2E00L3S8nz401pYYVQ; Fri, 16 May 2025 15:32:33 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1uFvAi-000000020iy-1h73; Fri, 16 May 2025 15:32:31 +0200 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1uFvAt-0000000152r-3LD2; Fri, 16 May 2025 15:32:31 +0200 From: Geert Uytterhoeven To: Mark Brown , Kuninori Morimoto , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Koji Matsuoka , Wolfram Sang Cc: linux-spi@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 11/22] spi: sh-msiof: SICTR bitfield conversion Date: Fri, 16 May 2025 15:32:14 +0200 Message-ID: <4511c678c8fce5969eb50ffa7372d53396ff80ff.1747401908.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Convert MSIOF Control Register field accesses to use the FIELD_PREP() bitfield access macro. This gets rid of explicit shifts. Signed-off-by: Geert Uytterhoeven --- v2: - No changes. --- drivers/spi/spi-sh-msiof.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 9bddf85dd9c7f2a1..4f582ecc524fe5fa 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -115,18 +115,18 @@ struct sh_msiof_spi_priv { #define SISCR_BRDV_DIV_1 7U /* SICTR */ -#define SICTR_TSCKIZ_MASK GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */ +#define SICTR_TSCKIZ GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */ #define SICTR_TSCKIZ_SCK BIT(31) /* Disable SCK when TX disabled */ -#define SICTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */ -#define SICTR_RSCKIZ_MASK GENMASK(29, 28) /* Receive Clock Polarity Select */ +#define SICTR_TSCKIZ_POL BIT(30) /* Transmit Clock Polarity */ +#define SICTR_RSCKIZ GENMASK(29, 28) /* Receive Clock Polarity Select */ #define SICTR_RSCKIZ_SCK BIT(29) /* Must match CTR_TSCKIZ_SCK */ -#define SICTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */ -#define SICTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */ -#define SICTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */ -#define SICTR_TXDIZ_MASK GENMASK(23, 22) /* Pin Output When TX is Disabled */ -#define SICTR_TXDIZ_LOW (0 << 22) /* 0 */ -#define SICTR_TXDIZ_HIGH (1 << 22) /* 1 */ -#define SICTR_TXDIZ_HIZ (2 << 22) /* High-impedance */ +#define SICTR_RSCKIZ_POL BIT(28) /* Receive Clock Polarity */ +#define SICTR_TEDG BIT(27) /* Transmit Timing (1 = falling edge) */ +#define SICTR_REDG BIT(26) /* Receive Timing (1 = falling edge) */ +#define SICTR_TXDIZ GENMASK(23, 22) /* Pin Output When TX is Disabled */ +#define SICTR_TXDIZ_LOW 0U /* 0 */ +#define SICTR_TXDIZ_HIGH 1U /* 1 */ +#define SICTR_TXDIZ_HIZ 2U /* High-impedance */ #define SICTR_TSCKE BIT(15) /* Transmit Serial Clock Output Enable */ #define SICTR_TFSE BIT(14) /* Transmit Frame Sync Signal Output Enable */ #define SICTR_TXE BIT(9) /* Transmit Enable */ @@ -382,14 +382,15 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss, sh_msiof_write(p, SIRMDR1, tmp); tmp = 0; - tmp |= SICTR_TSCKIZ_SCK | cpol << SICTR_TSCKIZ_POL_SHIFT; - tmp |= SICTR_RSCKIZ_SCK | cpol << SICTR_RSCKIZ_POL_SHIFT; + tmp |= SICTR_TSCKIZ_SCK | FIELD_PREP(SICTR_TSCKIZ_POL, cpol); + tmp |= SICTR_RSCKIZ_SCK | FIELD_PREP(SICTR_RSCKIZ_POL, cpol); edge = cpol ^ !cpha; - tmp |= edge << SICTR_TEDG_SHIFT; - tmp |= edge << SICTR_REDG_SHIFT; - tmp |= tx_hi_z ? SICTR_TXDIZ_HIZ : SICTR_TXDIZ_LOW; + tmp |= FIELD_PREP(SICTR_TEDG, edge); + tmp |= FIELD_PREP(SICTR_REDG, edge); + tmp |= FIELD_PREP(SICTR_TXDIZ, + tx_hi_z ? SICTR_TXDIZ_HIZ : SICTR_TXDIZ_LOW); sh_msiof_write(p, SICTR, tmp); } From patchwork Fri May 16 13:32:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 890850 Received: from cantor.telenet-ops.be (cantor.telenet-ops.be [195.130.132.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C48124CE08 for ; Fri, 16 May 2025 13:32:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402365; cv=none; b=X2I5JVifQOjaLG1T01LBdBX4EauEI6g5Cth9dgKx5ikRWfayYA7B9iwOsfVhGz0qkywK1Y+ivXsr/HYa+tkw9OgCVaguCOR7Nvn2c0ZLmBMFEom6qvhgW+7wehEczc2SP88AISYvaEBRD6pI5i1JjpPt+07MOtSJYMLmnU6OQLY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402365; c=relaxed/simple; bh=rCkTAxu6J7MASRwBXw7XS7QLkh1LD+VQPUkTUCO6fPc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WGelKsa0r9HVja62xIkKIBxFaNKhs6jpZ0Souy7p0ApgkcjMsAE8XB7a1fag1NUguyJbYSkmaAdhq3YIt/BCe9w/J1Milgme5hMlwEpYRnriiaaKfnDfuBPjbbYyF3MY1+EWfw/t/cQhsm/kNVIHnTGMnlehs67EdP2wYbaLT/8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.132.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from baptiste.telenet-ops.be (baptiste.telenet-ops.be [IPv6:2a02:1800:120:4::f00:13]) by cantor.telenet-ops.be (Postfix) with ESMTPS id 4ZzSgP2lLdz4x8Gp for ; Fri, 16 May 2025 15:32:33 +0200 (CEST) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:b0d6:ccd4:58dc:70fd]) by baptiste.telenet-ops.be with cmsmtp id ppYY2E0013S8nz401pYYVR; Fri, 16 May 2025 15:32:33 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1uFvAi-000000020j8-214a; Fri, 16 May 2025 15:32:31 +0200 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1uFvAt-00000001531-3YC4; Fri, 16 May 2025 15:32:31 +0200 From: Geert Uytterhoeven To: Mark Brown , Kuninori Morimoto , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Koji Matsuoka , Wolfram Sang Cc: linux-spi@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 13/22] spi: sh-msiof: Correct SIMDR2_GRPMASK Date: Fri, 16 May 2025 15:32:16 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Group Output Mask is not a single bit, but a bit field, containing one bit for each of the four possible groups. Correct the definition. Note that this change has no direct impact, as the driver only uses the first group. Signed-off-by: Geert Uytterhoeven --- v2: - No changes. --- drivers/spi/spi-sh-msiof.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 812e64ea5f79ce5e..57f27040b0fc78d7 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -102,7 +102,7 @@ struct sh_msiof_spi_priv { /* SITMDR2 and SIRMDR2 */ #define SIMDR2_BITLEN1 GENMASK(28, 24) /* Data Size (8-32 bits) */ #define SIMDR2_WDLEN1 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */ -#define SIMDR2_GRPMASK1 BIT(0) /* Group Output Mask 1 (SH, A1) */ +#define SIMDR2_GRPMASK GENMASK(3, 0) /* Group Output Mask 1-4 (SH, A1) */ /* SITSCR and SIRSCR */ #define SISCR_BRPS GENMASK(12, 8) /* Prescaler Setting (1-32) */ @@ -400,7 +400,7 @@ static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX)) sh_msiof_write(p, SITMDR2, dr2); else - sh_msiof_write(p, SITMDR2, dr2 | SIMDR2_GRPMASK1); + sh_msiof_write(p, SITMDR2, dr2 | SIMDR2_GRPMASK); if (rx_buf) sh_msiof_write(p, SIRMDR2, dr2); From patchwork Fri May 16 13:32:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 890848 Received: from xavier.telenet-ops.be (xavier.telenet-ops.be [195.130.132.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00EC3823DE for ; Fri, 16 May 2025 13:32:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402367; cv=none; b=jNb6Hsm93FNFjgX+IAdUfRVShSLNcJVpJIiBj7plvkQPavXQmprZdBSgEhz9PXUxWtAhOVRle4nmZW1NDMtQSMOfblfyUA6F4tZFONQd9Jl81j9wSReE2q0gYSDCxyxBKuQeu5uYmp60MSVeqKQYo2fKcab95Co/r66e3OB8W30= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402367; c=relaxed/simple; bh=MSvhpfzfxRAatgz6Ijb2BdMLJ7N3lj9jgMikPf86PqQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ktrx8LgM9e++9qKwTkTecuwtauspSEzNCCjy/CU8AgKN65hNSiybFLy9CXpg9e620H0iwR5Arl3vJVRBfZVsdZHyGBhR6dV+IF5rp0QLtt71bOOvqGFIS1zjo2BlxrblOUkLuBhQpDcedMejmGiEeHPTYeeeafIxr9TL+o2Gv+I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.132.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:b0d6:ccd4:58dc:70fd]) by xavier.telenet-ops.be with cmsmtp id ppYY2E0023S8nz401pYYau; Fri, 16 May 2025 15:32:33 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1uFvAi-000000020j9-27CA; Fri, 16 May 2025 15:32:31 +0200 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1uFvAt-00000001536-3fWb; Fri, 16 May 2025 15:32:31 +0200 From: Geert Uytterhoeven To: Mark Brown , Kuninori Morimoto , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Koji Matsuoka , Wolfram Sang Cc: linux-spi@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 14/22] spi: sh-msiof: Add core support for dual-group transfers Date: Fri, 16 May 2025 15:32:17 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 All MSIOF variants support transferring data of multiple (2 or 4) groups. Add definitions for the register bits related to multiple groups, and enhance sh_msiof_spi_set_mode_regs() to accept a second group size. For now the second group is unused. Signed-off-by: Geert Uytterhoeven --- v2: - No changes. --- drivers/spi/spi-sh-msiof.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 57f27040b0fc78d7..ea9277ab87f66cd5 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -100,10 +100,15 @@ struct sh_msiof_spi_priv { /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */ /* SITMDR2 and SIRMDR2 */ +#define SIMDR2_GRP GENMASK(31, 30) /* Group Count */ #define SIMDR2_BITLEN1 GENMASK(28, 24) /* Data Size (8-32 bits) */ #define SIMDR2_WDLEN1 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */ #define SIMDR2_GRPMASK GENMASK(3, 0) /* Group Output Mask 1-4 (SH, A1) */ +/* SITMDR3 and SIRMDR3 */ +#define SIMDR3_BITLEN2 GENMASK(28, 24) /* Data Size (8-32 bits) */ +#define SIMDR3_WDLEN2 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */ + /* SITSCR and SIRSCR */ #define SISCR_BRPS GENMASK(12, 8) /* Prescaler Setting (1-32) */ #define SISCR_BRDV GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */ @@ -392,10 +397,11 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss, static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, const void *tx_buf, void *rx_buf, - u32 bits, u32 words) + u32 bits, u32 words1, u32 words2) { - u32 dr2 = FIELD_PREP(SIMDR2_BITLEN1, bits - 1) | - FIELD_PREP(SIMDR2_WDLEN1, words - 1); + u32 dr2 = FIELD_PREP(SIMDR2_GRP, words2 ? 1 : 0) | + FIELD_PREP(SIMDR2_BITLEN1, bits - 1) | + FIELD_PREP(SIMDR2_WDLEN1, words1 - 1); if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX)) sh_msiof_write(p, SITMDR2, dr2); @@ -404,6 +410,15 @@ static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, if (rx_buf) sh_msiof_write(p, SIRMDR2, dr2); + + if (words2) { + u32 dr3 = FIELD_PREP(SIMDR3_BITLEN2, bits - 1) | + FIELD_PREP(SIMDR3_WDLEN2, words2 - 1); + + sh_msiof_write(p, SITMDR3, dr3); + if (rx_buf) + sh_msiof_write(p, SIRMDR3, dr3); + } } static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) @@ -712,7 +727,7 @@ static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, sh_msiof_write(p, SIFCTR, 0); /* setup msiof transfer mode registers */ - sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); + sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words, 0); sh_msiof_write(p, SIIER, SIIER_TEOFE | SIIER_REOFE); /* write tx fifo */ @@ -812,7 +827,7 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx, FIELD_PREP(SIFCTR_RFWM, SIFCTR_RFWM_1)); /* setup msiof transfer mode registers (32-bit words) */ - sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4); + sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4, 0); sh_msiof_write(p, SIIER, ier_bits); From patchwork Fri May 16 13:32:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 890854 Received: from baptiste.telenet-ops.be (baptiste.telenet-ops.be [195.130.132.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4997811CAF for ; Fri, 16 May 2025 13:32:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402357; cv=none; b=JY23xuTVXnA1wkJgXld++QMkSjMi0NAjABC5WRUsEiZredfrKRlnF2OlOZLkGd0Yd//BoCsppNf9xOamJtAJ53kYVeypAE4Ev6dholQmAmmQuRqTP7YeGkMWTZ89zGqTUVgXL+o6eOT0G0sHDfkysVgq0A6bYjGwdRt2DV3Et3k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402357; c=relaxed/simple; bh=x1puk1ZFl1FwUZ/v7ztHeHybvqbpZ68TydGFBgHL1hg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=M6QoOM2a2D33gPhRrjj6S4IC1F8btP0FXIDTXBsI9Df8saGiGDAPFpGgnb4Btt+MTZSuYzCnrSO2KMToFBLaUW12EqEFSZo5ujqbGGiapVdkNT4kEzMEb8zezuZLljKaMSMTjp9p/A6zJ35myEiIFXzWTnDFL++l8kyEekJ0BVE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.132.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:b0d6:ccd4:58dc:70fd]) by baptiste.telenet-ops.be with cmsmtp id ppYY2E0063S8nz401pYYVT; Fri, 16 May 2025 15:32:33 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1uFvAi-000000020jJ-2KKJ; Fri, 16 May 2025 15:32:32 +0200 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1uFvAt-0000000153G-3ykH; Fri, 16 May 2025 15:32:31 +0200 From: Geert Uytterhoeven To: Mark Brown , Kuninori Morimoto , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Koji Matsuoka , Wolfram Sang Cc: linux-spi@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 16/22] spi: sh-msiof: Correct RX FIFO size for R-Car Gen3 Date: Fri, 16 May 2025 15:32:19 +0200 Message-ID: <6f74508ea4681aa0b7c6bf6810eab026725e75a3.1747401908.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 According to the R-Car Gen3 Hardware Manual Errata for Rev 0.55 of September 28, 2017, the MSIOF receive FIFOs on R-Car Gen3 SoCs have room for 256 words of 32 bits. Note that this change has no actual impact on the behavior of the driver, as SPI_CONTROLLER_MUST_TX is set, and transfer size is currenty limited to the minimum of the transmit and receive FIFO sizes. Signed-off-by: Geert Uytterhoeven --- v2: - No changes. --- drivers/spi/spi-sh-msiof.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 8d18a26128d600f6..8afb7c1f64cd4486 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -1108,7 +1108,7 @@ static const struct sh_msiof_chipdata rcar_gen3_data = { .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | SPI_BPW_MASK(24) | SPI_BPW_MASK(32), .tx_fifo_size = 64, - .rx_fifo_size = 64, + .rx_fifo_size = 256, .ctlr_flags = SPI_CONTROLLER_MUST_TX, .min_div_pow = 1, }; @@ -1117,7 +1117,7 @@ static const struct sh_msiof_chipdata rcar_r8a7795_data = { .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | SPI_BPW_MASK(24) | SPI_BPW_MASK(32), .tx_fifo_size = 64, - .rx_fifo_size = 64, + .rx_fifo_size = 256, .ctlr_flags = SPI_CONTROLLER_MUST_TX, .min_div_pow = 1, .flags = SH_MSIOF_FLAG_FIXED_DTDL_200, From patchwork Fri May 16 13:32:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 890847 Received: from michel.telenet-ops.be (michel.telenet-ops.be [195.130.137.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D1EE136347 for ; Fri, 16 May 2025 13:32:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.137.88 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402367; cv=none; b=Ek2QQF+dtpk9UEZF/aJNSECYVLTqhq708TZVNMkqSFBZoO1Am3j8dK2FVP0fc6yJjmev8EXY6X1EEhtzbfsRjulidcIlVfIDJSnVFNRBI7VJbLJO/AY/UFZwMtA6xdudx7PnByn8xgILNWVChTaFwKt/FMSC7h5p1MvrWgE0FfQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402367; c=relaxed/simple; bh=WoN2M38Gq0Si4MJuTnhp6KJst1ym3ogf8jEo+hK8HI0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FuDKen6rwSF4DrhNP068Flkl2DO4XpRR1ZZmcKvFs++XEHMBK34TNtr0R+nazaihiLJcCWAyDMy4pSytYOPchePIA9K9cn02xWfuWLMi7RtAPMUrnqhaovSGRzfRzkz+UGx1XKfjNecZHYo53fuNVJfHI8ASWVWdLJ7BF80QAno= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.137.88 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:b0d6:ccd4:58dc:70fd]) by michel.telenet-ops.be with cmsmtp id ppYY2E0043S8nz406pYY0a; Fri, 16 May 2025 15:32:33 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1uFvAi-000000020jS-2cy4; Fri, 16 May 2025 15:32:32 +0200 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1uFvAu-0000000153V-05gR; Fri, 16 May 2025 15:32:32 +0200 From: Geert Uytterhoeven To: Mark Brown , Kuninori Morimoto , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Koji Matsuoka , Wolfram Sang Cc: linux-spi@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 19/22] spi: sh-msiof: Double maximum DMA transfer size using two groups Date: Fri, 16 May 2025 15:32:22 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The maximum DMA transfer size is limited by the maximum values that can be written to the word count fields (WDLENx) in the Transmit and Control Data Registers (SITDR2/SIRDR2). As all MSIOF variants support transferring data of multiple (two or four) groups, the maximum size can be doubled by using two groups instead of one, thus reducing setup overhead for very large SPI transfers. Signed-off-by: Geert Uytterhoeven --- Tested on R-Car M2-W, E3, V4H, and V4M with spi-loopback-test and a logic analyzer. v2: - No changes. --- drivers/spi/spi-sh-msiof.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 2b8c143b21219521..4d9a44118e1c9d6c 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -767,10 +767,12 @@ static void sh_msiof_dma_complete(void *arg) } static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx, - void *rx, unsigned int len) + void *rx, unsigned int len, + unsigned int max_wdlen) { u32 ier_bits = 0; struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; + unsigned int words1, words2; dma_cookie_t cookie; int ret; @@ -817,7 +819,9 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx, FIELD_PREP(SIFCTR_RFWM, SIFCTR_RFWM_1)); /* setup msiof transfer mode registers (32-bit words) */ - sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4, 0); + words1 = min(len / 4, max_wdlen); + words2 = len / 4 - words1; + sh_msiof_spi_set_mode_regs(p, tx, rx, 32, words1, words2); sh_msiof_write(p, SIIER, ier_bits); @@ -969,7 +973,7 @@ static int sh_msiof_transfer_one(struct spi_controller *ctlr, * DMA supports 32-bit words only, hence pack 8-bit and 16-bit * words, with byte resp. word swapping. */ - unsigned int l = min(round_down(len, 4), max_wdlen * 4); + unsigned int l = min(round_down(len, 4), 2 * max_wdlen * 4); if (bits <= 8) { copy32 = copy_bswap32; @@ -982,7 +986,7 @@ static int sh_msiof_transfer_one(struct spi_controller *ctlr, if (tx_buf) copy32(p->tx_dma_page, tx_buf, l / 4); - ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l); + ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l, max_wdlen); if (ret == -EAGAIN) { dev_warn_once(&p->pdev->dev, "DMA not available, falling back to PIO\n"); From patchwork Fri May 16 13:32:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 890852 Received: from cantor.telenet-ops.be (cantor.telenet-ops.be [195.130.132.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C47AC2A1AA for ; Fri, 16 May 2025 13:32:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402363; cv=none; b=jZXbKmGYsJkGsaATztYrGSDWIc1vJwyQ9Qd/L9EzqPiQsRDGx/ZLvbnc+5rU9Vyno8uGjkyRAI2R2tqBuh379BuXmCsvkoDmrVZxgNWRVtb1NMxSfF/kBceCS40QTB1z52VoQZ1NYom33c8wnY3AhFDNG8g4JuZaZkIG/q1HSzw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402363; c=relaxed/simple; bh=6u9qP4p/k120mz1GOGuRUINaz60Y8hyt8cE4KpTLTuU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=scvfylXySh0ViV9TBGq+w9OeGp4zj4YqBWWEWS5uavAAzqwh+wL96S0U1pE4kG5AQ1c8ijb/Eu0Phn8KABpqMj6ecl2lykYj34WCLiIp58nPAPiqGNX35IhuKl1i0YiLTJF5YsFhef3sDqYP8RBuGMMqSgXR5K+Vw9QmYc/Z1sw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.132.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from andre.telenet-ops.be (andre.telenet-ops.be [IPv6:2a02:1800:120:4::f00:15]) by cantor.telenet-ops.be (Postfix) with ESMTPS id 4ZzSgP32B4z4x925 for ; Fri, 16 May 2025 15:32:33 +0200 (CEST) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:b0d6:ccd4:58dc:70fd]) by andre.telenet-ops.be with cmsmtp id ppYY2E0063S8nz401pYYf5; Fri, 16 May 2025 15:32:33 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1uFvAi-000000020jY-2jCs; Fri, 16 May 2025 15:32:32 +0200 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1uFvAu-0000000153a-0BbA; Fri, 16 May 2025 15:32:32 +0200 From: Geert Uytterhoeven To: Mark Brown , Kuninori Morimoto , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Koji Matsuoka , Wolfram Sang Cc: linux-spi@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 20/22] spi: sh-msiof: Document frame start sync pulse mode Date: Fri, 16 May 2025 15:32:23 +0200 Message-ID: <3d3acaab4a4125106a0655d28c09c050341c5eeb.1747401908.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Unused, but nice to have it documented. Signed-off-by: Geert Uytterhoeven --- v2: - No changes. --- drivers/spi/spi-sh-msiof.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 4d9a44118e1c9d6c..5d9d551dbd220389 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -86,6 +86,7 @@ struct sh_msiof_spi_priv { /* SITMDR1 and SIRMDR1 */ #define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */ #define SIMDR1_SYNCMD GENMASK(29, 28) /* SYNC Mode */ +#define SIMDR1_SYNCMD_PULSE 0U /* Frame start sync pulse */ #define SIMDR1_SYNCMD_SPI 2U /* Level mode/SPI */ #define SIMDR1_SYNCMD_LR 3U /* L/R mode */ #define SIMDR1_SYNCAC BIT(25) /* Sync Polarity (1 = Active-low) */ From patchwork Fri May 16 13:32:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 890849 Received: from riemann.telenet-ops.be (riemann.telenet-ops.be [195.130.137.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F27457A13A for ; Fri, 16 May 2025 13:32:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.137.80 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402367; cv=none; b=clBwIiN30DpMSYvROclH8BQXnty9sHzP26oNsuYX66MqSFNxSOjWSREDb2assGxwjb49OUoU/SDzKee6JGWX1kXA0fp+qcYoVxbCGEr0f4cwyvk5HXNMxbFBRemwxoPIMbk2sCgTdVMA1CwYEpusHvDUKJQuyo02ohhDdkDR1VA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402367; c=relaxed/simple; bh=csAJ+nI00EfIWMUAD0PA1WYCs/P+CVWjr85cz+SUGQA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DYBsCIqaZRzRMnQLb5wxj4Vq5NsK8a65KsnjsU3NBXHgsOcyjp9wgFkQzaag00GdfooFbo2VnY5jfu2376xdz46LuxZNUD5Z4vwpXwaf/5GwX2iznrBSxDRojWEKCfvMBfteHnNnHRlpgM+H5nI2S8koNEJDQpmi7MuAfFePYoE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.137.80 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from baptiste.telenet-ops.be (baptiste.telenet-ops.be [IPv6:2a02:1800:120:4::f00:13]) by riemann.telenet-ops.be (Postfix) with ESMTPS id 4ZzSgP3Xn3z4xBP2 for ; Fri, 16 May 2025 15:32:33 +0200 (CEST) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:b0d6:ccd4:58dc:70fd]) by baptiste.telenet-ops.be with cmsmtp id ppYY2E00A3S8nz401pYYVW; Fri, 16 May 2025 15:32:33 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1uFvAi-000000020jd-2r4m; Fri, 16 May 2025 15:32:32 +0200 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1uFvAu-0000000153e-0IE4; Fri, 16 May 2025 15:32:32 +0200 From: Geert Uytterhoeven To: Mark Brown , Kuninori Morimoto , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Koji Matsuoka , Wolfram Sang Cc: linux-spi@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 21/22] spi: sh-msiof: Move register definitions to Date: Fri, 16 May 2025 15:32:24 +0200 Message-ID: <066d1086973eb309006258484e9fe8138807e565.1747401908.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Move the MSIOF register and register bit definitions from the MSIOF SPI driver to the existing header file , so they can be shared with the MSIOF I2S driver. Signed-off-by: Geert Uytterhoeven --- v2: - Make include/linux/spi/sh_msiof.h self-contained, to fix a build failure of sound/soc/renesas/rcar/msiof.c on some architectures after the next patch. --- drivers/spi/spi-sh-msiof.c | 124 ---------------------------------- include/linux/spi/sh_msiof.h | 125 +++++++++++++++++++++++++++++++++++ 2 files changed, 125 insertions(+), 124 deletions(-) diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 5d9d551dbd220389..94a867967e024446 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -7,7 +7,6 @@ * Copyright (C) 2014-2017 Glider bvba */ -#include #include #include #include @@ -64,129 +63,6 @@ struct sh_msiof_spi_priv { #define MAX_SS 3 /* Maximum number of native chip selects */ -#define SITMDR1 0x00 /* Transmit Mode Register 1 */ -#define SITMDR2 0x04 /* Transmit Mode Register 2 */ -#define SITMDR3 0x08 /* Transmit Mode Register 3 */ -#define SIRMDR1 0x10 /* Receive Mode Register 1 */ -#define SIRMDR2 0x14 /* Receive Mode Register 2 */ -#define SIRMDR3 0x18 /* Receive Mode Register 3 */ -#define SITSCR 0x20 /* Transmit Clock Select Register */ -#define SIRSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ -#define SICTR 0x28 /* Control Register */ -#define SIFCTR 0x30 /* FIFO Control Register */ -#define SISTR 0x40 /* Status Register */ -#define SIIER 0x44 /* Interrupt Enable Register */ -#define SITDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ -#define SITDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ -#define SITFDR 0x50 /* Transmit FIFO Data Register */ -#define SIRDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ -#define SIRDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ -#define SIRFDR 0x60 /* Receive FIFO Data Register */ - -/* SITMDR1 and SIRMDR1 */ -#define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */ -#define SIMDR1_SYNCMD GENMASK(29, 28) /* SYNC Mode */ -#define SIMDR1_SYNCMD_PULSE 0U /* Frame start sync pulse */ -#define SIMDR1_SYNCMD_SPI 2U /* Level mode/SPI */ -#define SIMDR1_SYNCMD_LR 3U /* L/R mode */ -#define SIMDR1_SYNCAC BIT(25) /* Sync Polarity (1 = Active-low) */ -#define SIMDR1_BITLSB BIT(24) /* MSB/LSB First (1 = LSB first) */ -#define SIMDR1_DTDL GENMASK(22, 20) /* Data Pin Bit Delay for MSIOF_SYNC */ -#define SIMDR1_SYNCDL GENMASK(18, 16) /* Frame Sync Signal Timing Delay */ -#define SIMDR1_FLD GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */ -#define SIMDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */ -/* SITMDR1 */ -#define SITMDR1_PCON BIT(30) /* Transfer Signal Connection */ -#define SITMDR1_SYNCCH GENMASK(27, 26) /* Sync Signal Channel Select */ - /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */ - -/* SITMDR2 and SIRMDR2 */ -#define SIMDR2_GRP GENMASK(31, 30) /* Group Count */ -#define SIMDR2_BITLEN1 GENMASK(28, 24) /* Data Size (8-32 bits) */ -#define SIMDR2_WDLEN1 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */ -#define SIMDR2_GRPMASK GENMASK(3, 0) /* Group Output Mask 1-4 (SH, A1) */ - -/* SITMDR3 and SIRMDR3 */ -#define SIMDR3_BITLEN2 GENMASK(28, 24) /* Data Size (8-32 bits) */ -#define SIMDR3_WDLEN2 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */ - -/* SITSCR and SIRSCR */ -#define SISCR_BRPS GENMASK(12, 8) /* Prescaler Setting (1-32) */ -#define SISCR_BRDV GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */ - -/* SICTR */ -#define SICTR_TSCKIZ GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */ -#define SICTR_TSCKIZ_SCK BIT(31) /* Disable SCK when TX disabled */ -#define SICTR_TSCKIZ_POL BIT(30) /* Transmit Clock Polarity */ -#define SICTR_RSCKIZ GENMASK(29, 28) /* Receive Clock Polarity Select */ -#define SICTR_RSCKIZ_SCK BIT(29) /* Must match CTR_TSCKIZ_SCK */ -#define SICTR_RSCKIZ_POL BIT(28) /* Receive Clock Polarity */ -#define SICTR_TEDG BIT(27) /* Transmit Timing (1 = falling edge) */ -#define SICTR_REDG BIT(26) /* Receive Timing (1 = falling edge) */ -#define SICTR_TXDIZ GENMASK(23, 22) /* Pin Output When TX is Disabled */ -#define SICTR_TXDIZ_LOW 0U /* 0 */ -#define SICTR_TXDIZ_HIGH 1U /* 1 */ -#define SICTR_TXDIZ_HIZ 2U /* High-impedance */ -#define SICTR_TSCKE BIT(15) /* Transmit Serial Clock Output Enable */ -#define SICTR_TFSE BIT(14) /* Transmit Frame Sync Signal Output Enable */ -#define SICTR_TXE BIT(9) /* Transmit Enable */ -#define SICTR_RXE BIT(8) /* Receive Enable */ -#define SICTR_TXRST BIT(1) /* Transmit Reset */ -#define SICTR_RXRST BIT(0) /* Receive Reset */ - -/* SIFCTR */ -#define SIFCTR_TFWM GENMASK(31, 29) /* Transmit FIFO Watermark */ -#define SIFCTR_TFWM_64 0U /* Transfer Request when 64 empty stages */ -#define SIFCTR_TFWM_32 1U /* Transfer Request when 32 empty stages */ -#define SIFCTR_TFWM_24 2U /* Transfer Request when 24 empty stages */ -#define SIFCTR_TFWM_16 3U /* Transfer Request when 16 empty stages */ -#define SIFCTR_TFWM_12 4U /* Transfer Request when 12 empty stages */ -#define SIFCTR_TFWM_8 5U /* Transfer Request when 8 empty stages */ -#define SIFCTR_TFWM_4 6U /* Transfer Request when 4 empty stages */ -#define SIFCTR_TFWM_1 7U /* Transfer Request when 1 empty stage */ -#define SIFCTR_TFUA GENMASK(28, 20) /* Transmit FIFO Usable Area */ -#define SIFCTR_RFWM GENMASK(15, 13) /* Receive FIFO Watermark */ -#define SIFCTR_RFWM_1 0U /* Transfer Request when 1 valid stages */ -#define SIFCTR_RFWM_4 1U /* Transfer Request when 4 valid stages */ -#define SIFCTR_RFWM_8 2U /* Transfer Request when 8 valid stages */ -#define SIFCTR_RFWM_16 3U /* Transfer Request when 16 valid stages */ -#define SIFCTR_RFWM_32 4U /* Transfer Request when 32 valid stages */ -#define SIFCTR_RFWM_64 5U /* Transfer Request when 64 valid stages */ -#define SIFCTR_RFWM_128 6U /* Transfer Request when 128 valid stages */ -#define SIFCTR_RFWM_256 7U /* Transfer Request when 256 valid stages */ -#define SIFCTR_RFUA GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */ - -/* SISTR */ -#define SISTR_TFEMP BIT(29) /* Transmit FIFO Empty */ -#define SISTR_TDREQ BIT(28) /* Transmit Data Transfer Request */ -#define SISTR_TEOF BIT(23) /* Frame Transmission End */ -#define SISTR_TFSERR BIT(21) /* Transmit Frame Synchronization Error */ -#define SISTR_TFOVF BIT(20) /* Transmit FIFO Overflow */ -#define SISTR_TFUDF BIT(19) /* Transmit FIFO Underflow */ -#define SISTR_RFFUL BIT(13) /* Receive FIFO Full */ -#define SISTR_RDREQ BIT(12) /* Receive Data Transfer Request */ -#define SISTR_REOF BIT(7) /* Frame Reception End */ -#define SISTR_RFSERR BIT(5) /* Receive Frame Synchronization Error */ -#define SISTR_RFUDF BIT(4) /* Receive FIFO Underflow */ -#define SISTR_RFOVF BIT(3) /* Receive FIFO Overflow */ - -/* SIIER */ -#define SIIER_TDMAE BIT(31) /* Transmit Data DMA Transfer Req. Enable */ -#define SIIER_TFEMPE BIT(29) /* Transmit FIFO Empty Enable */ -#define SIIER_TDREQE BIT(28) /* Transmit Data Transfer Request Enable */ -#define SIIER_TEOFE BIT(23) /* Frame Transmission End Enable */ -#define SIIER_TFSERRE BIT(21) /* Transmit Frame Sync Error Enable */ -#define SIIER_TFOVFE BIT(20) /* Transmit FIFO Overflow Enable */ -#define SIIER_TFUDFE BIT(19) /* Transmit FIFO Underflow Enable */ -#define SIIER_RDMAE BIT(15) /* Receive Data DMA Transfer Req. Enable */ -#define SIIER_RFFULE BIT(13) /* Receive FIFO Full Enable */ -#define SIIER_RDREQE BIT(12) /* Receive Data Transfer Request Enable */ -#define SIIER_REOFE BIT(7) /* Frame Reception End Enable */ -#define SIIER_RFSERRE BIT(5) /* Receive Frame Sync Error Enable */ -#define SIIER_RFUDFE BIT(4) /* Receive FIFO Underflow Enable */ -#define SIIER_RFOVFE BIT(3) /* Receive FIFO Overflow Enable */ - - static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) { switch (reg_offs) { diff --git a/include/linux/spi/sh_msiof.h b/include/linux/spi/sh_msiof.h index f950d280461b917d..9fbef3fd40567d04 100644 --- a/include/linux/spi/sh_msiof.h +++ b/include/linux/spi/sh_msiof.h @@ -2,6 +2,131 @@ #ifndef __SPI_SH_MSIOF_H__ #define __SPI_SH_MSIOF_H__ +#include +#include + +#define SITMDR1 0x00 /* Transmit Mode Register 1 */ +#define SITMDR2 0x04 /* Transmit Mode Register 2 */ +#define SITMDR3 0x08 /* Transmit Mode Register 3 */ +#define SIRMDR1 0x10 /* Receive Mode Register 1 */ +#define SIRMDR2 0x14 /* Receive Mode Register 2 */ +#define SIRMDR3 0x18 /* Receive Mode Register 3 */ +#define SITSCR 0x20 /* Transmit Clock Select Register */ +#define SIRSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ +#define SICTR 0x28 /* Control Register */ +#define SIFCTR 0x30 /* FIFO Control Register */ +#define SISTR 0x40 /* Status Register */ +#define SIIER 0x44 /* Interrupt Enable Register */ +#define SITDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ +#define SITDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ +#define SITFDR 0x50 /* Transmit FIFO Data Register */ +#define SIRDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ +#define SIRDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ +#define SIRFDR 0x60 /* Receive FIFO Data Register */ + +/* SITMDR1 and SIRMDR1 */ +#define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */ +#define SIMDR1_SYNCMD GENMASK(29, 28) /* SYNC Mode */ +#define SIMDR1_SYNCMD_PULSE 0U /* Frame start sync pulse */ +#define SIMDR1_SYNCMD_SPI 2U /* Level mode/SPI */ +#define SIMDR1_SYNCMD_LR 3U /* L/R mode */ +#define SIMDR1_SYNCAC BIT(25) /* Sync Polarity (1 = Active-low) */ +#define SIMDR1_BITLSB BIT(24) /* MSB/LSB First (1 = LSB first) */ +#define SIMDR1_DTDL GENMASK(22, 20) /* Data Pin Bit Delay for MSIOF_SYNC */ +#define SIMDR1_SYNCDL GENMASK(18, 16) /* Frame Sync Signal Timing Delay */ +#define SIMDR1_FLD GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */ +#define SIMDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */ +/* SITMDR1 */ +#define SITMDR1_PCON BIT(30) /* Transfer Signal Connection */ +#define SITMDR1_SYNCCH GENMASK(27, 26) /* Sync Signal Channel Select */ + /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */ + +/* SITMDR2 and SIRMDR2 */ +#define SIMDR2_GRP GENMASK(31, 30) /* Group Count */ +#define SIMDR2_BITLEN1 GENMASK(28, 24) /* Data Size (8-32 bits) */ +#define SIMDR2_WDLEN1 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */ +#define SIMDR2_GRPMASK GENMASK(3, 0) /* Group Output Mask 1-4 (SH, A1) */ + +/* SITMDR3 and SIRMDR3 */ +#define SIMDR3_BITLEN2 GENMASK(28, 24) /* Data Size (8-32 bits) */ +#define SIMDR3_WDLEN2 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */ + +/* SITSCR and SIRSCR */ +#define SISCR_BRPS GENMASK(12, 8) /* Prescaler Setting (1-32) */ +#define SISCR_BRDV GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */ + +/* SICTR */ +#define SICTR_TSCKIZ GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */ +#define SICTR_TSCKIZ_SCK BIT(31) /* Disable SCK when TX disabled */ +#define SICTR_TSCKIZ_POL BIT(30) /* Transmit Clock Polarity */ +#define SICTR_RSCKIZ GENMASK(29, 28) /* Receive Clock Polarity Select */ +#define SICTR_RSCKIZ_SCK BIT(29) /* Must match CTR_TSCKIZ_SCK */ +#define SICTR_RSCKIZ_POL BIT(28) /* Receive Clock Polarity */ +#define SICTR_TEDG BIT(27) /* Transmit Timing (1 = falling edge) */ +#define SICTR_REDG BIT(26) /* Receive Timing (1 = falling edge) */ +#define SICTR_TXDIZ GENMASK(23, 22) /* Pin Output When TX is Disabled */ +#define SICTR_TXDIZ_LOW 0U /* 0 */ +#define SICTR_TXDIZ_HIGH 1U /* 1 */ +#define SICTR_TXDIZ_HIZ 2U /* High-impedance */ +#define SICTR_TSCKE BIT(15) /* Transmit Serial Clock Output Enable */ +#define SICTR_TFSE BIT(14) /* Transmit Frame Sync Signal Output Enable */ +#define SICTR_TXE BIT(9) /* Transmit Enable */ +#define SICTR_RXE BIT(8) /* Receive Enable */ +#define SICTR_TXRST BIT(1) /* Transmit Reset */ +#define SICTR_RXRST BIT(0) /* Receive Reset */ + +/* SIFCTR */ +#define SIFCTR_TFWM GENMASK(31, 29) /* Transmit FIFO Watermark */ +#define SIFCTR_TFWM_64 0U /* Transfer Request when 64 empty stages */ +#define SIFCTR_TFWM_32 1U /* Transfer Request when 32 empty stages */ +#define SIFCTR_TFWM_24 2U /* Transfer Request when 24 empty stages */ +#define SIFCTR_TFWM_16 3U /* Transfer Request when 16 empty stages */ +#define SIFCTR_TFWM_12 4U /* Transfer Request when 12 empty stages */ +#define SIFCTR_TFWM_8 5U /* Transfer Request when 8 empty stages */ +#define SIFCTR_TFWM_4 6U /* Transfer Request when 4 empty stages */ +#define SIFCTR_TFWM_1 7U /* Transfer Request when 1 empty stage */ +#define SIFCTR_TFUA GENMASK(28, 20) /* Transmit FIFO Usable Area */ +#define SIFCTR_RFWM GENMASK(15, 13) /* Receive FIFO Watermark */ +#define SIFCTR_RFWM_1 0U /* Transfer Request when 1 valid stages */ +#define SIFCTR_RFWM_4 1U /* Transfer Request when 4 valid stages */ +#define SIFCTR_RFWM_8 2U /* Transfer Request when 8 valid stages */ +#define SIFCTR_RFWM_16 3U /* Transfer Request when 16 valid stages */ +#define SIFCTR_RFWM_32 4U /* Transfer Request when 32 valid stages */ +#define SIFCTR_RFWM_64 5U /* Transfer Request when 64 valid stages */ +#define SIFCTR_RFWM_128 6U /* Transfer Request when 128 valid stages */ +#define SIFCTR_RFWM_256 7U /* Transfer Request when 256 valid stages */ +#define SIFCTR_RFUA GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */ + +/* SISTR */ +#define SISTR_TFEMP BIT(29) /* Transmit FIFO Empty */ +#define SISTR_TDREQ BIT(28) /* Transmit Data Transfer Request */ +#define SISTR_TEOF BIT(23) /* Frame Transmission End */ +#define SISTR_TFSERR BIT(21) /* Transmit Frame Synchronization Error */ +#define SISTR_TFOVF BIT(20) /* Transmit FIFO Overflow */ +#define SISTR_TFUDF BIT(19) /* Transmit FIFO Underflow */ +#define SISTR_RFFUL BIT(13) /* Receive FIFO Full */ +#define SISTR_RDREQ BIT(12) /* Receive Data Transfer Request */ +#define SISTR_REOF BIT(7) /* Frame Reception End */ +#define SISTR_RFSERR BIT(5) /* Receive Frame Synchronization Error */ +#define SISTR_RFUDF BIT(4) /* Receive FIFO Underflow */ +#define SISTR_RFOVF BIT(3) /* Receive FIFO Overflow */ + +/* SIIER */ +#define SIIER_TDMAE BIT(31) /* Transmit Data DMA Transfer Req. Enable */ +#define SIIER_TFEMPE BIT(29) /* Transmit FIFO Empty Enable */ +#define SIIER_TDREQE BIT(28) /* Transmit Data Transfer Request Enable */ +#define SIIER_TEOFE BIT(23) /* Frame Transmission End Enable */ +#define SIIER_TFSERRE BIT(21) /* Transmit Frame Sync Error Enable */ +#define SIIER_TFOVFE BIT(20) /* Transmit FIFO Overflow Enable */ +#define SIIER_TFUDFE BIT(19) /* Transmit FIFO Underflow Enable */ +#define SIIER_RDMAE BIT(15) /* Receive Data DMA Transfer Req. Enable */ +#define SIIER_RFFULE BIT(13) /* Receive FIFO Full Enable */ +#define SIIER_RDREQE BIT(12) /* Receive Data Transfer Request Enable */ +#define SIIER_REOFE BIT(7) /* Frame Reception End Enable */ +#define SIIER_RFSERRE BIT(5) /* Receive Frame Sync Error Enable */ +#define SIIER_RFUDFE BIT(4) /* Receive FIFO Underflow Enable */ +#define SIIER_RFOVFE BIT(3) /* Receive FIFO Overflow Enable */ + enum { MSIOF_SPI_HOST, MSIOF_SPI_TARGET, From patchwork Fri May 16 13:32:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 890843 Received: from cantor.telenet-ops.be (cantor.telenet-ops.be [195.130.132.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E97022CCDB for ; Fri, 16 May 2025 13:32:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402369; cv=none; b=TP51gczZIwpj4py4F/qLfkUIlvxNnEjDTWAD29YOPyCnZORJkde89v8AmYLoEnFiVZj+0n04KRoO6u5dYD1mKFy+Dbx0Aazve8ByIq0SA5yvZOZdsOSKC3u+fUBaisjKD5q47WEFeQ7gTHGo77uHSuB58V92eFEylIWmOmpieuM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747402369; c=relaxed/simple; bh=Abw15zzJtQxJtQmksAX5S4pVBE/v9LqvizbIKz9pUGQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aChOiUsH8EHeZakVAytC4LHCkk+P5nB4dg2BrBcKRcd/MWBoYagujvJaKEpuVQ2BjGZSlB2NAd7MFFdTSIz0oSqZF3yjvjkqP0KxmD4CetD6p0hazY+c5xRk8xesDlCNbpTh8X4cJg0rhwKVcHOBS9aG3oLEXw/8A1Nm1YIqDeU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.132.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from albert.telenet-ops.be (albert.telenet-ops.be [IPv6:2a02:1800:110:4::f00:1a]) by cantor.telenet-ops.be (Postfix) with ESMTPS id 4ZzSgP4cRPz4xBbY for ; Fri, 16 May 2025 15:32:33 +0200 (CEST) Received: from ramsan.of.borg ([84.195.187.55]) by albert.telenet-ops.be with cmsmtp id ppYY2E0061C8whw06pYYx7; Fri, 16 May 2025 15:32:33 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1uFvAi-000000020jf-2xVV; Fri, 16 May 2025 15:32:32 +0200 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1uFvAu-0000000153k-0Pb0; Fri, 16 May 2025 15:32:32 +0200 From: Geert Uytterhoeven To: Mark Brown , Kuninori Morimoto , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Koji Matsuoka , Wolfram Sang Cc: linux-spi@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 22/22] ASoC: renesas: msiof: Convert to Date: Fri, 16 May 2025 15:32:25 +0200 Message-ID: <754ed54057e54effd06143e71d6cd305c3334eca.1747401908.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Convert the MSIOF I2S driver to reuse the MSIOF register and register bit definitions in the header file shared by the MSIOF SPI driver. Signed-off-by: Geert Uytterhoeven Tested-by: Kuninori Morimoto --- Compile-tested and asm-inspected only due to lack of local sound hardware. v2: - Add Tested-by. --- sound/soc/renesas/rcar/msiof.c | 94 ++++++++++------------------------ 1 file changed, 28 insertions(+), 66 deletions(-) diff --git a/sound/soc/renesas/rcar/msiof.c b/sound/soc/renesas/rcar/msiof.c index 75c9e91bada10289..36d31ab8ac6a5f18 100644 --- a/sound/soc/renesas/rcar/msiof.c +++ b/sound/soc/renesas/rcar/msiof.c @@ -30,56 +30,15 @@ #include #include #include +#include #include #include -/* register */ -#define SITMDR1 0x00 -#define SITMDR2 0x04 -#define SITMDR3 0x08 -#define SIRMDR1 0x10 -#define SIRMDR2 0x14 -#define SIRMDR3 0x18 -#define SICTR 0x28 -#define SISTR 0x40 -#define SIIER 0x44 -#define SITFDR 0x50 -#define SIRFDR 0x60 - -/* SITMDR1/ SIRMDR1 */ -#define PCON (1 << 30) /* Transfer Signal Connection */ -#define SYNCMD_LR (3 << 28) /* L/R mode */ -#define SYNCAC (1 << 25) /* Sync Polarity (Active-low) */ -#define DTDL_1 (1 << 20) /* 1-clock-cycle delay */ -#define TXSTP (1 << 0) /* Transmission/Reception Stop on FIFO */ - -/* SITMDR2 and SIRMDR2 */ -#define BITLEN1(x) (((x) - 1) << 24) /* Data Size (8-32 bits) */ -#define GRP (1 << 30) /* Group count */ - -/* SICTR */ -#define TEDG (1 << 27) /* Transmit Timing (1 = falling edge) */ -#define REDG (1 << 26) /* Receive Timing (1 = rising edge) */ -#define TXE (1 << 9) /* Transmit Enable */ -#define RXE (1 << 8) /* Receive Enable */ - /* SISTR */ -#define TFSERR (1 << 21) /* Transmit Frame Synchronization Error */ -#define TFOVF (1 << 20) /* Transmit FIFO Overflow */ -#define TFUDF (1 << 19) /* Transmit FIFO Underflow */ -#define RFSERR (1 << 5) /* Receive Frame Synchronization Error */ -#define RFUDF (1 << 4) /* Receive FIFO Underflow */ -#define RFOVF (1 << 3) /* Receive FIFO Overflow */ -#define SISTR_ERR_TX (TFSERR | TFOVF | TFUDF) -#define SISTR_ERR_RX (RFSERR | RFOVF | RFUDF) +#define SISTR_ERR_TX (SISTR_TFSERR | SISTR_TFOVF | SISTR_TFUDF) +#define SISTR_ERR_RX (SISTR_RFSERR | SISTR_RFOVF | SISTR_RFUDF) #define SISTR_ERR (SISTR_ERR_TX | SISTR_ERR_RX) -/* SIIER */ -#define TDMAE (1 << 31) /* Transmit Data DMA Transfer Req. Enable */ -#define TDREQE (1 << 28) /* Transmit Data Transfer Request Enable */ -#define RDMAE (1 << 15) /* Receive Data DMA Transfer Req. Enable */ -#define RDREQE (1 << 12) /* Receive Data Transfer Request Enable */ - /* * The data on memory in 24bit case is located at side * [ xxxxxx] @@ -174,42 +133,45 @@ static int msiof_hw_start(struct snd_soc_component *component, /* SITMDRx */ if (is_play) { - val = PCON | SYNCMD_LR | SYNCAC | TXSTP; + val = SITMDR1_PCON | + FIELD_PREP(SIMDR1_SYNCMD, SIMDR1_SYNCMD_LR) | + SIMDR1_SYNCAC | SIMDR1_XXSTP; if (msiof_flag_has(priv, MSIOF_FLAGS_NEED_DELAY)) - val |= DTDL_1; + val |= FIELD_PREP(SIMDR1_DTDL, 1); msiof_write(priv, SITMDR1, val); - val = BITLEN1(width); - msiof_write(priv, SITMDR2, val | GRP); + val = FIELD_PREP(SIMDR2_BITLEN1, width - 1); + msiof_write(priv, SITMDR2, val | FIELD_PREP(SIMDR2_GRP, 1)); msiof_write(priv, SITMDR3, val); } /* SIRMDRx */ else { - val = SYNCMD_LR | SYNCAC; + val = FIELD_PREP(SIMDR1_SYNCMD, SIMDR1_SYNCMD_LR) | + SIMDR1_SYNCAC; if (msiof_flag_has(priv, MSIOF_FLAGS_NEED_DELAY)) - val |= DTDL_1; + val |= FIELD_PREP(SIMDR1_DTDL, 1); msiof_write(priv, SIRMDR1, val); - val = BITLEN1(width); - msiof_write(priv, SIRMDR2, val | GRP); + val = FIELD_PREP(SIMDR2_BITLEN1, width - 1); + msiof_write(priv, SIRMDR2, val | FIELD_PREP(SIMDR2_GRP, 1)); msiof_write(priv, SIRMDR3, val); } /* SIIER */ if (is_play) - val = TDREQE | TDMAE | SISTR_ERR_TX; + val = SIIER_TDREQE | SIIER_TDMAE | SISTR_ERR_TX; else - val = RDREQE | RDMAE | SISTR_ERR_RX; + val = SIIER_RDREQE | SIIER_RDMAE | SISTR_ERR_RX; msiof_update(priv, SIIER, val, val); /* SICTR */ if (is_play) - val = TXE | TEDG; + val = SICTR_TXE | SICTR_TEDG; else - val = RXE | REDG; + val = SICTR_RXE | SICTR_REDG; msiof_update_and_wait(priv, SICTR, val, val, val); msiof_status_clear(priv); @@ -230,9 +192,9 @@ static int msiof_hw_stop(struct snd_soc_component *component, /* SIIER */ if (is_play) - val = TDREQE | TDMAE | SISTR_ERR_TX; + val = SIIER_TDREQE | SIIER_TDMAE | SISTR_ERR_TX; else - val = RDREQE | RDMAE | SISTR_ERR_RX; + val = SIIER_RDREQE | SIIER_RDMAE | SISTR_ERR_RX; msiof_update(priv, SIIER, val, 0); /* Stop DMAC */ @@ -240,9 +202,9 @@ static int msiof_hw_stop(struct snd_soc_component *component, /* SICTR */ if (is_play) - val = TXE; + val = SICTR_TXE; else - val = RXE; + val = SICTR_RXE; msiof_update_and_wait(priv, SICTR, val, 0, 0); /* indicate error status if exist */ @@ -478,22 +440,22 @@ static irqreturn_t msiof_interrupt(int irq, void *data) substream = priv->substream[SNDRV_PCM_STREAM_PLAYBACK]; if (substream && (sistr & SISTR_ERR_TX)) { // snd_pcm_stop_xrun(substream); - if (sistr & TFSERR) + if (sistr & SISTR_TFSERR) priv->err_syc[SNDRV_PCM_STREAM_PLAYBACK]++; - if (sistr & TFOVF) + if (sistr & SISTR_TFOVF) priv->err_ovf[SNDRV_PCM_STREAM_PLAYBACK]++; - if (sistr & TFUDF) + if (sistr & SISTR_TFUDF) priv->err_udf[SNDRV_PCM_STREAM_PLAYBACK]++; } substream = priv->substream[SNDRV_PCM_STREAM_CAPTURE]; if (substream && (sistr & SISTR_ERR_RX)) { // snd_pcm_stop_xrun(substream); - if (sistr & RFSERR) + if (sistr & SISTR_RFSERR) priv->err_syc[SNDRV_PCM_STREAM_CAPTURE]++; - if (sistr & RFOVF) + if (sistr & SISTR_RFOVF) priv->err_ovf[SNDRV_PCM_STREAM_CAPTURE]++; - if (sistr & RFUDF) + if (sistr & SISTR_RFUDF) priv->err_udf[SNDRV_PCM_STREAM_CAPTURE]++; }