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Fri, 16 May 2025 05:43:58 -0700 From: Akhil R To: , , , , , , , , , , , , CC: Akhil R Subject: [PATCH v2 1/3] dt-bindings: i2c: Add required properties Date: Fri, 16 May 2025 18:13:47 +0530 Message-ID: <20250516124349.58318-1-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.43.2 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7B:EE_|DM6PR12MB4106:EE_ X-MS-Office365-Filtering-Correlation-Id: d6f1dec8-d3c2-46c5-b569-08dd947761d6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|7416014|36860700013|1800799024|82310400026|921020; X-Microsoft-Antispam-Message-Info: Z8pPDB9fRjj+lGRVmmajOIROncBx2AyiUPv/Gm3zhTGnNCjm585tqxT950Awx8qCtt4w7U06GjGLS4tJxZBWnOesg0WpVidk6md0Wo7Cy6gTBCRNT0de5cCQMCrv+QLP4SfzuMVIghVKtM6F44tdee0xbzeknDnE1XUaeQKmUICQTyXIajD35XaHrk6eT2travUNSoaWXEaQPh7sJNWH+zqnP4XpmpVx/4niM0aazJ4JOdfBncaR/+y5qYd24rFeXhS8wxMsTXmNr1oORG4cSCSAtgNy7qQBRpe7lEClhPEk5zoPr3HctSphfwJYYeQKqAHk+cERb0CdvgnHJDuNCEWNu+QbJniNQqdHbkAjckQXiqQLNlaXuxi0Jn1sD8vOG8NJh+NbaJgQX1BqaL9UdlLgeTDZ3RjJI1JTrujLeUh6unfCYvhDcNxbiIQUf1CO9JUdiYwUFc90iTvXqgFGLbMCnpi4MU5xAkl97BjSFBeUWVj0L66euKRpfjRCzutF9i47q8aX1Sfa5wxz+/5qff+pz1U5tokqObL/19VB4MsMKeoAcka20bZMfPUq9qxsbyXUUlFd1uekAEmDk5pHdqi3yWyrNrkUqd40oibeYNEJila8K36TidWukzCuZUW/ZBf55UzjY+L5hCJrOT+TJdprz1kYwtHZPvluAGsTHZPryzvFiE+6tn8PPAOlJxWoVyeNnU0MgwQwd/hsWPVK98j3LnhXTLfi0aPaFOQ41BlcwgEGxVf4nHHVkA6nUlmoVsGeAcncn5+OM2jET9z/iua+A9SoE3MUG78L2i7ZjZAAqHBTR1wcBof9T3RAWPOPIV5nBigYD/TySzaA5OtCjQwQ9VmWBdGt4c//noUj4CiCCWu6lVQaRkyQZbGhvBZzlXysYXmM7nzjWXapdygXuWgqMUJiPM6IPw7LJnHMcUAYZ1O1uuKwoAQMKZkYmv9G5M8jK0LzsmGOf1kX3D96oTzK58xb+pNRVVH2i+kaS+vyxpgSVPId/Xzj898XqbI+8xBBqvjBSsZ592rMZ2X94Vd1p2pivIwCykCqlPXO5xIv/gihvUEvu2FLBWEoy6WSYGUZleLsSUlhNs8OtF7YX8wK6Chwp0pVIyBfPOdj5zLCRPUgfPNzwURBw8H+4Qqctlwy9wNudgn2qekS3//u/ITDkY1NZCm735iWcQSAbrEZ2mgmeO3J3BMgef6CPw2KaOdfZ5rQSLTHxbev7we9HhMw9eLI1Lrdd55Ea7AhnDBhdovCTCRWN1SaiR9ih2x3icfkLESiETalxtdweVRXbE+3RsVXAeOS/xGRbw1AhLTuks0xCK5YFRXo6jcsXHoAkaNUMm4JkxgRRpvH8cOdSQb94w7qSiOREuORIQ8zsiD8H6F1Q87mS06F871zvZQQQyjhWHwbI2OCAtkNs8LSPChRS4yrwfcR7osAzqlUKfg3fxjjPHCqv0llt65D1vYZW2P56gWeE9YAhFqprsnok4W8WQZj8NmPVFUt3uKKAW+nitRsfrRYby/S1xstMlVXbOKX4JTHfRdkFZtim3kPVA== X-Forefront-Antispam-Report: CIP:216.228.117.161; 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Signed-off-by: Akhil R --- v1->v2: * Added all required properties .../bindings/i2c/nvidia,tegra20-i2c.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml index 19aefc022c8b..0717f2304cfc 100644 --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml @@ -118,6 +118,13 @@ properties: - const: rx - const: tx +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + allOf: - $ref: /schemas/i2c/i2c-controller.yaml - if: @@ -171,6 +178,18 @@ allOf: properties: power-domains: false + - if: + not: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-i2c + then: + required: + - resets + - reset-names + unevaluatedProperties: false examples: From patchwork Fri May 16 12:43:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil R X-Patchwork-Id: 890694 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2045.outbound.protection.outlook.com [40.107.243.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CED323814C; 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This is useful in systems that choose to restrict reset control from Linux. Signed-off-by: Akhil R --- v1->v2: * Call devm_reset_control_get_optional_exclusive() unconditionally. * Add more delay based on HW recommendation. drivers/i2c/busses/i2c-tegra.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 87976e99e6d0..22ddbae9d847 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -134,6 +134,8 @@ #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16) #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) +#define I2C_MASTER_RESET_CNTRL 0x0a8 + /* configuration load timeout in microseconds */ #define I2C_CONFIG_LOAD_TIMEOUT 1000000 @@ -184,6 +186,9 @@ enum msg_end_type { * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that * provides additional features and allows for longer messages to * be transferred in one go. + * @has_mst_reset: The I2C controller contains MASTER_RESET_CTRL register which + * provides an alternative to controller reset when configured as + * I2C master * @quirks: I2C adapter quirks for limiting write/read transfer size and not * allowing 0 length transfers. * @supports_bus_clear: Bus Clear support to recover from bus hang during @@ -213,6 +218,7 @@ struct tegra_i2c_hw_feature { bool has_multi_master_mode; bool has_slcg_override_reg; bool has_mst_fifo; + bool has_mst_reset; const struct i2c_adapter_quirks *quirks; bool supports_bus_clear; bool has_apb_dma; @@ -604,6 +610,20 @@ static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) return 0; } +static int tegra_i2c_master_reset(struct tegra_i2c_dev *i2c_dev) +{ + if (!i2c_dev->hw->has_mst_reset) + return -EOPNOTSUPP; + + i2c_writel(i2c_dev, 0x1, I2C_MASTER_RESET_CNTRL); + udelay(2); + + i2c_writel(i2c_dev, 0x0, I2C_MASTER_RESET_CNTRL); + udelay(2); + + return 0; +} + static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) { u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; @@ -621,8 +641,10 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) */ if (handle) err = acpi_evaluate_object(handle, "_RST", NULL, NULL); - else + else if (i2c_dev->rst) err = reset_control_reset(i2c_dev->rst); + else + err = tegra_i2c_master_reset(i2c_dev); WARN_ON_ONCE(err); @@ -1467,6 +1489,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = false, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = false, .has_apb_dma = true, @@ -1491,6 +1514,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = false, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = false, .has_apb_dma = true, @@ -1515,6 +1539,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = false, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = true, @@ -1539,6 +1564,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = true, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = true, @@ -1563,6 +1589,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = true, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = true, @@ -1587,6 +1614,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = true, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = false, @@ -1611,6 +1639,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .has_multi_master_mode = true, .has_slcg_override_reg = true, .has_mst_fifo = true, + .has_mst_reset = true, .quirks = &tegra194_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = false, @@ -1666,7 +1695,7 @@ static int tegra_i2c_init_reset(struct tegra_i2c_dev *i2c_dev) if (ACPI_HANDLE(i2c_dev->dev)) return 0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(7416014)(82310400026)(376014)(36860700013)(13003099007)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2025 12:44:48.7410 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 45107a37-b72c-42e5-ba91-08dd947771d8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD74.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8091 Calling dma_sync_*() on a buffer from dma_alloc_coherent() is pointless. The driver should not be doing its own bounce-buffering if the buffer is allocated through dma_alloc_coherent() Suggested-by: Robin Murphy Signed-off-by: Akhil R --- v1->v2: No changes Related thread - https://lore.kernel.org/all/acdbf49c-1a73-a0b9-a10d-42d544be3117@arm.com/ drivers/i2c/busses/i2c-tegra.c | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 22ddbae9d847..b10a4bc9cb34 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -1292,17 +1292,9 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, if (i2c_dev->dma_mode) { if (i2c_dev->msg_read) { - dma_sync_single_for_device(i2c_dev->dma_dev, - i2c_dev->dma_phys, - xfer_size, DMA_FROM_DEVICE); - err = tegra_i2c_dma_submit(i2c_dev, xfer_size); if (err) return err; - } else { - dma_sync_single_for_cpu(i2c_dev->dma_dev, - i2c_dev->dma_phys, - xfer_size, DMA_TO_DEVICE); } } @@ -1312,11 +1304,6 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, if (i2c_dev->dma_mode) { memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE, msg->buf, i2c_dev->msg_len); - - dma_sync_single_for_device(i2c_dev->dma_dev, - i2c_dev->dma_phys, - xfer_size, DMA_TO_DEVICE); - err = tegra_i2c_dma_submit(i2c_dev, xfer_size); if (err) return err; @@ -1357,13 +1344,8 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, return -ETIMEDOUT; } - if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) { - dma_sync_single_for_cpu(i2c_dev->dma_dev, - i2c_dev->dma_phys, - xfer_size, DMA_FROM_DEVICE); - + if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, i2c_dev->msg_len); - } } time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete,