From patchwork Fri May 16 23:18:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Biggers X-Patchwork-Id: 890664 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC4D3280A53; Fri, 16 May 2025 23:21:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747437702; cv=none; b=LssBJtt6uZKs+6U7wkLbbXIwy6jGgnmt/fcDb0Edx+Jkq73Y1eXd9yZYBUOQfVsHoNuLIEE19AUW6VtOQBgY9dLU12BfUuYHnV+Sa/iRDKeQz7nNzkYJ+I1xWQqPlHfgUChVZKBnCydZu1Rnsb/bmBSVhEKKoT+xCDlD//n3Wu0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747437702; c=relaxed/simple; bh=EyEIYHKmSDcRWjcjZuBlOz8/xbPehLGEHqj0Xc579mU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QgLofKP/sAhlhuBzW8ObPa2hDwBJAhx+td52vixJWj8SdUxTpygTs7IEEwOmdLMdqPiCrjshD2/zoC0qJZ5EWUH78EwSFtl+N2fGUhH2Yj7kvhPd2OCNsMq/nk36ZL0f/lg1Py8CQY2F4Ic9+7ioLBiH2bA2j5xjIHw92ovGVX8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dV/au78r; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dV/au78r" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3DC29C4CEE9; Fri, 16 May 2025 23:21:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747437700; bh=EyEIYHKmSDcRWjcjZuBlOz8/xbPehLGEHqj0Xc579mU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dV/au78riVFVpGQw7WnhYNZLgBcB/NnyKgJNRSWGsVkWk4m16wMco8idAskCoVfLO +LyAWGHYkZtKuQjN4PEBCRu8Mb7FQBLbjqMJUEURUzN5VgMgIBf+rXvKkd7MGfjRT3 nmf0YijhWYWA6TcwhMqE+IcCvn+XfTkBP7PzhHKgkfdu+xp6ESbq6xR5zRiuyWHORP CPb/zH6GuDCNlbfsa0VDd/EGyw+mAXzI8YwKeDEKVEzPuZIWywIN0BzTJoCu8wsEi9 Kc82iV1eU0k5WHKrox6k+Qt3VgR1aBwNHkjKKmtqgSuYMTGI/qKVziu7BXyz18595+ ADb2u8YfmKJvQ== From: Eric Biggers To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, linux-pm@vger.kernel.org, Borislav Petkov , Thomas Gleixner , Ayush Jain , Herbert Xu , Ard Biesheuvel Subject: [PATCH 1/3] x86/fpu: Add fpu_save_state() for __save_processor_state() Date: Fri, 16 May 2025 16:18:56 -0700 Message-ID: <20250516231858.27899-2-ebiggers@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250516231858.27899-1-ebiggers@kernel.org> References: <20250516231858.27899-1-ebiggers@kernel.org> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Eric Biggers Add a new function fpu_save_state() which handles the FPU state saving and invalidation that __save_processor_state() needs. This will allow __save_processor_state() to stop using kernel_fpu_begin() and kernel_fpu_end() for something other than actual kernel-mode FPU. Signed-off-by: Eric Biggers --- arch/x86/include/asm/fpu/api.h | 1 + arch/x86/kernel/fpu/core.c | 43 ++++++++++++++++++++++++++++------ 2 files changed, 37 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/fpu/api.h b/arch/x86/include/asm/fpu/api.h index 8e6848f55dcdb..3ad359c5b100e 100644 --- a/arch/x86/include/asm/fpu/api.h +++ b/arch/x86/include/asm/fpu/api.h @@ -26,10 +26,11 @@ #define KFPU_MXCSR _BITUL(1) /* MXCSR will be initialized */ extern void kernel_fpu_begin_mask(unsigned int kfpu_mask); extern void kernel_fpu_end(void); extern bool irq_fpu_usable(void); +extern void fpu_save_state(void); extern void fpregs_mark_activate(void); /* Code that is unaware of kernel_fpu_begin_mask() can use this */ static inline void kernel_fpu_begin(void) { diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index 948b4f5fad99c..476393b1d5e8f 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -118,11 +118,11 @@ static void update_avx_timestamp(struct fpu *fpu) /* * Save the FPU register state in fpu->fpstate->regs. The register state is * preserved. * - * Must be called with fpregs_lock() held. + * Must be called with fpregs_lock() held or hardirqs disabled. * * The legacy FNSAVE instruction clears all FPU state unconditionally, so * register state has to be reloaded. That might be a pointless exercise * when the FPU is going to be used by another task right after that. But * this only affects 20+ years old 32bit systems and avoids conditionals all @@ -431,26 +431,31 @@ int fpu_copy_uabi_to_guest_fpstate(struct fpu_guest *gfpu, const void *buf, return copy_uabi_from_kernel_to_xstate(kstate, ustate, vpkru); } EXPORT_SYMBOL_GPL(fpu_copy_uabi_to_guest_fpstate); #endif /* CONFIG_KVM */ +static __always_inline void __fpu_save_state(void) +{ + if (!(current->flags & (PF_KTHREAD | PF_USER_WORKER)) && + !test_thread_flag(TIF_NEED_FPU_LOAD)) { + set_thread_flag(TIF_NEED_FPU_LOAD); + save_fpregs_to_fpstate(x86_task_fpu(current)); + } + __cpu_invalidate_fpregs_state(); +} + void kernel_fpu_begin_mask(unsigned int kfpu_mask) { if (!irqs_disabled()) fpregs_lock(); WARN_ON_FPU(!irq_fpu_usable()); WARN_ON_FPU(this_cpu_read(in_kernel_fpu)); this_cpu_write(in_kernel_fpu, true); - if (!(current->flags & (PF_KTHREAD | PF_USER_WORKER)) && - !test_thread_flag(TIF_NEED_FPU_LOAD)) { - set_thread_flag(TIF_NEED_FPU_LOAD); - save_fpregs_to_fpstate(x86_task_fpu(current)); - } - __cpu_invalidate_fpregs_state(); + __fpu_save_state(); /* Put sane initial values into the control registers. */ if (likely(kfpu_mask & KFPU_MXCSR) && boot_cpu_has(X86_FEATURE_XMM)) ldmxcsr(MXCSR_DEFAULT); @@ -467,10 +472,34 @@ void kernel_fpu_end(void) if (!irqs_disabled()) fpregs_unlock(); } EXPORT_SYMBOL_GPL(kernel_fpu_end); +#ifdef CONFIG_PM_SLEEP +/* + * If the FPU registers are live for the current task, save them to current's + * memory register state and set TIF_NEED_FPU_LOAD. This is used by the suspend + * and kexec code to prepare for the FPU registers being clobbered. Unlike + * kernel_fpu_begin(), this function can be called with hardirqs disabled, and + * it does not initialize the FPU control registers for kernel-mode FPU use. + */ +void fpu_save_state(void) +{ + unsigned long flags; + + WARN_ON_FPU(this_cpu_read(in_kernel_fpu)); + + /* + * This is sometimes called with hardirqs disabled, so we need to use + * local_irq_save/restore() instead of fpregs_lock/unlock(). + */ + local_irq_save(flags); + __fpu_save_state(); + local_irq_restore(flags); +} +#endif /* CONFIG_PM_SLEEP */ + /* * Sync the FPU register state to current's memory register state when the * current task owns the FPU. The hardware register state is preserved. */ void fpu_sync_fpstate(struct fpu *fpu) From patchwork Fri May 16 23:18:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Biggers X-Patchwork-Id: 890665 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 078BC22DA15; Fri, 16 May 2025 23:21:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747437701; cv=none; b=OEwNcswIhwiM+7ac3mi/vXfnnSvxbS2nh5ipeTwcBTM91/D/cGle2VznF6kzDm8YUbk3ZsmJNjGgjIy4u+QFatbZbHzuYCsf0prXD6T01739ES48KfX8g0T9nd4HHbqUF9OuyTX7rkG7aUchZT7vLerCXynVMm/imR2kT46QIvQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747437701; c=relaxed/simple; bh=OwRlj0tM+iP/0crW1PSRzlCFDkAFzLKKS3A/BV9mA2A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Jtblw81xeFaOpVnM1Ho3JPSvbX8YFoM4Z4DWgkS+iTXZ+f1g5J7bCAAW47K3O09KfhxUXjQFFDnVWKcwjIAVDqEwFfsQgqPIH+aswuVfeJ0PubpFpFcelNhzvgjT+6gDHTUbKz9xnsya2A4Iijt+o12joz+z+eh6KVIVblEt3hA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=obsMl2Qj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="obsMl2Qj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9EFECC4AF0B; Fri, 16 May 2025 23:21:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747437700; bh=OwRlj0tM+iP/0crW1PSRzlCFDkAFzLKKS3A/BV9mA2A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=obsMl2Qj/M0jALKhFX8su33JKI/fDILbHUAKFbgBNwOXicOKeOUSukI71e3Xn8x3U zobV0ZMt9YtTApbmnAGXvlblFbdTcVpXUAw1yuc5z/4YO53g/WNrwrjK6EnRSxi4Xc eyZIzFVdY0IxzIhP89CXPmkWR90EBmhMULqJVjEDELOJDvdCdOgHtTDfbyhq+45Hir dKEQIG2U+hHyl4985BUe3Nu5PlJcEA/oXIQ4OXiFynFoObxI9AKa2Hnd9xKSLIDxHl HP7oI+TNxanGWdVKRJvmFHXhYYri4WzG5pAzHv69fZoS7dyP4l+d6A6vbUwDd+HEKi 1uobTrZiUx7QA== From: Eric Biggers To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, linux-pm@vger.kernel.org, Borislav Petkov , Thomas Gleixner , Ayush Jain , Herbert Xu , Ard Biesheuvel Subject: [PATCH 2/3] x86/pm: Use fpu_save_state() in __save_processor_state() Date: Fri, 16 May 2025 16:18:57 -0700 Message-ID: <20250516231858.27899-3-ebiggers@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250516231858.27899-1-ebiggers@kernel.org> References: <20250516231858.27899-1-ebiggers@kernel.org> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Eric Biggers Make __save_processor_state() use fpu_save_state() instead of a kernel_fpu_begin() and kernel_fpu_end() pair. This matches more directly what it needs. This eliminates the need for kernel_fpu_begin() and kernel_fpu_end() to support the irqs_disabled() case. Signed-off-by: Eric Biggers --- arch/x86/power/cpu.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c index 916441f5e85ce..dde4ccbc77f4b 100644 --- a/arch/x86/power/cpu.c +++ b/arch/x86/power/cpu.c @@ -81,11 +81,17 @@ static void msr_restore_context(struct saved_context *ctxt) static void __save_processor_state(struct saved_context *ctxt) { #ifdef CONFIG_X86_32 mtrr_save_fixed_ranges(NULL); #endif - kernel_fpu_begin(); + + /* + * The FPU registers may be live for the current task, so save them to + * current's memory register state. The corresponding restore happens + * lazily when returning to userspace, not in restore_processor_state(). + */ + fpu_save_state(); /* * descriptor tables */ store_idt(&ctxt->idt); @@ -99,11 +105,10 @@ static void __save_processor_state(struct saved_context *ctxt) ctxt->gdt_desc.size = GDT_SIZE - 1; ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_rw(smp_processor_id()); store_tr(ctxt->tr); - /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */ /* * segment registers */ savesegment(gs, ctxt->gs); #ifdef CONFIG_X86_64 @@ -139,18 +144,10 @@ void save_processor_state(void) } #ifdef CONFIG_X86_32 EXPORT_SYMBOL(save_processor_state); #endif -static void do_fpu_end(void) -{ - /* - * Restore FPU regs if necessary. - */ - kernel_fpu_end(); -} - static void fix_processor_context(void) { int cpu = smp_processor_id(); #ifdef CONFIG_X86_64 struct desc_struct *desc = get_cpu_gdt_rw(cpu); @@ -272,11 +269,10 @@ static void notrace __restore_processor_state(struct saved_context *ctxt) wrmsrq(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); #else loadsegment(gs, ctxt->gs); #endif - do_fpu_end(); tsc_verify_tsc_adjust(true); x86_platform.restore_sched_clock_state(); cache_bp_restore(); perf_restore_debug_store();