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Thu, 15 May 2025 11:55:31 -0700 (PDT) Received: from NB-GIGA003.letovo.school ([95.167.212.10]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-550e702dd8asm60389e87.196.2025.05.15.11.55.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 11:55:31 -0700 (PDT) From: Alexey Charkov Date: Thu, 15 May 2025 21:55:27 +0300 Subject: [PATCH v3 2/4] clocksource/drivers/timer-vt8500: Add defines for magic constants Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250515-vt8500-timer-updates-v3-2-2197a1b062bd@gmail.com> References: <20250515-vt8500-timer-updates-v3-0-2197a1b062bd@gmail.com> In-Reply-To: <20250515-vt8500-timer-updates-v3-0-2197a1b062bd@gmail.com> To: Krzysztof Kozlowski , Daniel Lezcano , Thomas Gleixner , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Wim Van Sebroeck , Guenter Roeck Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-watchdog@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747335328; l=4723; i=alchark@gmail.com; s=20250416; h=from:subject:message-id; bh=4CyYsnhnKma2xppJbhsHsOk6fmvNYSaorpOr7AaIMyg=; b=oax/cP43gm6/fN+1TVTnpNq77UoNNvIAD9cQbR19U34VFUVdyq2fIGy/3QiCSwVASJSocHcBl gHX4ZTGOHRIAxWTYub6LTkjMpWNNQhcWHPEoZWR9SQ3DKbXm/Qp759D X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=ltKbQzKLTJPiDgPtcHxdo+dzFthCCMtC3V9qf7+0rkc= Add defines for all known registers and their bits to make the code more self-explanatory. While at that, replace _VAL suffixes with more intuitive _REG suffixes on register offsets. No functional changes. Signed-off-by: Alexey Charkov --- drivers/clocksource/timer-vt8500.c | 65 ++++++++++++++++++++++++-------------- 1 file changed, 42 insertions(+), 23 deletions(-) diff --git a/drivers/clocksource/timer-vt8500.c b/drivers/clocksource/timer-vt8500.c index a469b1b5f97233202bf01298b9f612e07026c20c..9f28f30dcaf83ab4e9c89952175b0d4c75bd6b40 100644 --- a/drivers/clocksource/timer-vt8500.c +++ b/drivers/clocksource/timer-vt8500.c @@ -24,15 +24,31 @@ #define VT8500_TIMER_OFFSET 0x0100 #define VT8500_TIMER_HZ 3000000 -#define TIMER_MATCH_VAL 0x0000 -#define TIMER_COUNT_VAL 0x0010 -#define TIMER_STATUS_VAL 0x0014 -#define TIMER_IER_VAL 0x001c /* interrupt enable */ -#define TIMER_CTRL_VAL 0x0020 -#define TIMER_AS_VAL 0x0024 /* access status */ -#define TIMER_COUNT_R_ACTIVE (1 << 5) /* not ready for read */ -#define TIMER_COUNT_W_ACTIVE (1 << 4) /* not ready for write */ -#define TIMER_MATCH_W_ACTIVE (1 << 0) /* not ready for write */ + +#define TIMER_MATCH_REG(x) (4 * (x)) +#define TIMER_COUNT_REG 0x0010 /* clocksource counter */ + +#define TIMER_STATUS_REG 0x0014 +#define TIMER_STATUS_MATCH(x) BIT((x)) +#define TIMER_STATUS_CLEARALL (TIMER_STATUS_MATCH(0) | \ + TIMER_STATUS_MATCH(1) | \ + TIMER_STATUS_MATCH(2) | \ + TIMER_STATUS_MATCH(3)) + +#define TIMER_WATCHDOG_EN_REG 0x0018 +#define TIMER_WD_EN BIT(0) + +#define TIMER_INT_EN_REG 0x001c /* interrupt enable */ +#define TIMER_INT_EN_MATCH(x) BIT((x)) + +#define TIMER_CTRL_REG 0x0020 +#define TIMER_CTRL_ENABLE BIT(0) /* enable clocksource counter */ +#define TIMER_CTRL_RD_REQ BIT(1) /* request counter read */ + +#define TIMER_ACC_STS_REG 0x0024 /* access status */ +#define TIMER_ACC_WR_MATCH(x) BIT((x)) /* writing Match (x) value */ +#define TIMER_ACC_WR_COUNTER BIT(4) /* writing clocksource counter */ +#define TIMER_ACC_RD_COUNTER BIT(5) /* reading clocksource counter */ #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) @@ -43,11 +59,12 @@ static void __iomem *regbase; static u64 vt8500_timer_read(struct clocksource *cs) { int loops = msecs_to_loops(10); - writel(3, regbase + TIMER_CTRL_VAL); - while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE) - && --loops) + + writel(TIMER_CTRL_ENABLE | TIMER_CTRL_RD_REQ, regbase + TIMER_CTRL_REG); + while (readl(regbase + TIMER_ACC_STS_REG) & TIMER_ACC_RD_COUNTER + && --loops) cpu_relax(); - return readl(regbase + TIMER_COUNT_VAL); + return readl(regbase + TIMER_COUNT_REG); } static struct clocksource clocksource = { @@ -63,23 +80,25 @@ static int vt8500_timer_set_next_event(unsigned long cycles, { int loops = msecs_to_loops(10); u64 alarm = clocksource.read(&clocksource) + cycles; - while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE) - && --loops) + + while (readl(regbase + TIMER_ACC_STS_REG) & TIMER_ACC_WR_MATCH(0) + && --loops) cpu_relax(); - writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL); + writel((unsigned long)alarm, regbase + TIMER_MATCH_REG(0)); if ((signed)(alarm - clocksource.read(&clocksource)) <= MIN_OSCR_DELTA) return -ETIME; - writel(1, regbase + TIMER_IER_VAL); + writel(TIMER_INT_EN_MATCH(0), regbase + TIMER_INT_EN_REG); return 0; } static int vt8500_shutdown(struct clock_event_device *evt) { - writel(readl(regbase + TIMER_CTRL_VAL) | 1, regbase + TIMER_CTRL_VAL); - writel(0, regbase + TIMER_IER_VAL); + writel(readl(regbase + TIMER_CTRL_REG) | TIMER_CTRL_ENABLE, + regbase + TIMER_CTRL_REG); + writel(0, regbase + TIMER_INT_EN_REG); return 0; } @@ -95,7 +114,7 @@ static struct clock_event_device clockevent = { static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = dev_id; - writel(0xf, regbase + TIMER_STATUS_VAL); + writel(TIMER_STATUS_CLEARALL, regbase + TIMER_STATUS_REG); evt->event_handler(evt); return IRQ_HANDLED; @@ -119,9 +138,9 @@ static int __init vt8500_timer_init(struct device_node *np) return -EINVAL; } - writel(1, regbase + TIMER_CTRL_VAL); - writel(0xf, regbase + TIMER_STATUS_VAL); - writel(~0, regbase + TIMER_MATCH_VAL); + writel(TIMER_CTRL_ENABLE, regbase + TIMER_CTRL_REG); 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Thu, 15 May 2025 11:55:33 -0700 (PDT) Received: from NB-GIGA003.letovo.school ([95.167.212.10]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-550e702dd8asm60389e87.196.2025.05.15.11.55.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 11:55:33 -0700 (PDT) From: Alexey Charkov Date: Thu, 15 May 2025 21:55:29 +0300 Subject: [PATCH v3 4/4] watchdog: Add support for VIA/WonderMedia SoC watchdog functionality Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250515-vt8500-timer-updates-v3-4-2197a1b062bd@gmail.com> References: <20250515-vt8500-timer-updates-v3-0-2197a1b062bd@gmail.com> In-Reply-To: <20250515-vt8500-timer-updates-v3-0-2197a1b062bd@gmail.com> To: Krzysztof Kozlowski , Daniel Lezcano , Thomas Gleixner , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Wim Van Sebroeck , Guenter Roeck Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-watchdog@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747335328; l=6862; i=alchark@gmail.com; s=20250416; h=from:subject:message-id; bh=2XFRYiD91queAeJhWuLHIGRtox7ITgkji4UZkOxOnJU=; b=TCQO3le/NzI+O9M2LYnIFQZPy6L1dVDvBwVsgTeULw4pXLs/se7iBNx5Z11uwcTanQn+OeT+N PalmzHKo5kvAqLiKno6ziebxGbP/kUaEgcuoAV8Kx+bhK2dIPyFI6nq X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=ltKbQzKLTJPiDgPtcHxdo+dzFthCCMtC3V9qf7+0rkc= VIA/WonderMedia SoCs can use their system timer's first channel as a watchdog device which will reset the system if the clocksource counter matches the value given in its match register 0 and if the watchdog function is enabled. Since the watchdog function is tightly coupled to the timer itself, it is implemented as a child platform device of the timer device, and just reuses the MMIO registers already remapped by the timer driver. This is similar to the approach taken by gxp-wdt.c Signed-off-by: Alexey Charkov --- MAINTAINERS | 1 + drivers/watchdog/Kconfig | 14 +++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/vt8500-wdt.c | 116 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 132 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b8b2843491c47182a4fc6c76f5c29b6c411830a6..d809643b76ad299ca1c08804540b08cc4a7184a6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3446,6 +3446,7 @@ F: drivers/tty/serial/vt8500_serial.c F: drivers/video/fbdev/vt8500lcdfb.* F: drivers/video/fbdev/wm8505fb* F: drivers/video/fbdev/wmt_ge_rops.* +F: drivers/watchdog/vt8500-wdt.c ARM/ZYNQ ARCHITECTURE M: Michal Simek diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 0d8d37f712e8cfb4bf8156853baa13c23a57d6d9..429e4e775f1f458fd457067a3a039a5d544b4818 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -2003,6 +2003,20 @@ config PIC32_DMT To compile this driver as a loadable module, choose M here. The module will be called pic32-dmt. +config VT8500_WATCHDOG + tristate "VIA/WonderMedia VT8500 watchdog support" + depends on ARCH_VT8500 || COMPILE_TEST + select WATCHDOG_CORE + help + VIA/WonderMedia SoCs can use their system timer as a hardware + watchdog, as long as the first timer channel is free from other + uses and respective function is enabled in its registers. To + make use of it, say Y here and ensure that the device tree + lists at least two interrupts for the VT8500 timer device. + + To compile this driver as a module, choose M here. + The module will be called vt8500-wdt. + # PARISC Architecture # POWERPC Architecture diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index c9482904bf870a085c7fce2a439ac5089b6e6fee..3072786bf226c357102be3734fe6e701f753d45b 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -101,6 +101,7 @@ obj-$(CONFIG_MSC313E_WATCHDOG) += msc313e_wdt.o obj-$(CONFIG_APPLE_WATCHDOG) += apple_wdt.o obj-$(CONFIG_SUNPLUS_WATCHDOG) += sunplus_wdt.o obj-$(CONFIG_MARVELL_GTI_WDT) += marvell_gti_wdt.o +obj-$(CONFIG_VT8500_WATCHDOG) += vt8500-wdt.o # X86 (i386 + ia64 + x86_64) Architecture obj-$(CONFIG_ACQUIRE_WDT) += acquirewdt.o diff --git a/drivers/watchdog/vt8500-wdt.c b/drivers/watchdog/vt8500-wdt.c new file mode 100644 index 0000000000000000000000000000000000000000..8e605c850dd9f42c90104f362b74adac63dd9fdb --- /dev/null +++ b/drivers/watchdog/vt8500-wdt.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2025 Alexey Charkov +#include +#include +#include +#include +#include + +#define TIMER_MATCH_REG(x) (4 * (x)) +#define TIMER_COUNT_REG 0x0010 /* clocksource counter */ + +#define TIMER_WATCHDOG_EN_REG 0x0018 +#define TIMER_WD_EN BIT(0) + +#define TIMER_CTRL_REG 0x0020 +#define TIMER_CTRL_ENABLE BIT(0) /* enable clocksource counter */ +#define TIMER_CTRL_RD_REQ BIT(1) /* request counter read */ + +#define TIMER_ACC_STS_REG 0x0024 /* access status */ +#define TIMER_ACC_WR_MATCH(x) BIT((x)) /* writing Match (x) value */ +#define TIMER_ACC_WR_COUNTER BIT(4) /* writing clocksource counter */ +#define TIMER_ACC_RD_COUNTER BIT(5) /* reading clocksource counter */ + +#define VT8500_TIMER_HZ 3000000 +#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) + +struct vt8500_wdt { + void __iomem *regbase; + struct watchdog_device wdd; +}; + +static u64 vt8500_timer_read(void __iomem *regbase) +{ + int loops = msecs_to_loops(10); + + writel(TIMER_CTRL_ENABLE | TIMER_CTRL_RD_REQ, regbase + TIMER_CTRL_REG); + while (readl(regbase + TIMER_ACC_STS_REG) & TIMER_ACC_RD_COUNTER + && --loops) + cpu_relax(); + return readl(regbase + TIMER_COUNT_REG); +} + +static int vt8500_watchdog_start(struct watchdog_device *wdd) +{ + struct vt8500_wdt *drvdata = watchdog_get_drvdata(wdd); + u64 cycles = wdd->timeout * VT8500_TIMER_HZ; + u64 deadline = vt8500_timer_read(drvdata->regbase) + cycles; + + writel((u32)deadline, drvdata->regbase + TIMER_MATCH_REG(0)); + writel(TIMER_WD_EN, drvdata->regbase + TIMER_WATCHDOG_EN_REG); + return 0; +} + +static int vt8500_watchdog_stop(struct watchdog_device *wdd) +{ + struct vt8500_wdt *drvdata = watchdog_get_drvdata(wdd); + + writel(0, drvdata->regbase + TIMER_WATCHDOG_EN_REG); + return 0; +} + +static const struct watchdog_ops vt8500_watchdog_ops = { + .start = vt8500_watchdog_start, + .stop = vt8500_watchdog_stop, +}; + +static const struct watchdog_info vt8500_watchdog_info = { + .identity = "VIA VT8500 watchdog", + .options = WDIOF_MAGICCLOSE | + WDIOF_KEEPALIVEPING | + WDIOF_SETTIMEOUT, +}; + +static int vt8500_wdt_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct vt8500_wdt *drvdata; + + drvdata = devm_kzalloc(dev, sizeof(struct vt8500_wdt), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + /* + * The register area where the timer and watchdog reside is disarranged. + * Hence mapping individual register blocks for the timer and watchdog + * is not recommended as they would have access to each others + * registers. The timer driver creates the watchdog as a child device. + * During the watchdogs creation, the timer driver passes the base + * address to the watchdog over the private interface. + */ + + drvdata->regbase = (void __iomem *)dev->platform_data; + + drvdata->wdd.info = &vt8500_watchdog_info; + drvdata->wdd.ops = &vt8500_watchdog_ops; + drvdata->wdd.max_hw_heartbeat_ms = -1UL / (VT8500_TIMER_HZ / 1000); + drvdata->wdd.parent = dev; + + watchdog_set_drvdata(&drvdata->wdd, drvdata); + + return devm_watchdog_register_device(dev, &drvdata->wdd); +} + +static struct platform_driver vt8500_wdt_driver = { + .probe = vt8500_wdt_probe, + .driver = { + .name = "vt8500-wdt", + }, +}; +module_platform_driver(vt8500_wdt_driver); + +MODULE_AUTHOR("Alexey Charkov "); +MODULE_DESCRIPTION("Driver for the VIA VT8500 watchdog timer"); +MODULE_LICENSE("GPL");