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This change is a precursor to the next patchset in this series, which requires these two operations to be distinct. Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 37887ec68412..23b4fc84dc8c 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -531,6 +531,12 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) goto out_disable_phy; } + ret = phy_calibrate(phy); + if (ret) { + dev_err(hba->dev, "Failed to calibrate PHY: %d\n", ret); + goto out_disable_phy; + } + ufs_qcom_select_unipro_mode(host); return 0; From patchwork Thu May 15 16:27:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 890648 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E6EE21FF2E; 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Thu, 15 May 2025 16:27:30 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 54FGRRcw023562; Thu, 15 May 2025 16:27:27 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 46hyvmvnnb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 15 May 2025 16:27:27 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 54FGRRGO023551; Thu, 15 May 2025 16:27:27 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 54FGRQ2r023549; Thu, 15 May 2025 16:27:27 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id 6F1445015B0; Thu, 15 May 2025 21:57:26 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, bvanassche@acm.org, andersson@kernel.org, neil.armstrong@linaro.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat Subject: [PATCH V5 02/11] phy: qcom-qmp-ufs: Rename qmp_ufs_enable and qmp_ufs_power_on Date: Thu, 15 May 2025 21:57:13 +0530 Message-ID: <20250515162722.6933-3-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250515162722.6933-1-quic_nitirawa@quicinc.com> References: <20250515162722.6933-1-quic_nitirawa@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: R_cR6di3rKaCRK1bGAXrlZvehQqvvwYJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE2MyBTYWx0ZWRfX8RUSq3alCB9F 9u/+CB4WPVfNRPkguq82qFEk3EyPM1mViRc5blgTVUFLYTslKg8S64Y1ybMobiGC23+z/wrbUlP AHZEPsy6KHlOPAymXC/pA/pehfHTu2YP4BHbUt2aQKbrxRmcMkRVmuRGzTrwH0nVeja/rrcE9za NdoSyEWhTi/RAJZV0DcFFZxgUa9uxSKhIO/+jmC8VT4AB+yTE4nDECXt8RgMsMUJmABd4FzyIvC /6KTZqcWs4L8n3Y80jQQjlenLFgE5HxbD6L0SGsz9s2p1l5xFcf773eq0H7U4OrFhM63mIFJy7k 1pjtwYGvKoLBm3tna0bd9ONA0yLrEmx3g3J3vWVs2GuTdfa46cjeOesDwq5fUcIdmkYy3jLN1ei wo6ikqNZRATVE/PvhSjOU5yEJwM7Zy/UFcF23o0TlDRpo5f+IyBePGSP+UVF2VyQr6HugiNW X-Authority-Analysis: v=2.4 cv=K7UiHzWI c=1 sm=1 tr=0 ts=682615f2 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=jENGRIT2ScPjwYuSNhQA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: R_cR6di3rKaCRK1bGAXrlZvehQqvvwYJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_07,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 clxscore=1015 bulkscore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150163 Rename qmp_ufs_enable to qmp_ufs_power_on and qmp_ufs_power_on to qmp_ufs_phy_calibrate to better reflect their functionality. Also update function calls and structure assignments accordingly. Reviewed-by: Dmitry Baryshkov Co-developed-by: Ram Kumar Dwivedi Signed-off-by: Ram Kumar Dwivedi Signed-off-by: Nitin Rawat --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index b33e2e2b5014..a67cf0a64f74 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1838,7 +1838,7 @@ static int qmp_ufs_init(struct phy *phy) return 0; } -static int qmp_ufs_power_on(struct phy *phy) +static int qmp_ufs_phy_calibrate(struct phy *phy) { struct qmp_ufs *qmp = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qmp->cfg; @@ -1899,7 +1899,7 @@ static int qmp_ufs_exit(struct phy *phy) return 0; } -static int qmp_ufs_enable(struct phy *phy) +static int qmp_ufs_power_on(struct phy *phy) { int ret; @@ -1907,7 +1907,7 @@ static int qmp_ufs_enable(struct phy *phy) if (ret) return ret; - ret = qmp_ufs_power_on(phy); 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Thu, 15 May 2025 16:27:31 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 54FGRRQM023561; Thu, 15 May 2025 16:27:28 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 46hyvmvnnp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 15 May 2025 16:27:28 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 54FGRSJ9023569; Thu, 15 May 2025 16:27:28 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 54FGRRlQ023567; Thu, 15 May 2025 16:27:28 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id 5E1565015B0; Thu, 15 May 2025 21:57:27 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, bvanassche@acm.org, andersson@kernel.org, neil.armstrong@linaro.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat Subject: [PATCH V5 03/11] phy: qcom-qmp-ufs: Refactor phy_power_on and phy_calibrate callbacks Date: Thu, 15 May 2025 21:57:14 +0530 Message-ID: <20250515162722.6933-4-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250515162722.6933-1-quic_nitirawa@quicinc.com> References: <20250515162722.6933-1-quic_nitirawa@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: _m6yQ0eQXMshcArOy0APZhSXvD0HqsS- X-Proofpoint-ORIG-GUID: _m6yQ0eQXMshcArOy0APZhSXvD0HqsS- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE2MyBTYWx0ZWRfX75qGyqBJ5Yd3 1HfN+4w2eSxR1rCtgLLTGSXWtXGda4vklicM2aDvqe1O6PC7+5AURAUT4dDSDbPXZqJ1RFtN3NO ssTm82ZufByatHWgyAP3+wnj1l/ZoK35yaM8Drb267Zm0IGblDcL7MWBTI4uj0VWU0Ec10hksdI z9rTqJg2yxm5q8q2hmye688flkkQ6oBhI5qxPtT7+0lxrEP7Jc8oX0UjXO0tn8W98F4hZPS+0va b7TBUnAf41qC3oK1ccO8fIcBSL7ryJruvwXPKP1OSFtOfSqD0ac3+D9m8WfZBd1yaDCkCEtEFND XV2iqlYHtVtkl3OZpDJ6f+okNFA1fxdlxp6F3ngO7+AfAjMT15Bkyt5l4BM6CBD59Ic0X7cbeKp P5ARCxzTEa+3m5Aq/0MQr7MA5JT6Hx7wYeC0doZUUHEU5PxJGvN+UAzBN653vCkts5Pm8Uw6 X-Authority-Analysis: v=2.4 cv=LOFmQIW9 c=1 sm=1 tr=0 ts=682615f4 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=ZEhkBkkNTqPGxlI-GDwA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_07,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 adultscore=0 priorityscore=1501 suspectscore=0 mlxscore=0 malwarescore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 clxscore=1015 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150163 Commit 052553af6a31 ("ufs/phy: qcom: Refactor to use phy_init call") puts enabling regulators & clks, calibrating UFS PHY, starting serdes and polling PCS ready status into phy_power_on. In Current code regulators enable, clks enable, calibrating UFS PHY, start_serdes and polling PCS_ready_status are part of phy_power_on. UFS PHY registers are retained after power collapse, meaning calibrating UFS PHY, start_serdes and polling PCS_ready_status can be done only when hba is powered_on, and not needed every time when phy_power_on is called during resume. Hence keep the code which enables PHY's regulators & clks in phy_power_on and move the rest steps into phy_calibrate function. Refactor the code to retain PHY regulators & clks in phy_power_on and move out rest of the code to new phy_calibrate function. Also move reset_control_assert to qmp_ufs_phy_calibrate to align with Hardware programming guide. Reviewed-by: Dmitry Baryshkov Co-developed-by: Can Guo Signed-off-by: Can Guo Signed-off-by: Nitin Rawat --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 26 ++++++------------------- 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index a67cf0a64f74..ade8e9c4b9ae 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1797,7 +1797,7 @@ static int qmp_ufs_com_exit(struct qmp_ufs *qmp) return 0; } -static int qmp_ufs_init(struct phy *phy) +static int qmp_ufs_power_on(struct phy *phy) { struct qmp_ufs *qmp = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qmp->cfg; @@ -1825,10 +1825,6 @@ static int qmp_ufs_init(struct phy *phy) return ret; } } - - ret = reset_control_assert(qmp->ufs_reset); - if (ret) - return ret; } ret = qmp_ufs_com_init(qmp); @@ -1847,6 +1843,10 @@ static int qmp_ufs_phy_calibrate(struct phy *phy) unsigned int val; int ret; + ret = reset_control_assert(qmp->ufs_reset); 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Thu, 15 May 2025 16:27:32 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 54FGRTEP023599; Thu, 15 May 2025 16:27:29 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 46hyvmvnp1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 15 May 2025 16:27:29 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 54FGRRGQ023551; Thu, 15 May 2025 16:27:29 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 54FGRTDp023592; Thu, 15 May 2025 16:27:29 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id 770705015B0; Thu, 15 May 2025 21:57:28 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, bvanassche@acm.org, andersson@kernel.org, neil.armstrong@linaro.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat Subject: [PATCH V5 04/11] phy: qcom-qmp-ufs: Refactor UFS PHY reset Date: Thu, 15 May 2025 21:57:15 +0530 Message-ID: <20250515162722.6933-5-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250515162722.6933-1-quic_nitirawa@quicinc.com> References: <20250515162722.6933-1-quic_nitirawa@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: hSJWVOr0_vQJaen84Zbss4veKPkfn1J2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE2MyBTYWx0ZWRfX2Hygg0S36M6c cp68fDUWuMfyb8GfRHranvY5W+kVCNEWelumh/YQCgBeFaM1fHSbtXpj+AQAuTn+rWJjsRo0M8O BJzAzEaevTaLg7ZOmP4IhOwDFHxJ9MHgOOM6CxPIf8mLMr81BbN8jzgVgBUBP+KF4zgZQmAArhk 99bvliJCSsX4GdMVZDMounv8zuJl3VdLIaX1k4zEQ1mxl5ITQ2zIL+vmYrf61U2/W69UIen+GY4 pAnNlah8aJK+/KGzKMwVB07gcvmKOcjLuxlrPLMBxkG4vWgxQg17rFVp7ckNQ6n2PYA9EOzee1r wkPlUF8ovLpywGBi87Gi6jTZUEyOFnXXjoQN5b9rMzf0EejflVnz4sKHUwJMY8JAuk5rgyhr6tU Y5NkDsQk4haWYZWTFNgNwIBKGhQ5v8tSCjfi9aOSFaYBHW3j9q6knu8PQoB9e7IwaMPDvLgc X-Authority-Analysis: v=2.4 cv=K7UiHzWI c=1 sm=1 tr=0 ts=682615f5 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=SnDgZOM3ual17WrlNmIA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: hSJWVOr0_vQJaen84Zbss4veKPkfn1J2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_07,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 clxscore=1015 bulkscore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150163 Refactor the UFS PHY reset handling to parse the reset logic only once during initialization, instead of every resume. As part of this change, move the UFS PHY reset parsing logic from qmp_phy_power_on to the new qmp_ufs_phy_init function. Co-developed-by: Ram Kumar Dwivedi Signed-off-by: Ram Kumar Dwivedi Signed-off-by: Nitin Rawat Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 59 +++++++++++++------------ 1 file changed, 31 insertions(+), 28 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index ade8e9c4b9ae..33d238cf49aa 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1800,38 +1800,11 @@ static int qmp_ufs_com_exit(struct qmp_ufs *qmp) static int qmp_ufs_power_on(struct phy *phy) { struct qmp_ufs *qmp = phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg = qmp->cfg; int ret; dev_vdbg(qmp->dev, "Initializing QMP phy\n"); - if (cfg->no_pcs_sw_reset) { - /* - * Get UFS reset, which is delayed until now to avoid a - * circular dependency where UFS needs its PHY, but the PHY - * needs this UFS reset. - */ - if (!qmp->ufs_reset) { - qmp->ufs_reset = - devm_reset_control_get_exclusive(qmp->dev, - "ufsphy"); - - if (IS_ERR(qmp->ufs_reset)) { - ret = PTR_ERR(qmp->ufs_reset); - dev_err(qmp->dev, - "failed to get UFS reset: %d\n", - ret); - - qmp->ufs_reset = NULL; - return ret; - } - } - } - ret = qmp_ufs_com_init(qmp); - if (ret) - return ret; - - return 0; + return ret; } static int qmp_ufs_phy_calibrate(struct phy *phy) @@ -1925,7 +1898,37 @@ static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode) return 0; } +static int qmp_ufs_phy_init(struct phy *phy) +{ + struct qmp_ufs *qmp = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qmp->cfg; + int ret; + + if (!cfg->no_pcs_sw_reset) + return 0; + + /* + * Get UFS reset, which is delayed until now to avoid a + * circular dependency where UFS needs its PHY, but the PHY + * needs this UFS reset. + */ + if (!qmp->ufs_reset) { + qmp->ufs_reset = + devm_reset_control_get_exclusive(qmp->dev, "ufsphy"); + + if (IS_ERR(qmp->ufs_reset)) { + ret = PTR_ERR(qmp->ufs_reset); + dev_err(qmp->dev, "failed to get PHY reset: %d\n", ret); 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Thu, 15 May 2025 16:27:31 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 46hyvmvnp8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 15 May 2025 16:27:31 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 54FGRSJB023569; Thu, 15 May 2025 16:27:30 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 54FGRUGS023604; Thu, 15 May 2025 16:27:30 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id A8E2B5015B0; Thu, 15 May 2025 21:57:29 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, bvanassche@acm.org, andersson@kernel.org, neil.armstrong@linaro.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat Subject: [PATCH V5 05/11] phy: qcom-qmp-ufs: Remove qmp_ufs_com_init() Date: Thu, 15 May 2025 21:57:16 +0530 Message-ID: <20250515162722.6933-6-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250515162722.6933-1-quic_nitirawa@quicinc.com> References: <20250515162722.6933-1-quic_nitirawa@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE2MyBTYWx0ZWRfXz9PS8tt6SYZY /ZEzjqO0kNXFxxDrOPxepKwOE1lLV3snvyvQduP5O5YGAFqgPjObPxVYSLwASSEjj6rJpJWCDnf kYzsj7QYD3deOU7M00cmZI0s+ycARb4KCMu8lPNSazlnc92BH8Gb/ejo7qG2SUNppRY7SUw8VO0 FEkVIkA8SBa9YKaJPJj5vxIth00RW6DuxyNWQn/pCTqP7IhQU1T9ftzFWr37S52Sm2wqjPLTKag GflIj8703PuGzwAbfx+9syYpJnITfnCBPGL2uFXopnDeGfHqThH3BmWLC9XTEBQ5dGubvSgE4+h 8MgacRCuIjWwa5tlI8EG/3ndvFNbDmM+gu8nj+QU9XyJ+TllL6pRb0vDdN1zF81PSgKYTfeGr/B BTXzrlo/tNrQ+MxMLbG0I0TKPL4qZtI8Myo2TvVbS3oaGXBJWrIwrnyTN+FIjpbn++NCrRDO X-Proofpoint-ORIG-GUID: BD1qiAcQGd1ZdcVAmhmkaVzVPVL6GUgh X-Proofpoint-GUID: BD1qiAcQGd1ZdcVAmhmkaVzVPVL6GUgh X-Authority-Analysis: v=2.4 cv=IcuHWXqa c=1 sm=1 tr=0 ts=682615f6 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=qNV7bCZu-Ug6FuTvl7kA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_07,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxscore=0 adultscore=0 mlxlogscore=999 bulkscore=0 clxscore=1015 spamscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150163 The qmp_ufs_power_on() function acts as a wrapper, solely invoking qmp_ufs_com_init(). Additionally, the code within qmp_ufs_com_init() does not correspond well with its name. Therefore, to enhance the readability and eliminate unnecessary function call inline qmp_ufs_com_init() into qmp_ufs_power_on(). There is no change to the functionality. Reviewed-by: Dmitry Baryshkov Signed-off-by: Nitin Rawat --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 43 ++++++++++--------------- 1 file changed, 17 insertions(+), 26 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 33d238cf49aa..d3f9ee490a32 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1758,12 +1758,28 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); } -static int qmp_ufs_com_init(struct qmp_ufs *qmp) +static int qmp_ufs_com_exit(struct qmp_ufs *qmp) { const struct qmp_phy_cfg *cfg = qmp->cfg; + + reset_control_assert(qmp->ufs_reset); + + clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); + + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); + + return 0; +} + +static int qmp_ufs_power_on(struct phy *phy) +{ + struct qmp_ufs *qmp = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qmp->cfg; void __iomem *pcs = qmp->pcs; int ret; + dev_vdbg(qmp->dev, "Initializing QMP phy\n"); + ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); if (ret) { dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); @@ -1775,35 +1791,10 @@ static int qmp_ufs_com_init(struct qmp_ufs *qmp) goto err_disable_regulators; qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); - return 0; err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); - - return ret; -} - -static int qmp_ufs_com_exit(struct qmp_ufs *qmp) -{ - const struct qmp_phy_cfg *cfg = qmp->cfg; - - reset_control_assert(qmp->ufs_reset); - - clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); - - regulator_bulk_disable(cfg->num_vregs, qmp->vregs); - - return 0; -} - -static int qmp_ufs_power_on(struct phy *phy) -{ - struct qmp_ufs *qmp = phy_get_drvdata(phy); - int ret; - dev_vdbg(qmp->dev, "Initializing QMP phy\n"); - - ret = qmp_ufs_com_init(qmp); return ret; } From patchwork Thu May 15 16:27:17 2025 Content-Type: text/plain; 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Thu, 15 May 2025 16:27:31 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 54FGRRGS023551; Thu, 15 May 2025 16:27:31 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 54FGRV9Z023613; Thu, 15 May 2025 16:27:31 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id 793B85015B1; Thu, 15 May 2025 21:57:30 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, bvanassche@acm.org, andersson@kernel.org, neil.armstrong@linaro.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat Subject: [PATCH V5 06/11] phy: qcom-qmp-ufs: Rename qmp_ufs_power_off Date: Thu, 15 May 2025 21:57:17 +0530 Message-ID: <20250515162722.6933-7-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250515162722.6933-1-quic_nitirawa@quicinc.com> References: <20250515162722.6933-1-quic_nitirawa@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: DwhoVs59B6YED4IlvbGMxF5D9WWwxckS X-Authority-Analysis: v=2.4 cv=D8dHKuRj c=1 sm=1 tr=0 ts=682615f7 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=OtgkZb4fJjdbvehu_hcA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE2MyBTYWx0ZWRfX/g4TpB6e+P29 5y8vh764EXf7UVghV9EFmcVs2q3Mh3lrPA2S1QNnybgr3DFrWKPxFBgOIsrxifdraPLJN+BU9Z/ KBFKV/ypYXp6LXkfJn/eSZSTT/2+m/WAXvssY7EjnW7BS3pppMDrEi/F2kw+HCDnQckSx3PnwgP txx37NuZ+FrfbVUCoino++bwIoSZWMggXYKTEOwjVbSnwO55jti9uSDF4ovYLm2lvtUaWaHpgDt vDCFmqzULWdqI0UXrABMTLHys1KoSxQidXk+DQQAU2XdjdNx9rbjuvPr75OzsPan71V0w4PiEuR cAjXl0buaUoIuRg6AV4Zs3r4oOI9120IRqattJy1NQk75Ize4zOgvGEQeZfi4RIY/rDp10/wks0 Mrgbtp6lmKkA4QEZYiTzSUgKy33fHa41gKCVOCv+uowBdGK8IsbGPBbIWd1pRg1pav+fq2ns X-Proofpoint-GUID: DwhoVs59B6YED4IlvbGMxF5D9WWwxckS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_07,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 impostorscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 mlxscore=0 adultscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150163 Rename qmp_ufs_disable to qmp_ufs_power_off to better represent its functionality. Additionally, inline qmp_ufs_exit into qmp_ufs_power_off function to preserve the functionality of .power_off. There is no functional change. Signed-off-by: Nitin Rawat --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-) -- 2.48.1 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index d3f9ee490a32..a5974a1fb5bb 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1851,28 +1851,11 @@ static int qmp_ufs_power_off(struct phy *phy) qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); - return 0; -} - -static int qmp_ufs_exit(struct phy *phy) -{ - struct qmp_ufs *qmp = phy_get_drvdata(phy); - qmp_ufs_com_exit(qmp); return 0; } -static int qmp_ufs_disable(struct phy *phy) -{ - int ret; - - ret = qmp_ufs_power_off(phy); - if (ret) - return ret; - return qmp_ufs_exit(phy); -} - static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode) { struct qmp_ufs *qmp = phy_get_drvdata(phy); @@ -1921,7 +1904,7 @@ static int qmp_ufs_phy_init(struct phy *phy) static const struct phy_ops qcom_qmp_ufs_phy_ops = { .init = qmp_ufs_phy_init, .power_on = qmp_ufs_power_on, - .power_off = qmp_ufs_disable, + .power_off = qmp_ufs_power_off, .calibrate = qmp_ufs_phy_calibrate, .set_mode = qmp_ufs_set_mode, .owner = THIS_MODULE, From patchwork Thu May 15 16:27:18 2025 Content-Type: text/plain; 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Thu, 15 May 2025 16:27:32 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 54FGRWpm023630; Thu, 15 May 2025 16:27:32 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 54FGRV25023627; Thu, 15 May 2025 16:27:32 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id 5F84C5015B0; Thu, 15 May 2025 21:57:31 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, bvanassche@acm.org, andersson@kernel.org, neil.armstrong@linaro.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat Subject: [PATCH V5 07/11] phy: qcom-qmp-ufs: Remove qmp_ufs_exit() and Inline qmp_ufs_com_exit() Date: Thu, 15 May 2025 21:57:18 +0530 Message-ID: <20250515162722.6933-8-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250515162722.6933-1-quic_nitirawa@quicinc.com> References: <20250515162722.6933-1-quic_nitirawa@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: YV3526Iemkh1JHtrM4WA05ZgN9jyQ6Xu X-Proofpoint-ORIG-GUID: YV3526Iemkh1JHtrM4WA05ZgN9jyQ6Xu X-Authority-Analysis: v=2.4 cv=cO7gskeN c=1 sm=1 tr=0 ts=682615f8 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=ckjLh8WlKRlJn9_E0bwA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE2MyBTYWx0ZWRfX3xbxmuWBhgE5 Vkx1dcurBND8VQfIKLYMU/MjMMtfZqK5wWwAQQlv+kexlfJw3h0I0mU23XuDXoFDmuJ2TN07lGo eac2reRWR0yee5OS/wzLI3OOL28Kl1n3xolZf9AOvWh1unZ68esJm+lQIL5iIj+FLcTeoYK1AMn U3e0Biqjgff4oThl0RMbtd++cRwsXbJw0HfbRcLQS8nmFkNRJ9l9zvbzO95cI6XT7jl1KuYb4s3 aFBoMPQYMtl8vbY6emJc1gGkbpuCOH1z4JSm/DjTUKX6erHT71KVKTtAyjn/QhVlir7/5ipLGuh /JCw9sOuuT+FVvygLFnrJWB01SOg0hzOZ3KBw+yBaMlw22QI/lLPccfFNq6EmxUgHRpvvJx8XMy itE125aN4BVPulJ4RrzkWFFiu3hgx947anFZTxENTqLFIdO0wkgt1sCfzjBRArqY4aXqniQg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_07,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 malwarescore=0 impostorscore=0 clxscore=1015 priorityscore=1501 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150163 qmp_ufs_exit() is a wrapper function. It only calls qmp_ufs_com_exit(). Remove it to simplify the ufs phy driver. Additonally partial Inline(dropping the reset assert) qmp_ufs_com_exit into qmp_ufs_power_off function to avoid unnecessary function call. Signed-off-by: Nitin Rawat Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index a5974a1fb5bb..fca47e5e8bf0 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1758,19 +1758,6 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); } -static int qmp_ufs_com_exit(struct qmp_ufs *qmp) -{ - const struct qmp_phy_cfg *cfg = qmp->cfg; - - reset_control_assert(qmp->ufs_reset); - - clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); - - regulator_bulk_disable(cfg->num_vregs, qmp->vregs); - - return 0; -} - static int qmp_ufs_power_on(struct phy *phy) { struct qmp_ufs *qmp = phy_get_drvdata(phy); @@ -1851,7 +1838,11 @@ static int qmp_ufs_power_off(struct phy *phy) qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); - qmp_ufs_com_exit(qmp); + /* Turn off all the phy clocks */ + clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); + + /* Turn off all the phy rails */ + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); return 0; } From patchwork Thu May 15 16:27:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 890252 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F0E12253EB; Thu, 15 May 2025 16:27:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747326477; cv=none; b=S3XIZEEAO4LDuIQ/WRaEWdXkBFuMZ9Xs+RmiLGixm4oPSzmWEvjF0K2g32TVNm7ZLNDSU5fi0RLd3dZpf5K7x3Q+xXE8CvDGuLF1d1dDVfJno59x0ShxoEzJPsPKqBwrZsZwpgnHlZK3nd5M3x/Puzb4oN07cBRwIwpIJ0CfHLE= ARC-Message-Signature: i=1; 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Thu, 15 May 2025 16:27:33 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 46hyvmvnpt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 15 May 2025 16:27:33 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 54FGRXFP023644; Thu, 15 May 2025 16:27:33 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 54FGRWdl023642; Thu, 15 May 2025 16:27:33 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id 49C8C5015B0; Thu, 15 May 2025 21:57:32 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, bvanassche@acm.org, andersson@kernel.org, neil.armstrong@linaro.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat Subject: [PATCH V5 08/11] phy: qcom-qmp-ufs: refactor qmp_ufs_power_off Date: Thu, 15 May 2025 21:57:19 +0530 Message-ID: <20250515162722.6933-9-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250515162722.6933-1-quic_nitirawa@quicinc.com> References: <20250515162722.6933-1-quic_nitirawa@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE2MiBTYWx0ZWRfX55MSJAFPoPt3 aCY30UVyOap2FHslkszuk1hD4WNZwsZhPTlUQL/pQiUsfuPxky9PiFZaQBcibWWJr7GDD/nWd3O S2x3FKe4MjFS9waoxJSp6E3R6eNRUrUjtDCTNnySwf3+CrG0aHboSij/5Np8k9QCZaP5EQctTmv QRhK3zhDH4RkR2jSePR0mYKEWNn1e6djWT5SAUmx+Fie+0ifYFxUFlpFGnvZ4QEpjooL8hSVpzT bdWiPnKoWGoEuO2tWRUH5wgMaFYs/S6djzevcOr0sq5KSDNEQKOAcPVFtOMwgcofECZ0LWB9+0V rwbK6aZsa7IGTd9J8Pb3XCp9Ji+akpnY6EjqenyhWYNSvnBj30M5N5uBQhYff5J3KIa+fWXMpMD 0VO6vuF5nrqdXdBEfECeb8ZE3iP+UCx0PA8BCfEoiqy+AcVEtDoJ/xSFlfGmT1HEzvp0XJm9 X-Authority-Analysis: v=2.4 cv=G5scE8k5 c=1 sm=1 tr=0 ts=682615f9 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=0NjA6WJkZe3NLfXfqlsA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: XrHuWMRx3wjcNz0n7UuXwR8t7jw8W1n- X-Proofpoint-ORIG-GUID: XrHuWMRx3wjcNz0n7UuXwR8t7jw8W1n- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_07,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 clxscore=1015 phishscore=0 bulkscore=0 suspectscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 malwarescore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150162 In qmp_ufs_power_off, the PHY is already powered down by asserting QPHY_PCS_POWER_DOWN_CONTROL. Therefore, additional phy_reset and stopping SerDes are unnecessary. Also this approach does not align with the phy HW programming guide. Thus, refactor qmp_ufs_power_off to remove the phy_reset and stop SerDes calls to simplify the code and ensure alignment with the PHY HW programming guide. Signed-off-by: Nitin Rawat Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index fca47e5e8bf0..abfebf0435d8 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1827,13 +1827,6 @@ static int qmp_ufs_power_off(struct phy *phy) struct qmp_ufs *qmp = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qmp->cfg; - /* PHY reset */ - if (!cfg->no_pcs_sw_reset) - qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); - - /* stop SerDes */ - qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START); - /* Put PHY into POWER DOWN state: active low */ qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); From patchwork Thu May 15 16:27:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 890251 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF2CE22C32D; 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Thu, 15 May 2025 16:27:37 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 54FGRT6L023598; Thu, 15 May 2025 16:27:34 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 46hyvmvnpy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 15 May 2025 16:27:34 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 54FGRXgH023658; Thu, 15 May 2025 16:27:33 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 54FGRXiN023655; Thu, 15 May 2025 16:27:33 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id 22AA15015B1; Thu, 15 May 2025 21:57:33 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, bvanassche@acm.org, andersson@kernel.org, neil.armstrong@linaro.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat Subject: [PATCH V5 09/11] scsi: ufs: qcom : Refactor phy_power_on/off calls Date: Thu, 15 May 2025 21:57:20 +0530 Message-ID: <20250515162722.6933-10-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250515162722.6933-1-quic_nitirawa@quicinc.com> References: <20250515162722.6933-1-quic_nitirawa@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE2MiBTYWx0ZWRfX5nxZOBpYAuF8 JMpi5OPtR6JgOuj4I1KQ0m9KJaMP6CWBZDAqFTBjAqixx9I1PCYnbbv6hRPURNTF7ZwfX7F8B99 Gg+XIwJHa1IK22cxrJS/qj5uQCnKrFEpJ+5DRMBSVGWz9gRZbFvaC9zvIMlCUN/Gyin+V78t/QE RJ8wWqH8eNf5oXjD/iqEjAlLGK9zNddTELzvTkjJVn3fjq3LwmLVVAIR2OdzeeZQNFlK7pAZTey zHmLfwUva6PIv2VisoNWXk4VAF4Okj7BYr+EbfkBr587TCfWRT7JHVdErixkmf3Y0VOO2S5EBxG M1TA4DtNM3MP0g3bAMJ2sMwEXf/Uky8HKBCWw6hHVrxekH3gstPz5zpuhFnbzQ0GBCEkThB9zyr TKeHYnuKbyKDcdzFZCY2Koh9QchD+uHZecI9Aa5Iqb2f7kZ8J/vsYxTOO8wHeUHKUY4bf2Du X-Authority-Analysis: v=2.4 cv=G5scE8k5 c=1 sm=1 tr=0 ts=682615f9 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=ylzO3PbLlNu0Q4qtwUgA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: va8ZlpkUkxKZwIvHRw-ot5mxEwNygFQx X-Proofpoint-ORIG-GUID: va8ZlpkUkxKZwIvHRw-ot5mxEwNygFQx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_07,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 clxscore=1015 phishscore=0 bulkscore=0 suspectscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 malwarescore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150162 Commit 3f6d1767b1a0 ("phy: ufs-qcom: Refactor all init steps into phy_poweron") removes the phy_power_on/off from ufs_qcom_setup_clocks to suspend/resume func. To have a better power saving, remove the phy_power_on/off calls from resume/suspend path and put them back to ufs_qcom_setup_clocks, so that PHY regulators & clks can be turned on/off along with UFS's clocks. Since phy phy_power_on is separated out from phy calibrate, make separate calls to phy_power_on and phy_calibrate calls from ufs qcom driver. Co-developed-by: Can Guo Signed-off-by: Can Guo Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 61 ++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 32 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 23b4fc84dc8c..3ee4ab90dfba 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -697,26 +697,17 @@ static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, enum ufs_notify_change_status status) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - struct phy *phy = host->generic_phy; if (status == PRE_CHANGE) return 0; - if (ufs_qcom_is_link_off(hba)) { - /* - * Disable the tx/rx lane symbol clocks before PHY is - * powered down as the PLL source should be disabled - * after downstream clocks are disabled. - */ + if (!ufs_qcom_is_link_active(hba)) ufs_qcom_disable_lane_clks(host); - phy_power_off(phy); - /* reset the connected UFS device during power down */ - ufs_qcom_device_reset_ctrl(hba, true); - } else if (!ufs_qcom_is_link_active(hba)) { - ufs_qcom_disable_lane_clks(host); - } + /* reset the connected UFS device during power down */ + if (ufs_qcom_is_link_off(hba) && host->device_reset) + ufs_qcom_device_reset_ctrl(hba, true); return ufs_qcom_ice_suspend(host); } @@ -724,26 +715,11 @@ static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - struct phy *phy = host->generic_phy; int err; - if (ufs_qcom_is_link_off(hba)) { - err = phy_power_on(phy); - if (err) { - dev_err(hba->dev, "%s: failed PHY power on: %d\n", - __func__, err); - return err; - } - - err = ufs_qcom_enable_lane_clks(host); - if (err) - return err; - - } else if (!ufs_qcom_is_link_active(hba)) { - err = ufs_qcom_enable_lane_clks(host); - if (err) - return err; - } + err = ufs_qcom_enable_lane_clks(host); + if (err) + return err; return ufs_qcom_ice_resume(host); } @@ -1133,12 +1109,20 @@ static void ufs_qcom_set_caps(struct ufs_hba *hba) * @on: If true, enable clocks else disable them. * @status: PRE_CHANGE or POST_CHANGE notify * + * There are certain clocks which comes from the PHY so it needs + * to be managed together along with controller clocks which also + * provides a better power saving. Hence keep phy_power_off/on calls + * in ufs_qcom_setup_clocks, so that PHY's regulators & clks can be + * turned on/off along with UFS's clocks. + * * Return: 0 on success, non-zero on failure. */ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, enum ufs_notify_change_status status) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct phy *phy = host->generic_phy; + int err; /* * In case ufs_qcom_init() is not yet done, simply ignore. @@ -1157,10 +1141,22 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, /* disable device ref_clk */ ufs_qcom_dev_ref_clk_ctrl(host, false); } + + err = phy_power_off(phy); + if (err) { + dev_err(hba->dev, "phy power off failed, ret=%d\n", err); + return err; + } } break; case POST_CHANGE: if (on) { + err = phy_power_on(phy); + if (err) { + dev_err(hba->dev, "phy power on failed, ret = %d\n", err); + return err; + } + /* enable the device ref clock for HS mode*/ if (ufshcd_is_hs_mode(&hba->pwr_info)) ufs_qcom_dev_ref_clk_ctrl(host, true); @@ -1343,9 +1339,10 @@ static int ufs_qcom_init(struct ufs_hba *hba) static void ufs_qcom_exit(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct phy *phy = host->generic_phy; ufs_qcom_disable_lane_clks(host); - phy_power_off(host->generic_phy); + phy_power_off(phy); phy_exit(host->generic_phy); } From patchwork Thu May 15 16:27:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 890645 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6689822B5AD; Thu, 15 May 2025 16:27:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747326480; cv=none; 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For instance, ufs_qcom_power_up_sequence can be called multiple times from ufshcd_link_startup as part of ufshcd_hba_enable call for each link startup retries(max retries =3), causing the PHY reference count to increase and leading to inconsistent phy behavior. Similarly, there can be scenarios where phy_power_on or phy_power_off might be called directly from the UFS controller driver when the PHY is already powered on or off respectiely, causing similar issues. To fix this, introduce ufs_qcom_phy_power_on and ufs_qcom_phy_power_off wrappers for phy_power_on and phy_power_off. These wrappers will use an is_phy_pwr_on flag to check if the PHY is already powered on or off, avoiding redundant calls. Protect the is_phy_pwr_on flag with a mutex to ensure safe usage and prevent race conditions. Co-developed-by: Can Guo Signed-off-by: Can Guo Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 44 +++++++++++++++++++++++++++++++------ drivers/ufs/host/ufs-qcom.h | 4 ++++ 2 files changed, 41 insertions(+), 7 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 3ee4ab90dfba..583db910efd4 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -479,6 +479,38 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) return UFS_HS_G3; } +static int ufs_qcom_phy_power_on(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct phy *phy = host->generic_phy; + int ret = 0; + + guard(mutex)(&host->phy_mutex); + if (!host->is_phy_pwr_on) { + ret = phy_power_on(phy); + if (!ret) + host->is_phy_pwr_on = true; + } + + return ret; +} + +static int ufs_qcom_phy_power_off(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct phy *phy = host->generic_phy; + int ret = 0; + + guard(mutex)(&host->phy_mutex); + if (host->is_phy_pwr_on) { + ret = phy_power_off(phy); + if (!ret) + host->is_phy_pwr_on = false; + } + + return ret; +} + static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); @@ -507,7 +539,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) return ret; if (phy->power_count) { - phy_power_off(phy); + ufs_qcom_phy_power_off(hba); phy_exit(phy); } @@ -524,7 +556,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) goto out_disable_phy; /* power on phy - start serdes and phy's power and clocks */ - ret = phy_power_on(phy); + ret = ufs_qcom_phy_power_on(hba); if (ret) { dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", __func__, ret); @@ -1121,7 +1153,6 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, enum ufs_notify_change_status status) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - struct phy *phy = host->generic_phy; int err; /* @@ -1142,7 +1173,7 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, ufs_qcom_dev_ref_clk_ctrl(host, false); } - err = phy_power_off(phy); + err = ufs_qcom_phy_power_off(hba); if (err) { dev_err(hba->dev, "phy power off failed, ret=%d\n", err); return err; @@ -1151,7 +1182,7 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, break; case POST_CHANGE: if (on) { - err = phy_power_on(phy); + err = ufs_qcom_phy_power_on(hba); if (err) { dev_err(hba->dev, "phy power on failed, ret = %d\n", err); return err; @@ -1339,10 +1370,9 @@ static int ufs_qcom_init(struct ufs_hba *hba) static void ufs_qcom_exit(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - struct phy *phy = host->generic_phy; ufs_qcom_disable_lane_clks(host); - phy_power_off(phy); + ufs_qcom_phy_power_off(hba); phy_exit(host->generic_phy); } diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 0a5cfc2dd4f7..f51b774e17be 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -281,6 +281,10 @@ struct ufs_qcom_host { u32 phy_gear; bool esi_enabled; + /* flag to check if phy is powered on */ + bool is_phy_pwr_on; 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[5.146763] phy phy-1d80000.phy.0: phy_power_on was called before phy_init Fixes: 7bac65687510 ("scsi: ufs: qcom: Power off the PHY if it was already powered on in ufs_qcom_power_up_sequence()") Signed-off-by: Nitin Rawat Reviewed-by: Konrad Dybcio --- drivers/ufs/host/ufs-qcom.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 583db910efd4..bd7f65500db7 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -540,7 +540,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) if (phy->power_count) { ufs_qcom_phy_power_off(hba); - phy_exit(phy); } /* phy initialization - calibrate the phy */