From patchwork Thu May 15 19:58:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Connor Abbott X-Patchwork-Id: 890248 Received: from mail-qk1-f175.google.com (mail-qk1-f175.google.com [209.85.222.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B1B2296FCB for ; Thu, 15 May 2025 19:59:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.222.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747339181; cv=none; b=q8XQ2BmCI09AIluRBENzkJ5xOpYAqriKX/gHpkLiCjHEPcxC1hgHzf6NPZg66V+hWxaR8WPUvepxLkZAYqIVuMkmwr8E+SQI0ogGLVDdRXZ2PfLTzYtE4rkg8irD+h4iEq3ubBStYajpbBXJjNlPWpFoqo13VUOkPGtnxKkEhfY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747339181; c=relaxed/simple; bh=DPKRVjaqGjt+UvV8ZZCM0hAEA0xW5F7yYBkPh+fJ4X4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Fz60bjrSle6twrVe+XyIqyM7G80Ty2nvyY4Fx3c4XNTtD4SR1N3fS71zRiYvGvRn+s1K72FiPCOEMwR22EHD5988+EhsbUKqVAhe8pIAlzB9h34cMr/CGUU/94qlLPlxc1wwAuf+YYompLtEhgF2Vp1RSBHKnYUnjCxTuLUdczc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=k7XwqUKX; arc=none smtp.client-ip=209.85.222.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="k7XwqUKX" Received: by mail-qk1-f175.google.com with SMTP id af79cd13be357-7c57f2f5a1bso15891185a.1 for ; Thu, 15 May 2025 12:59:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1747339178; x=1747943978; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qWJZCHLwo4+rNxVq1K/n30vdDm3CIQkELPwI2pLPS/o=; b=k7XwqUKX7GHUjczxYsXnJJBqTeWZ4Me+jNtQD1aszORXYMRHoAiZFW1fRyf36MHSTF mxCnlhNEm8v78t/CjpLNwfBx1LOrdyqfyh7k+bqH/VKuZGSGY5/wJZJ81P2z2eobvn4t X6VlJvjvqpXf6tOI3pTW9iEMHPjMGHlw6WdoW9EUhzmF392F+qzTdAs/8VLuLn6jNpxa RHRsh37MFlWb5U5t4I6j+2wToKS+XlWd1ddOgU12x3OpGakuOqViVxrWPvODHtRZJPhO huaS8UE8579mw5UbtS6P5ymFrP0rksR/hwQXIg44LH5luhFDs+87J2h30dGFeomyp8Ye UXww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747339178; x=1747943978; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qWJZCHLwo4+rNxVq1K/n30vdDm3CIQkELPwI2pLPS/o=; b=boSiEPuvQYoljhPlYRD/6NjymOdh+E/WRM0j2KgmhKmUfmM1EadpfJUtGihKzB+3OF NaiXW4mc23N64WqgAe0oP7KO2n2PcJRJFROrfmXlvKObJq2x7X8ERAGtR8OxD8OmaoZY 2hw0rmc+Hhu7ERVVXwFij+Zdp0zGw+l+iPD2wN4mL43zs512IK6qNUcvt0C8rU1/qEva nIqMP5yA5dJuhE7uNC3e9hEKfz4VFGD/j58HGOMC9E0Eanzjlu2o8sbdv0ZMUM+Ke7h+ IsacdGfy8HlpJUFf6m3yTojMYPL5oquLIHL7du1sOSSMqeHa1W3HwiP8NBUx6LnlOHxO tmJA== X-Forwarded-Encrypted: i=1; AJvYcCWlTH+Sj44DZc29IjNKWgyAvg1U1g8Z5W9iVgsJYqVntOtmJ/G/3YlgijYoMV/j8OIw4zgFfk1yRR+C/ir4@vger.kernel.org X-Gm-Message-State: AOJu0YxvmrsDasEYYvqrG0zQj1H9Z94l7WM7MJTDGEgpxpBrM5bhR301 oDbhgQdGYtfDsQpQCH5mjQQ7ItXfyfMzCmCFI7pvhYYTjZrrcfe64aV6 X-Gm-Gg: ASbGncuXWQgeaYxlXXd6ewDg8KQzdI1ZvukztUhfrpsQXNa+rTBh/vmYCwFkwj8gf6l gT3d9sm8E6rTix3M+as6aj96O3xRPbuE2qGFe9I7ixPNmMxfTi6X1hHjtXRfJDuIWR7mZlEcRyv d79uJOuClJL7LBdRw4FDsJi8fZ3pb9waz2ozq6ruxIS0dGZEC5SHzLYRDgxoCabwyq6OI2cqUi2 7hk3TaWmZRkYMUPm031m6Uf/Po5L+LLA8a9yFUeULM7AaY7SN+pK9HtZTxAOGCi5F9CFfG7W3kv pUMSQ0toBXdXSlezwskXqQf08LjQYwB87VwUcBxtVFN8Xec+Y7J8h2epGlteIQUOL9FucuHwCGi lT5KuTE05L2X6m1qUlSw= X-Google-Smtp-Source: AGHT+IH82TQ9c8cVYqaXjsAhzpScTuQetKQyv8EkyvQLwXx7nU7GdytaDPOdEesc7oYyyCkeN49+/Q== X-Received: by 2002:ac8:5951:0:b0:475:876:ac3d with SMTP id d75a77b69052e-494ae41e3a4mr3460681cf.13.1747339178066; Thu, 15 May 2025 12:59:38 -0700 (PDT) Received: from [192.168.124.1] (syn-067-243-142-039.res.spectrum.com. [67.243.142.39]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-494ae4fd80bsm1957231cf.56.2025.05.15.12.59.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 12:59:37 -0700 (PDT) From: Connor Abbott Date: Thu, 15 May 2025 15:58:43 -0400 Subject: [PATCH v6 1/7] iommu/arm-smmu-qcom: Enable threaded IRQ for Adreno SMMUv2/MMU500 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250515-msm-gpu-fault-fixes-next-v6-1-4fe2a583a878@gmail.com> References: <20250515-msm-gpu-fault-fixes-next-v6-0-4fe2a583a878@gmail.com> In-Reply-To: <20250515-msm-gpu-fault-fixes-next-v6-0-4fe2a583a878@gmail.com> To: Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747339176; l=2173; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=DPKRVjaqGjt+UvV8ZZCM0hAEA0xW5F7yYBkPh+fJ4X4=; b=62Z0w3hpPUoa4KOiyVuNO04DfGNn3v70J7ZnmSCozzrwREkvpBQansvHOQaEZoUFL+zftDl/L uXXn7xCS28bAYrzU5iTGeMySBdN12STsv+/vLopzuc9rlGmgu1VXpvp X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= The recommended flow for stall-on-fault in SMMUv2 is the following: 1. Resolve the fault. 2. Write to FSR to clear the fault bits. 3. Write RESUME to retry or fail the transaction. MMU500 is designed with this sequence in mind. For example, experimentally we have seen on MMU500 that writing RESUME does not clear FSR.SS unless the original fault is cleared in FSR, so 2 must come before 3. FSR.SS is allowed to signal a fault (and does on MMU500) so that if we try to do 2 -> 1 -> 3 (while exiting from the fault handler after 2) we can get duplicate faults without hacks to disable interrupts. However, resolving the fault typically requires lengthy operations that can stall, like bringing in pages from disk. The only current user, drm/msm, dumps GPU state before failing the transaction which indeed can stall. Therefore, from now on we will require implementations that want to use stall-on-fault to also enable threaded IRQs. Do that with the Adreno MMU implementations. Signed-off-by: Connor Abbott --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 6372f3e25c4bc24cb52f9233095170e8aa510a53..2b21b7208bc7b439d69e36ca678acd2eacbd5b85 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -468,6 +468,7 @@ static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = { .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, .write_sctlr = qcom_adreno_smmu_write_sctlr, .tlb_sync = qcom_smmu_tlb_sync, + .context_fault_needs_threaded_irq = true, }; static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = { @@ -477,6 +478,7 @@ static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = { .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, .write_sctlr = qcom_adreno_smmu_write_sctlr, .tlb_sync = qcom_smmu_tlb_sync, + .context_fault_needs_threaded_irq = true, }; static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, From patchwork Thu May 15 19:58:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Connor Abbott X-Patchwork-Id: 890247 Received: from mail-qk1-f178.google.com (mail-qk1-f178.google.com [209.85.222.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7C9A296FCB for ; Thu, 15 May 2025 19:59:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.222.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747339183; cv=none; b=nCPG6qXxlQHydKqXur1AtqO2ev1ToMhPSmxvW9KuXF6vi+VKwOzOGy9Iw72JTMkzFsfKe2k2icyq/Hv1DwyPtb4u3N7ESHOYi1CCEAoJ7/fKO/iUnaeacWOTiVvfppL67CahEDKCn9l2sr5dKL25eFZXCis6VIqI2Zo2+YKVrGU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747339183; c=relaxed/simple; bh=NuuNOSzcg6T6eP7lLDMW2wQqpv+M7MyGEuNFao145fo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JSWEJ3JeL6b+vfl+F/c+o7gZ3jkL/CS8r5xZhY09tQn5S1PYpyKuseDoG3nV8S5xHbibD08iX4CuYETAA4DhqqbaOZXEjCS8OoOhl+watgw3uMq5cgQSr/hlQNAIvY/rnv0PsmDu5XcAHJYs8/8/9m0PogeMITXqubhxm7Cs0f8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=AhbYZCPM; arc=none smtp.client-ip=209.85.222.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="AhbYZCPM" Received: by mail-qk1-f178.google.com with SMTP id af79cd13be357-7c5a3334fddso23443085a.1 for ; Thu, 15 May 2025 12:59:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1747339181; x=1747943981; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=aRX2mmgMKg0kWmEalfWfPxyKsLjxoohp0lPvLbYN2U4=; b=AhbYZCPMJ8jfK8Wk3gMLcAvsbBGER5OoRpKYvezpFHbSOewoaY2nMEjUHWDMRtvRpU 5sgp8ikCqey1uXaSQOGsugitxk3H9M6ExH338SbkWFgrw1SSRAhSHKUXRg3MKVOM2YXs rWi7dDmnBvExJm6jG5E1jmn1GpCn6DpzmSVmKl6Adi86TOnWa8UZQb3Iv1zPMpB3n6iR /jLjH7HOsco8YsladjMSXTDWy40FTemOWCh8wIyMeJR52DSehPiBwzJTCLZVGXDZlyD1 IvsTTsB46lconTWKbECfchSFt+8SaDM5NJu+Bf9Q2lp4KCqoA30AMhzSD+bWKXlFF5rv JoAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747339181; x=1747943981; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aRX2mmgMKg0kWmEalfWfPxyKsLjxoohp0lPvLbYN2U4=; b=VNm2kGNeB3kbbnDvGmI8DWhoPcSrvfsuKXfQLli+/RKB1bxpKXbJehkKm4F+lv1f8C wOErBLybCwFnx6hhPU4Cr6d619vcCY3n+w+caruB+8ULLceBghxWyMqeN3ctw1xjNaBj cZpB9dKtzI3JT+Z4I+MnwjHzrnJMlhFjJYpJPEJsh3aZxIcvfaMJv3GoabJKpLVhTXZD 5rv52caNAv4KgchpSyOwXQvYejVNh2F71r2Nh4iAkwONN73MNvHm4HcX+iL5gDiJ3gg6 xuu46Ob4RXjw/TJVC97OqzAItj6O92S72+Net6BoO0E2xii09youlXgvI51JC3T2kQPX j0SA== X-Forwarded-Encrypted: i=1; AJvYcCWfk7lOTB4B7ozfo8I9CgYVtDZJRQVIAYEjZ1+EIC6VAngaVpp1IHwqzWJpg06hLXQ2mONmkWtrb88m5Jub@vger.kernel.org X-Gm-Message-State: AOJu0YxRhOJb9fUiEIulUNN5yDAtQ3pJDoaCB4tMZOw8AmkTFTutwNmj LLw/rvZ09Vh9po/NRBHnp/oodij3nCofD0Npg196kGCWyrc/udVU12y3 X-Gm-Gg: ASbGncunSFBCCCPv5RMuByaSVobjN/RKPf4Ato+DHXuw2fG0dhkiiPRGUdGhRRC3oop u76m9y1L5qwqoeamYrWV2lXlceUmJ1fXAwof7goOx6bcEQDJhdO8RuNXg7Ak5h5IU3LFn+LXIY7 9Gx2r15rMJP/JRtPPfcsEHyOnINQnlc+EfOZE4MbOI8SjmM61Rv6IIyKwcHc2ZUBBKDMHCCRhpE NCjBR36SV8yOhCsT8q5MEbllbMviVpv4aqu9cSVwr2/vPYZvtrO5ML68kXWC6EWT0/rWfQLlNpe KVuKwF59KYEvrFs8RYJaZLA45CcBWAxiriwZJdNsuVso15SPiGuBNrBi6+tItrc4TW9GDluZPY5 XpyijAvh9hw0bQ0ja5TI= X-Google-Smtp-Source: AGHT+IFDWp8u+QjgmXSWCzrAKUKVyvuRDbgutIyJGTYJ63yX5WXLYpLuZEG+9WHmxaOHRSYMoJ0INw== X-Received: by 2002:a05:622a:1306:b0:474:e664:691b with SMTP id d75a77b69052e-494ae37764emr4557401cf.8.1747339180611; Thu, 15 May 2025 12:59:40 -0700 (PDT) Received: from [192.168.124.1] (syn-067-243-142-039.res.spectrum.com. [67.243.142.39]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-494ae4fd80bsm1957231cf.56.2025.05.15.12.59.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 12:59:40 -0700 (PDT) From: Connor Abbott Date: Thu, 15 May 2025 15:58:45 -0400 Subject: [PATCH v6 3/7] iommu/arm-smmu-qcom: Make set_stall work when the device is on Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250515-msm-gpu-fault-fixes-next-v6-3-4fe2a583a878@gmail.com> References: <20250515-msm-gpu-fault-fixes-next-v6-0-4fe2a583a878@gmail.com> In-Reply-To: <20250515-msm-gpu-fault-fixes-next-v6-0-4fe2a583a878@gmail.com> To: Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747339176; l=3349; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=NuuNOSzcg6T6eP7lLDMW2wQqpv+M7MyGEuNFao145fo=; b=G8f7cSFchFa6Ol5NZmbPn25aQKQkCTssSAZn+8lrwlFIh1x96h6u6Eq2OveCkRVCprigujkFM gF8bATUpx0qDSrjfTkYolsLQIxjAjr3aU2RLL0cOv0MsHcy5zrhpUHQ X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= Up until now we have only called the set_stall callback during initialization when the device is off. But we will soon start calling it to temporarily disable stall-on-fault when the device is on, so handle that by checking if the device is on and writing SCTLR. Signed-off-by: Connor Abbott Reviewed-by: Rob Clark --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 33 +++++++++++++++++++++++++++--- include/linux/adreno-smmu-priv.h | 6 +++--- 2 files changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index d71404ad90376b2c258d67e07ec380674961a429..98927be42bd1af25dcc3f667cb75d250a320c447 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -78,12 +78,39 @@ static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled) { struct arm_smmu_domain *smmu_domain = (void *)cookie; struct arm_smmu_cfg *cfg = &smmu_domain->cfg; - struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu); + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); + u32 mask = BIT(cfg->cbndx); + bool stall_changed = !!(qsmmu->stall_enabled & mask) != enabled; + unsigned long flags; if (enabled) - qsmmu->stall_enabled |= BIT(cfg->cbndx); + qsmmu->stall_enabled |= mask; else - qsmmu->stall_enabled &= ~BIT(cfg->cbndx); + qsmmu->stall_enabled &= ~mask; + + /* + * If the device is on and we changed the setting, update the register. + * The spec pseudocode says that CFCFG is resampled after a fault, and + * we believe that no implementations cache it in the TLB, so it should + * be safe to change it without a TLB invalidation. + */ + if (stall_changed && pm_runtime_get_if_active(smmu->dev) > 0) { + spin_lock_irqsave(&smmu_domain->cb_lock, flags); + + u32 reg = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_SCTLR); + + if (enabled) + reg |= ARM_SMMU_SCTLR_CFCFG; + else + reg &= ~ARM_SMMU_SCTLR_CFCFG; + + arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_SCTLR, reg); + + spin_unlock_irqrestore(&smmu_domain->cb_lock, flags); + + pm_runtime_put_autosuspend(smmu->dev); + } } #define QCOM_ADRENO_SMMU_GPU_SID 0 diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h index c637e0997f6d8eedcc42a03a9d303700f62f8cf2..8ed94fb39e6ec6a3d8e6fabe61ff142682f1764c 100644 --- a/include/linux/adreno-smmu-priv.h +++ b/include/linux/adreno-smmu-priv.h @@ -45,9 +45,9 @@ struct adreno_smmu_fault_info { * TTBR0 translation is enabled with the specified cfg * @get_fault_info: Called by the GPU fault handler to get information about * the fault - * @set_stall: Configure whether stall on fault (CFCFG) is enabled. Call - * before set_ttbr0_cfg(). If stalling on fault is enabled, - * the GPU driver must call resume_translation() + * @set_stall: Configure whether stall on fault (CFCFG) is enabled. If + * stalling on fault is enabled, the GPU driver must call + * resume_translation() * @resume_translation: Resume translation after a fault * * From patchwork Thu May 15 19:58:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Connor Abbott X-Patchwork-Id: 890246 Received: from mail-qv1-f44.google.com (mail-qv1-f44.google.com [209.85.219.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 962DD29B23B for ; Thu, 15 May 2025 19:59:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747339186; cv=none; b=rLtTMAf1SJO46cAo4AnnN+TOQBvHB2dhH03nyEUFimiZ2Y/nZXw40Buu1Xcb3Ztr0PQ7vklSNKWGO1dVTPSH+eqBQVL68738F5xR7MEO7Rjvhr/HXK+9T3C2v3rxlUTG9JF4XSTiAwmepKKjURETPApnVyKqRHkPFL9twVbiir0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747339186; c=relaxed/simple; bh=Qq5k1GBVvpOoe3vbf7lHYuU1s8ow91pqey8KnhArgxI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EiB9sbv+/RTAj3ytw3lcHFMOkFxYZ/84CLxFIOHPSXTXMRlBXXLJkgT6Tz2axD0R/rA38hQ53wiE8AQkVCAc034FgHqGP+9GYMTN5M4i5CZRy9MnevuvFi0TJWHEwXxabgBaOggFhlt6Ith5HsC1JLv14tjuP0wQ/th+VNhDpoI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=PNPDlYyZ; arc=none smtp.client-ip=209.85.219.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PNPDlYyZ" Received: by mail-qv1-f44.google.com with SMTP id 6a1803df08f44-6f53e612fa1so2109596d6.1 for ; Thu, 15 May 2025 12:59:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1747339183; x=1747943983; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=CXRAlEAkp/v2H222njYW3lOGT6rTudruLVTCXUshl+c=; b=PNPDlYyZfZI3mGyWMKE8+11lafp3o9T37BOVZYls0tMJMuvmpyFDPolj+lakeZiQan 1H9/OnpylnD7W96z7gRKx2nUdgcODzIUpyiXGOJK9MK+MsfMvZV3GwbdnFm8RWqGNzVy Jr8TtEJXi0mfoBSnXDNgfUoE81lwE49lz27gMwtsAJuafeL8EGNQ1ru+hGgWO6xBeon5 zZTQrQknylfCRVHDNsfhw4zjUnM2GhhSWn5K0kfeUus3hHo6+S8mXwdj/7OLJjxm0rfo op1Sc8hEe9zxmgZKvAz+cTIH01JA9ZcjhcrrwvEJ2bjuaEztAYlgQkHrr9CRMfni8xII 5aRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747339183; x=1747943983; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CXRAlEAkp/v2H222njYW3lOGT6rTudruLVTCXUshl+c=; b=VQv/uA4t/WFiGyx5mUkCAsh4W9cCJb+HOkRhavlXYqrPhbYTXmuAlNQOgeM3TuvUvx iA3z6szgbym2NYIdiRs9ajO07FNHesXleDvsc8cLSKU7c8CmoDlLoR2lNUH41Zexd4Kl hTtUoOBxgqrlgTKGXRwQFOokG2E4K2zUxeI2SVq36/Jb9ayIypCC4W6sTL+SXMfxWIw6 PYAVoRuZNYN0QzBrcKhRORGkV1J5tjcge2qT4jM+fX7a5PxjUe3DgvC8Qz7EGlTrT68c JIzc4RQZ4KHKc+pAIdo7/etB6iJ2lh9v1B1cQ8n1O6oyD57XTW/+lGRgEMvFkoVsRqNL w9SA== X-Forwarded-Encrypted: i=1; AJvYcCXl2UBbsdPoduI6Ss5sSEP2WVbU86Dr4q4P4i3gUzJY2vI5f3sXVcJVHavWcMTEUEoB6Yz5LtnlU5rJyVW2@vger.kernel.org X-Gm-Message-State: AOJu0YwAUhuHX1otjeZNv9lw8Lcz/81qxXmdqadgNJYdHYUrh2RONoHz AHC37+wZjRiaFoMFcVtF1FjrUXsUaCu0AEDQKdr8Og6LrvPVUFlbMBiR X-Gm-Gg: ASbGncvSafnhdYMxSUw28sU6Z3RSpddN0pIFbDWB/Iwm+B700T2q0sEVLPZRgbZbAng 2qoI1xg/7DwxNqIyapyU/1Jj0I2CwYq78CKQ2xCBQ2/Nx/o7pyIcuSkQ7KWeMX6AQhHSqlGSZCn ONNmsXxjiix0p06W9SZt7Popy7cFISPulYrKXs0nWDfdTBnKrxVh2PWq33f/PgVW8paaJmPR2qR QS9HKOXfALsunubbDLqAtJ+Y2J2vTFykpYotaG2dnmtw5BtSUeF0dOwmQrVCEx0XNAykYLalY3q U3aPxWcxGBc04Im7vFtpeAFU0u7DqdeVQsDbDQsdf33mDIFgD2bRLxctbCutfo5QRuTd1EeUXSg LsUbcmd5iQa27yKr7ZnQ= X-Google-Smtp-Source: AGHT+IHON1Ci4ArRCi8J9fIgnvSIH3M28UzX9E4XnN9n89/XqiNa63YZ+YYjbAguQ3rvFJAVU38Aqg== X-Received: by 2002:a05:622a:19aa:b0:473:884e:dcff with SMTP id d75a77b69052e-494ae4539b1mr3915141cf.13.1747339183019; Thu, 15 May 2025 12:59:43 -0700 (PDT) Received: from [192.168.124.1] (syn-067-243-142-039.res.spectrum.com. [67.243.142.39]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-494ae4fd80bsm1957231cf.56.2025.05.15.12.59.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 12:59:42 -0700 (PDT) From: Connor Abbott Date: Thu, 15 May 2025 15:58:47 -0400 Subject: [PATCH v6 5/7] drm/msm: Delete resume_translation() Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250515-msm-gpu-fault-fixes-next-v6-5-4fe2a583a878@gmail.com> References: <20250515-msm-gpu-fault-fixes-next-v6-0-4fe2a583a878@gmail.com> In-Reply-To: <20250515-msm-gpu-fault-fixes-next-v6-0-4fe2a583a878@gmail.com> To: Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747339176; l=3253; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=Qq5k1GBVvpOoe3vbf7lHYuU1s8ow91pqey8KnhArgxI=; b=/yM3pG9E+DokL/lrL3Cl3ogv2uxixtq/MENaQRhh9mJ7nye6cSJOdpS0NZNuJb+oTQewG5E6D ++dtz6vH3kzBvtRX4KSQtz77NW08TMP7QhhfQ5z4KlxpGJRz/i6wi0U X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= Unused since the previous commit. Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/adreno/a2xx_gpummu.c | 5 ----- drivers/gpu/drm/msm/msm_iommu.c | 13 ------------- drivers/gpu/drm/msm/msm_mmu.h | 1 - 3 files changed, 19 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpummu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpummu.c index 39641551eeb66d1441810c9691708ef448192578..4280f71e472a4130a62ba74e936870905ca260bb 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_gpummu.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpummu.c @@ -71,10 +71,6 @@ static int a2xx_gpummu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len) return 0; } -static void a2xx_gpummu_resume_translation(struct msm_mmu *mmu) -{ -} - static void a2xx_gpummu_destroy(struct msm_mmu *mmu) { struct a2xx_gpummu *gpummu = to_a2xx_gpummu(mmu); @@ -90,7 +86,6 @@ static const struct msm_mmu_funcs funcs = { .map = a2xx_gpummu_map, .unmap = a2xx_gpummu_unmap, .destroy = a2xx_gpummu_destroy, - .resume_translation = a2xx_gpummu_resume_translation, }; struct msm_mmu *a2xx_gpummu_new(struct device *dev, struct msm_gpu *gpu) diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 2a94e82316f95c5f9dcc37ef0a4664a29e3492b2..c6fed9bcb0021a5ad25d8487db1cc05869668c3e 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -323,7 +323,6 @@ static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, unsigned long iova, int flags, void *arg) { struct msm_iommu *iommu = arg; - struct msm_mmu *mmu = &iommu->base; struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(iommu->base.dev); struct adreno_smmu_fault_info info, *ptr = NULL; @@ -337,20 +336,9 @@ static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags); - if (mmu->funcs->resume_translation) - mmu->funcs->resume_translation(mmu); - return 0; } -static void msm_iommu_resume_translation(struct msm_mmu *mmu) -{ - struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(mmu->dev); - - if (adreno_smmu->resume_translation) - adreno_smmu->resume_translation(adreno_smmu->cookie, true); -} - static void msm_iommu_detach(struct msm_mmu *mmu) { struct msm_iommu *iommu = to_msm_iommu(mmu); @@ -398,7 +386,6 @@ static const struct msm_mmu_funcs funcs = { .map = msm_iommu_map, .unmap = msm_iommu_unmap, .destroy = msm_iommu_destroy, - .resume_translation = msm_iommu_resume_translation, }; struct msm_mmu *msm_iommu_new(struct device *dev, unsigned long quirks) diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h index 88af4f490881f2a6789ae2d03e1c02d10046331a..f118de637b1b35acba76a92c2cca1de9b2fad5a0 100644 --- a/drivers/gpu/drm/msm/msm_mmu.h +++ b/drivers/gpu/drm/msm/msm_mmu.h @@ -15,7 +15,6 @@ struct msm_mmu_funcs { size_t len, int prot); int (*unmap)(struct msm_mmu *mmu, uint64_t iova, size_t len); void (*destroy)(struct msm_mmu *mmu); - void (*resume_translation)(struct msm_mmu *mmu); }; enum msm_mmu_type { From patchwork Thu May 15 19:58:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Connor Abbott X-Patchwork-Id: 890245 Received: from mail-qk1-f175.google.com (mail-qk1-f175.google.com [209.85.222.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83F5C29B773 for ; Thu, 15 May 2025 19:59:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.222.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747339188; cv=none; b=jLehTamGOUgR/5Py5YLOkaj1MKNtR54jWoLZ5qI1yB9knKpNRraZsdFgNOqS9RUIhdqDFJh3t/5mIFVMPsQGgJixpgaz+5G43jgm+fEJxzYseaKMg2Q9wZu/XTbNVeHxaRoy5H/mL2h4zfBhB7tAeLR4MjPHDturaqyXwpi+kDg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747339188; c=relaxed/simple; bh=aRsZmjoGo/cSFHXwutiwXX9pdz9qjGh+q+3C5UDfQvg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sQ/b46+8PR+BoHiZHFeJxTRQNdDu80FXSMULGPeToMje/OCc8tBWfbtC1K0pWaU5KtopG1bFg/is42NrmXBS3uoQWB4PQAN/dIF/rkE5s0MDJq83lQn+ilJ95uASiMzXsA0WAdEU8m9/JGHKiuwNCf+g0U9jXbs8PGSByKqqhiw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=is+b4yhO; arc=none smtp.client-ip=209.85.222.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="is+b4yhO" Received: by mail-qk1-f175.google.com with SMTP id af79cd13be357-7c921ec37e5so10624885a.2 for ; Thu, 15 May 2025 12:59:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1747339185; x=1747943985; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=W9GO00zbxnFbKyoYKR1MGg1EYQGaCXyOc2lNqTvdH6I=; b=is+b4yhOqO4XccVREl7VkmDsuowbjyaVQcdnNWz+RIYdIHZ4zjzzFOPCcpqiw2C1YU W3sVEQQTRJ3Bdc4T0DSJP16f9RYuC3tVzAz4a0Dnvj6t2N8Vlbv+lKNZTtS9Z1uIKbx2 40BJSYtMc8PNpcaAhyMrG1gzUEKKl0BpQk/21iRRYtEX2NZNg04TJRiQvmKZRbJ0E3WE 4ZxOYeeMvw5YZqiIVAYQG4Alq+6aR7ms62h3cMY+V83kehbMV3a+bhqMBno00L6CQ1Wf 1SlhGPURFVWo9MWh3i2yOPGH9sQ0HwXh1HzW/sjlg3dBziYNNgkzXlUuZmko0EGPWB6C zySQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747339185; x=1747943985; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W9GO00zbxnFbKyoYKR1MGg1EYQGaCXyOc2lNqTvdH6I=; b=J0lKoueKvx3bsP1JJAp7zSRH16fiT7lXsZiSzv6yJSy8o7f/ajoR0UvLjNYhxm0LTG 9gdXzNnCo/dhnc2VoLHHSqtP4UTriVP2rnwz7CHhS7oZLFXZvok3Kx7z0bZJOrjSPkKS 3M/jNIBEhq7E6kGoOwNTPH+bO+GZum6A1avxCnNNoFJnItxcef7hJzirkk3fkHysco/C WvQMdMOYB/x1ljfsKbOuCoYi+HMiY5JQMpmev/5CzIWaznzkldLpaCHLt6l85pRipgmn 9ESHZ2zvjl+hiAJn2CS9EFapKHAmH7tfLw4LByH+8Q9GGx0QCIb0VwCKS0W1vFTLgz3C /Epg== X-Forwarded-Encrypted: i=1; AJvYcCW2OThskAKW5ZxcJTcb7YT/hcqX3POF4QT032AiE4CYyVC40UjJounIPBTxajC0o9lblpA46GcoTW6suIYl@vger.kernel.org X-Gm-Message-State: AOJu0Yz5hoeikyO5R26xs61/EmF6aTITJlUFIh/t9he7g87fIZCHbhq8 sW7FF+St9PM8c1HeC8BjymtKmjr3t8s4XT/t2ZzgFbm+DKtBFOiCVvzL X-Gm-Gg: ASbGncvrGNJtlUWvXGad49m2kC7AitLRwUoMuFYDOo9Sd3dCXWjT78KK1vtK/7khJma O2mmsEUDYsg/Iw+I+frkJTgG5FbN4dsZqNCsiOoSoVb9KZ35iTd68Re9KJwUNu2NbFWfj//4LNa H5PlD0tFhlceplwWMYMvP+BTBz1pO6qT0rJqJm+a/blxz3AQvGkYZJEnRKWYRgsQomz0npMM/78 32dXbFV9c5i8gjc6kwJZODwWoDRvrb3lEyPgana3JKh1xKMuZB4yq57CW4CMoSrNpVkhgnrdgDf 31VtvSm4KnP/uq/xKbm2Z3JgBEe8Uh5kdt7QPOdwQ4VLwLM7y/JKJDjVgpGETsiALPyyFA0BwX5 SJtrakoE1cSI5D9B8hlU= X-Google-Smtp-Source: AGHT+IG6CqnqToKilBZg3d95WbqLz8tctrzr994PFqGigAXmx649QoHO+YFYQoHsNTC0rhdZ3luaSQ== X-Received: by 2002:a05:620a:2803:b0:7c3:d1b9:e667 with SMTP id af79cd13be357-7cd4671faaemr58332985a.5.1747339185205; Thu, 15 May 2025 12:59:45 -0700 (PDT) Received: from [192.168.124.1] (syn-067-243-142-039.res.spectrum.com. [67.243.142.39]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-494ae4fd80bsm1957231cf.56.2025.05.15.12.59.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 12:59:44 -0700 (PDT) From: Connor Abbott Date: Thu, 15 May 2025 15:58:49 -0400 Subject: [PATCH v6 7/7] iommu/smmu-arm-qcom: Delete resume_translation() Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250515-msm-gpu-fault-fixes-next-v6-7-4fe2a583a878@gmail.com> References: <20250515-msm-gpu-fault-fixes-next-v6-0-4fe2a583a878@gmail.com> In-Reply-To: <20250515-msm-gpu-fault-fixes-next-v6-0-4fe2a583a878@gmail.com> To: Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747339176; l=1531; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=aRsZmjoGo/cSFHXwutiwXX9pdz9qjGh+q+3C5UDfQvg=; b=+pdVVw82/z0eIgzgC6o+AzTuVq7FlJ1dneFaBpTdAtknFxz/eSWyUdXaQGcHd4MoAd4oA8kti e6nMCOZKmtuBM8tRS1ISKqELZJCTLF3R76A1EnTAP8F/VIbPZJpnnUk X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= Unused since "drm/msm: Delete resume_translation()". Signed-off-by: Connor Abbott --- include/linux/adreno-smmu-priv.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h index 8ed94fb39e6ec6a3d8e6fabe61ff142682f1764c..80bb36e09f07901fd73c522ec077b0b3211adc50 100644 --- a/include/linux/adreno-smmu-priv.h +++ b/include/linux/adreno-smmu-priv.h @@ -46,9 +46,8 @@ struct adreno_smmu_fault_info { * @get_fault_info: Called by the GPU fault handler to get information about * the fault * @set_stall: Configure whether stall on fault (CFCFG) is enabled. If - * stalling on fault is enabled, the GPU driver must call - * resume_translation() - * @resume_translation: Resume translation after a fault + * stalling on fault is enabled, the GPU driver should return + * -EAGAIN from the fault handler if retrying is required. * * * The GPU driver (drm/msm) and adreno-smmu work together for controlling @@ -66,7 +65,6 @@ struct adreno_smmu_priv { int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); void (*set_stall)(const void *cookie, bool enabled); - void (*resume_translation)(const void *cookie, bool terminate); }; #endif /* __ADRENO_SMMU_PRIV_H */