From patchwork Wed May 14 07:01:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao via B4 Relay X-Patchwork-Id: 890409 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF7B32036F3; Wed, 14 May 2025 07:01:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747206102; cv=none; b=mxvQLAP4BpBVXgE9svRyOkEiabkFtQ4XEiDnC9oGn4R3UvAbHIczt3Cm9ltEb2g07fzY2Kzu6X9AfvUSCP43gHCTA9W91ZD/W9EyIemYigNx4d74vsAli+C7ERGh8YEzSaP+5EUWTW6o+9SwAfkGdtu3VD+qIxANLhbeiL1HMZc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747206102; c=relaxed/simple; bh=byLh/bsiv/fh1hzyDOXgi4uR68X6jhJgLI5muBJNEqE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pgCaIxIJ3776X6u8548WMtO7O8+CWoOSP3Q2Av6S5OJxdFtVcKKKsrZDNfumQ8TPUwQNO7xbNgeoAwCyq/NIMkYE9ciTG1rnubSC5WNTwtghYrObqddXMhFXYsMCVcGvKW7yh47gNF10gnpZj49HeQAGuXAoR7isG+zZDoPmab0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=otJpfrzN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="otJpfrzN" Received: by smtp.kernel.org (Postfix) with ESMTPS id 30A6BC4CEE9; Wed, 14 May 2025 07:01:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747206102; bh=byLh/bsiv/fh1hzyDOXgi4uR68X6jhJgLI5muBJNEqE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=otJpfrzN4sAQT2ytf8z6fW020uvqNP9h04UWaVVjgtgbv9mpVLikBN0rkvCwN318c Z0BL9wASYF5r9hPCB2l9JRn3b8WjWgXeYfWk9ZNPcHn8UDlxmFB2QZSq8dy6KDaX1p VxRoUXxw2qfXKA9R805Oc3BaieU+RLhqZ3hzDF6xdqhkLhIGb58Ux66Yry92kOTRhq mFyLv48vlCjqkODrxFM8r29SFKNp7bVJ1A2AsIK/Ra86nhNtedR7nGQ8q/gNhU1CZZ f+Y3W0JTAM+nYRlvtFN2ldmSpj0hDAD+c+r9rQxqYRa+tNyqIMARZ9/LeYwMFd1sLp uwYj04k7eihBg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E488C3ABDA; Wed, 14 May 2025 07:01:42 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 14 May 2025 15:01:28 +0800 Subject: [PATCH 1/8] dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S7 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-s6-s7-pinctrl-v1-1-39d368cad250@amlogic.com> References: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> In-Reply-To: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747206100; l=857; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=GTxtiAQGmCYOsgbEQ6EOKgzNKF5l16qDKM+F3b/U1zI=; b=Tss7kkbHInMJD70OvuMcwhicWga68wC2NtehbOPKsGQ2z8FEc6GRKYVYIE88fkviKSXt9HCpG 9Oe4CQ+Je/1AWPaRSy0cahmKIGRXxbF94t7lAUnZmL4+Dlvb1L4NChm X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Update dt-binding document for pinctrl of Amlogic S7. Signed-off-by: Xianwei Zhao --- Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml index c36b6fe377ad..8a6981e9f873 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml @@ -15,7 +15,9 @@ allOf: properties: compatible: oneOf: - - const: amlogic,pinctrl-a4 + - enum: + - amlogic,pinctrl-a4 + - amlogic,pinctrl-s7 - items: - enum: - amlogic,pinctrl-a5 From patchwork Wed May 14 07:01:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao via B4 Relay X-Patchwork-Id: 890408 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF823203706; Wed, 14 May 2025 07:01:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747206102; cv=none; b=SFFLAtZiIMrwJZQmkaiiFlbIAkojLSRn6WC0dUAPoV0iOkFglibUJysSqlhynV8SZ2GTfkliQSVIYPSVi7Rjh+lDp6zph4Wk36V3yaALmBwRTqNBPq+bud2uFo9CStkqHHGmEM7XfVmzt+b/nWy7RU02oKLcppMw2l+Kw9F2Fwc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747206102; c=relaxed/simple; bh=SqXI1uvoCkhyqkrY5xjtQtfDKxNrvjB2D2HwRduTNGc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SejN4XeP/sqyMZdoQL/KxSgcKW9G1y5Ojx32azkyRoZBWdFH2oVicclgq1u5hKSuRAyLPCLSgbIDS29hPPwytM3kFg+fYfo+xhmjFUh+SDI6QYQo+j+KU9w8mf5/sAZ9rvXgYL8h1Xr0t0pauUKxQabeiEHuZnca4/SN5eZ2Vi8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=K2OHsTUQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="K2OHsTUQ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3F87EC4CEF0; Wed, 14 May 2025 07:01:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747206102; bh=SqXI1uvoCkhyqkrY5xjtQtfDKxNrvjB2D2HwRduTNGc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=K2OHsTUQNkDEkSSMUAjk/aeXAhC6BLnwtb/0xF6Z5ExttzehGBwqkkPM/W6VlW0tQ nhQ414J24WnwQkTGAn22KMNF2vfCWUlTK+9mLoFc2JKex1wU05/R1z+a99mvCwlKF8 Ki3QbEnnnNuuTOx0FPGegaG1o53H3aZOQ9DYDjMLSdiLmSdYUEwl3ijYdK3f+qNJRW uPqvKeHgoWP3six4emWbwFSctczNr4HA6zlCE+tlxoUAq9erlfho2OMKn+UnKb1moY AyNkJ2Qj9b1IbqwAPNhaLbZynzRwWHdD9kHPiEqAMzP2YOqnjPA1sQO+hKzN5KgCXe yzQhXExOX0TTw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E97DC3ABDD; Wed, 14 May 2025 07:01:42 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 14 May 2025 15:01:29 +0800 Subject: [PATCH 2/8] dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S7D Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-s6-s7-pinctrl-v1-2-39d368cad250@amlogic.com> References: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> In-Reply-To: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747206100; l=1044; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=SRGfN0xHu7rPLyCZFtaZT28fxmetKbOy0Gk6C4ftPKQ=; b=3PHyXSoGV95skhliBDZMXH0l8EuvpG+EqyHCmUwBq2UV0lVqWG3FLCfhsTMVqMVVP8Ru2jAVz s83N7u82Sp/A5O1bSI4WQMyrSDP8znh40QyaIPL9cu/bGH2f6sCQB/K X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Update dt-binding document for pinctrl of Amlogic S7D SoC. Amlogic S7D SoCs uses the same pintrl controller as S7 SoCs. There is no need for an extra compatible line in the driver, but add S7D compatible line for documentation. Signed-off-by: Xianwei Zhao --- Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml index 8a6981e9f873..96a7c5646c13 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml @@ -22,6 +22,10 @@ properties: - enum: - amlogic,pinctrl-a5 - const: amlogic,pinctrl-a4 + - items: + - enum: + - amlogic,pinctrl-s7d + - const: amlogic,pinctrl-s7 "#address-cells": const: 2 From patchwork Wed May 14 07:01:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao via B4 Relay X-Patchwork-Id: 890011 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF87B204096; Wed, 14 May 2025 07:01:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747206102; cv=none; b=P+EM+EfH/9WqiXuL6mw5cQYdhynY8e9Y1wbPe5c/5yHzlXS+3zTEcdVbA3Tf6igUL282uCCD2MnTxCEQMNikNFscS6WWiRkt2BKHBGWwT54nNoT45JclEjEOvdcvau0n/2mCSjAU1LznFnSk1qpWFfiGFHfrgVxNdQ36keDDor8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747206102; c=relaxed/simple; bh=RhXaG6D10XuprrM2uwXZ+yryGaiW6qQjUHpNKKnNco4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FsbS1hTJumXwrbUnKbSxC0fNZkqObAD3vD2kdoEwLux2rigyyOVjhyZKHNv8No4E+GCyeJL30tbqAYIRESO0QVh7SiriCcRXQO2fj5PTcrZv0CtaiqxOJOU/hGJHEmqrXzPV80Z2e7NtuXYER+we5VbJUpx7bTIiFgjuRJNRXY4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eHwvoObs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eHwvoObs" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4C6A1C4CEEB; Wed, 14 May 2025 07:01:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747206102; bh=RhXaG6D10XuprrM2uwXZ+yryGaiW6qQjUHpNKKnNco4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=eHwvoObsxQY3MpoRSkhPWgLKhUksDEdk1jl8Wa8VmcNU26EGdaEst84a7hA8auT8/ SYLGSnnKnCZhzRpf24kMjECzayANSmpWVojht96wWY1xJe8maAq9edikem9yB8vpVn tgR9NxofW8wTLTeT64O4qACZNZZhg1r78MtvrCoWVQ3Q7PM3ELH+qvd/owQUIT7fo8 55OXG/SV6zpaIl+YnHCJyOm9L6Nsw1sTU3CiKkIlcXGK2Oiiy2napiGFGvrnH530UK yqy9TrePmCrkTKCQPBfqmkko9YRzDnr4ZX1yPb3NIlAcv79HZm1lUMuoiAybuf/rQq k37yTgs4Qhx5Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C497C3ABDE; Wed, 14 May 2025 07:01:42 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 14 May 2025 15:01:30 +0800 Subject: [PATCH 3/8] dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S6 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-s6-s7-pinctrl-v1-3-39d368cad250@amlogic.com> References: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> In-Reply-To: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747206100; l=777; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=SGs48wURMjraERop2ENTKoLj76g7oJ3ublU0QekYvzE=; b=rEqYoaagVtWnwccz+GPoTSGpAh94WJcq+4gnR1fgKV7VHyJeoiV4IoNKYrTVI+RfssOUFjmUS xZt7xPptmWPBGTOn3Rauo5rXQh3GVD6b7ou5ya83Rk7YLBhUHLgUG2I X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Update dt-binding document for pinctrl of Amlogic S6 SoC. Signed-off-by: Xianwei Zhao --- Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml index 96a7c5646c13..61a4685f9748 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml @@ -17,6 +17,7 @@ properties: oneOf: - enum: - amlogic,pinctrl-a4 + - amlogic,pinctrl-s6 - amlogic,pinctrl-s7 - items: - enum: From patchwork Wed May 14 07:01:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao via B4 Relay X-Patchwork-Id: 890012 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80B161FCFFC; Wed, 14 May 2025 07:01:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747206102; cv=none; b=MJYLH8EOdx7rMd46ED5XhY4fnb1uU7/zMVLSrbRREu8zBYj1fSw73n3EKCT8HIpOfwC+Tc8KVCXkYXPYWCWeWv2hrhRDd5CpebJSIeSVj2P1O1iOVa3BbsV2dDpR3s7v66ct3YNA9YrJo3FO+ChAeOUZLQKaC+oOKW9LzKI5Cvc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747206102; c=relaxed/simple; bh=urScH87aRUYYRU4uMH/UcgcwqDXNvfnULC466CYiu1A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mGWrlicG8UdSkYLOJerFRlRjY5XDBbRgDLFqFDluF4SBNL4gfRXYjpXLMXtQEdnWdNXGujp1Gk0kqzp7T+43DSdx9++T9YAtdg5a724wV+SuSCcN3d8EytwY17bSqgFDQTjpIwPaubeIE1AewWuRfHuozwOwhTXOKCbk9LaJDTQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UNcD5uGQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UNcD5uGQ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 54D4FC4CEF3; Wed, 14 May 2025 07:01:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747206102; bh=urScH87aRUYYRU4uMH/UcgcwqDXNvfnULC466CYiu1A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=UNcD5uGQI9/jVyg8Di29D94BA3lKhnw11VkC391nr75+adpIkN071VF/MsE2+vrA0 +3vu8f0btFQcB+KRwbLqMN03cxrGnEwzPK0w0rSh30VztddhiA73C5rgTxVGTDN0uu OEBbCNDG5H+UDkGePv5de6fRQKWCUDctFhz+E/laIG1sBCTfo9sWn6MLf/1bo5J8uz pxsHx9nqDkU/hJSyVo4isAaxf3+J5Fp+63HutVj2ONwrGePxK0SPD2ht8OGWPNMXP3 PrKw97EuTruCSAvf39BfyK//xCTp1rV4GQdD4S34qIW80Y/Ra37Mo6BEzKGwmIx3+r x1of5bS0L+Ypg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AF4AC3ABDC; Wed, 14 May 2025 07:01:42 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 14 May 2025 15:01:31 +0800 Subject: [PATCH 4/8] pinctrl: meson: a4: remove special data processing Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-s6-s7-pinctrl-v1-4-39d368cad250@amlogic.com> References: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> In-Reply-To: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747206100; l=1982; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=FRMEmxN5zjpQVQOxtUKSm3GQm/lC+q2P8YsijCrDdRM=; b=+6hLKSp0TODk9+4jPyX0PxesuamsmX2QcK+x5esdSc3SYblzTFKWXatB/oAB2U0+Tfv5MEg6X ZWVfF23ZwRGA4BhIn08ObpMSlwTK3z44oHVT+iB42n7EHzbE+Qh2xO9 X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao According to the data specifications of Amlogic's existing SoCs, the function register offset and the bit offset are the same value among various chips. Therefore, general processing can be carried out without the need for private data modification. Drop special data processing. Signed-off-by: Xianwei Zhao --- drivers/pinctrl/meson/pinctrl-amlogic-a4.c | 33 +++--------------------------- 1 file changed, 3 insertions(+), 30 deletions(-) diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c index a76f266b4b94..90d4d10ca10b 100644 --- a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c +++ b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c @@ -50,15 +50,8 @@ struct aml_pio_control { u32 bit_offset[AML_NUM_REG]; }; -struct aml_reg_bit { - u32 bank_id; - u32 reg_offs[AML_NUM_REG]; - u32 bit_offs[AML_NUM_REG]; -}; - struct aml_pctl_data { unsigned int number; - struct aml_reg_bit rb_offs[]; }; struct aml_pmx_func { @@ -843,31 +836,11 @@ static const struct gpio_chip aml_gpio_template = { static void init_bank_register_bit(struct aml_pinctrl *info, struct aml_gpio_bank *bank) { - const struct aml_pctl_data *data = info->data; - const struct aml_reg_bit *aml_rb; - bool def_offs = true; int i; - if (data) { - for (i = 0; i < data->number; i++) { - aml_rb = &data->rb_offs[i]; - if (bank->bank_id == aml_rb->bank_id) { - def_offs = false; - break; - } - } - } - - if (def_offs) { - for (i = 0; i < AML_NUM_REG; i++) { - bank->pc.reg_offset[i] = aml_def_regoffs[i]; - bank->pc.bit_offset[i] = 0; - } - } else { - for (i = 0; i < AML_NUM_REG; i++) { - bank->pc.reg_offset[i] = aml_rb->reg_offs[i]; - bank->pc.bit_offset[i] = aml_rb->bit_offs[i]; - } + for (i = 0; i < AML_NUM_REG; i++) { + bank->pc.reg_offset[i] = aml_def_regoffs[i]; + bank->pc.bit_offset[i] = 0; } } From patchwork Wed May 14 07:01:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao via B4 Relay X-Patchwork-Id: 890406 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88D1220FA81; Wed, 14 May 2025 07:01:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 14 May 2025 07:01:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747206103; bh=RqOyY2jGCkyEVgXr7GCKE7372fyZqazKLEDvm8VS4nA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=HCNYoxu+yPlb+arEGU8A+AV1VzIIyn7mdqbyISKRa/3pixyQ4n1r2jY5BwbGXFve+ ohqbahroBGlr8cGF6kMgEI+9qL9nnUeI91arz2dInEDPDqRc40DP5XPbUc3p3H+GOc VnvzQwRFFekdYZvSh26OgxyjEMnxHdlNp1kJdXk17xQwGm4FlAGfjtcHkHOs7bdCn4 wJJi+JoL7bXm7Tm/rrR6SHKMKRPG1ehpFjfi1/xuwkZweDgFkQyCzZKTMdHV5YCC8P w2qEqMyBkns8Qn76b3nmJT669lN8pq2/109MXIKP6Xgomm8NiPZBGwqSvLIwv9oHYL C9wEvuEMTroJw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59009C3ABDA; Wed, 14 May 2025 07:01:42 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 14 May 2025 15:01:32 +0800 Subject: [PATCH 5/8] pinctrl: meson: support amlogic S6/S7/S7D SoC Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-s6-s7-pinctrl-v1-5-39d368cad250@amlogic.com> References: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> In-Reply-To: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747206100; l=5229; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=gBld46AxkELbpQvuVxx+JAeuTI0Fp+bQupU9PRwGIaM=; b=O0H7JfjGniNuecua7TnPLDc7MaS7+00eIT5GXbEd2wGaDL8q8He4wQek3RADn0VfcH6+uskOK dXygW6aEOgqABPsJ3fMmyGH4oFflTnEVQs1wThzAI05bwrQeZVC7B+n X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao In some Amlogic SoCs, to save register space or due to some abnormal arrangements, two sets of pins share one mux register. A group starting from pin0 is the main pin group, which acquires the register address through DTS and has management permissions, but the register bit offset is undetermined. Another GPIO group as a subordinate group. Some pins mux use share register and bit offset from bit0 . But this group do not have register management permissions. This submission implements this situation. Signed-off-by: Xianwei Zhao --- drivers/pinctrl/meson/pinctrl-amlogic-a4.c | 94 +++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c index 90d4d10ca10b..f2c98ee9cdb1 100644 --- a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c +++ b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c @@ -50,8 +50,23 @@ struct aml_pio_control { u32 bit_offset[AML_NUM_REG]; }; +/* + * partial bank(subordinate) pins mux config use other bank(main) mux registgers + * m_bank_id: the main bank which pin_id from 0, but register bit not from bit 0 + * m_bit_offs: bit offset the main bank mux register + * sid: start pin_id of subordinate bank + * eid: end pin_id of subordinate bank + */ +struct multi_mux { + unsigned int m_bank_id; + unsigned int m_bit_offs; + unsigned int sid; + unsigned int eid; +}; + struct aml_pctl_data { unsigned int number; + struct multi_mux multi_data[]; }; struct aml_pmx_func { @@ -71,10 +86,12 @@ struct aml_gpio_bank { struct gpio_chip gpio_chip; struct aml_pio_control pc; u32 bank_id; + u32 mux_bit_offs; unsigned int pin_base; struct regmap *reg_mux; struct regmap *reg_gpio; struct regmap *reg_ds; + const struct multi_mux *p_mux; }; struct aml_pinctrl { @@ -106,13 +123,39 @@ static const char *aml_bank_name[31] = { "GPIOCC", "TEST_N", "ANALOG" }; +const struct aml_pctl_data s7_priv_data = { + .number = 1, + .multi_data[0] = { + .m_bank_id = AMLOGIC_GPIO_CC, + .m_bit_offs = 24, + .sid = (AMLOGIC_GPIO_X << 8) + 16, + .eid = (AMLOGIC_GPIO_X << 8) + 19, + }, +}; + +const struct aml_pctl_data s6_priv_data = { + .number = 2, + .multi_data[0] = { + .m_bank_id = AMLOGIC_GPIO_CC, + .m_bit_offs = 24, + .sid = (AMLOGIC_GPIO_X << 8) + 16, + .eid = (AMLOGIC_GPIO_X << 8) + 19, + }, + .multi_data[1] = { + .m_bank_id = AMLOGIC_GPIO_F, + .m_bit_offs = 4, + .sid = (AMLOGIC_GPIO_D << 8) + 6, + .eid = (AMLOGIC_GPIO_D << 8) + 6, + }, +}; + static int aml_pmx_calc_reg_and_offset(struct pinctrl_gpio_range *range, unsigned int pin, unsigned int *reg, unsigned int *offset) { unsigned int shift; - shift = (pin - range->pin_base) << 2; + shift = ((pin - range->pin_base) << 2) + *offset; *reg = (shift / 32) * 4; *offset = shift % 32; @@ -124,9 +167,36 @@ static int aml_pctl_set_function(struct aml_pinctrl *info, int pin_id, int func) { struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); + unsigned int shift; int reg; - int offset; + int i; + unsigned int offset = bank->mux_bit_offs; + const struct multi_mux *p_mux; + + /* peculiar mux reg set */ + if (bank->p_mux) { + p_mux = bank->p_mux; + if (pin_id >= p_mux->sid && pin_id <= p_mux->eid) { + bank = NULL; + for (i = 0; i < info->nbanks; i++) { + if (info->banks[i].bank_id == p_mux->m_bank_id) { + bank = &info->banks[i]; + break; + } + } + + if (!bank || !bank->reg_mux) + return -EINVAL; + + shift = (pin_id - p_mux->sid) << 2; + reg = (shift / 32) * 4; + offset = shift % 32; + return regmap_update_bits(bank->reg_mux, reg, + 0xf << offset, (func & 0xf) << offset); + } + } + /* normal mux reg set */ if (!bank->reg_mux) return 0; @@ -836,12 +906,30 @@ static const struct gpio_chip aml_gpio_template = { static void init_bank_register_bit(struct aml_pinctrl *info, struct aml_gpio_bank *bank) { + const struct aml_pctl_data *data = info->data; + const struct multi_mux *multi_data; int i; for (i = 0; i < AML_NUM_REG; i++) { bank->pc.reg_offset[i] = aml_def_regoffs[i]; bank->pc.bit_offset[i] = 0; } + + bank->mux_bit_offs = 0; + + if (data) { + for (i = 0; i < data->number; i++) { + multi_data = &data->multi_data[i]; + if (bank->bank_id == multi_data->m_bank_id) { + bank->mux_bit_offs = multi_data->m_bit_offs; + break; + } + if (multi_data->sid >> 8 == bank->bank_id) { + bank->p_mux = multi_data; + break; + } + } + } } static int aml_gpiolib_register_bank(struct aml_pinctrl *info, @@ -1008,6 +1096,8 @@ static int aml_pctl_probe(struct platform_device *pdev) static const struct of_device_id aml_pctl_of_match[] = { { .compatible = "amlogic,pinctrl-a4", }, + { .compatible = "amlogic,pinctrl-s7", .data = &s7_priv_data, }, + { .compatible = "amlogic,pinctrl-s6", .data = &s6_priv_data, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, aml_pctl_dt_match); From patchwork Wed May 14 07:01:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao via B4 Relay X-Patchwork-Id: 890010 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5AB6205501; Wed, 14 May 2025 07:01:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747206103; cv=none; b=mfAT7RypE4QUKl69fNA1Ruy6XWndSZW8RAXcrhnl1bYlECR0cn+eP6E6oI4o6riqqVZO3kT5QXRuFp0jZzOupJP714kDyvPIWkCxPd+Cos0De24hjgNj9B/UKKcnS0p8Iw5el3y42SZIGQhlQhcFRBKakjoaQSOr+4fMg9Q7QqY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747206103; 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Wed, 14 May 2025 07:01:42 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 14 May 2025 15:01:33 +0800 Subject: [PATCH 6/8] dts: arm64: amlogic: add S7 pinctrl node Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-s6-s7-pinctrl-v1-6-39d368cad250@amlogic.com> References: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> In-Reply-To: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747206100; l=3124; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=BWdYQqBMaY6QH+w4v+ycYDJAgq8chiBLXYLDSukgN2o=; b=+Ojibt0W9PyMDMcmm+oqePAvJGE6pbyxpns8nJEEzkxJkF5VaeXtMu78lrbksG/xg48gTpqxy NZOAnWHK9uWCvY8S0ChDP7W6uFDlWVeqLO5AQ9CZBpt+/B+MrcC2Txu X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add pinctrl device to support Amlogic S7. Signed-off-by: Xianwei Zhao --- arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 81 +++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi index f0c172681bd1..924f10aff269 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { cpus { @@ -94,6 +95,86 @@ uart_b: serial@7a000 { clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; + + periphs_pinctrl: pinctrl { + compatible = "amlogic,pinctrl-s7"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>; + + gpioz: gpio@c0 { + reg = <0 0xc0 0 0x20>, <0 0x18 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 13>; + }; + + gpiox: gpio@100 { + reg = <0 0x100 0 0x30>, <0 0xc 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; + }; + + gpioh: gpio@140 { + reg = <0 0x140 0 0x20>, <0 0x2c 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 12>; + }; + + gpiod: gpio@180 { + reg = <0 0x180 0 0x20>, <0 0x40 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 12>; + }; + + gpioe: gpio@1c0 { + reg = <0 0x1c0 0 0x20>, <0 0x48 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>; + }; + + gpioc: gpio@200 { + reg = <0 0x200 0 0x20>, <0 0x24 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>; + }; + + gpiob: gpio@240 { + reg = <0 0x240 0 0x20>, <0 0x0 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; + }; + + test_n: gpio@2c0 { + reg = <0 0x2c0 0 0x20>; + reg-names = "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = + <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; + }; + + gpiocc: gpio@300 { + reg = <0 0x300 0 0x20>, <0 0x14 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; + }; + }; }; }; }; From patchwork Wed May 14 07:01:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao via B4 Relay X-Patchwork-Id: 890407 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECCB8205502; Wed, 14 May 2025 07:01:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=ed25519-sha256; t=1747206100; l=3396; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=aT13wp7utfZt17yM5w7BMgo+z9/dQ9PDbViGUVlLZus=; b=5tfeiZNABChrE/HjXy92wSrWmtbhFa2QQw4K95Ftsg6X6v3om6qOyW5BZFdbtCpmrWvWFe8/b 0KGElMPiZQ7DfCGoQhlXmW9yi1Doi3qi7h4+aSf8/j5Zpbl7ddJ6kRx X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add pinctrl device to support Amlogic S7D. Signed-off-by: Xianwei Zhao --- arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi | 90 ++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi index e1099bc1535d..4de889bf291b 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { cpus { @@ -94,6 +95,95 @@ uart_b: serial@7a000 { clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; + + periphs_pinctrl: pinctrl { + compatible = "amlogic,pinctrl-s7d", + "amlogic,pinctrl-s7"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>; + + gpioz: gpio@c0 { + reg = <0 0xc0 0 0x20>, <0 0x18 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 13>; + }; + + gpiox: gpio@100 { + reg = <0 0x100 0 0x30>, <0 0xc 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; + }; + + gpioh: gpio@140 { + reg = <0 0x140 0 0x20>, <0 0x2c 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 12>; + }; + + gpiod: gpio@180 { + reg = <0 0x180 0 0x20>, <0 0x40 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 5>; + }; + + gpioe: gpio@1c0 { + reg = <0 0x1c0 0 0x20>, <0 0x48 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>; + }; + + gpioc: gpio@200 { + reg = <0 0x200 0 0x20>, <0 0x24 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>; + }; + + gpiob: gpio@240 { + reg = <0 0x240 0 0x20>, <0 0x0 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; + }; + + gpiodv: gpio@280 { + reg = <0 0x280 0 0x20>, <0 0x8 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_DV<<8) 7>; + }; + + test_n: gpio@2c0 { + reg = <0 0x2c0 0 0x20>; + reg-names = "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = + <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; + }; + + gpiocc: gpio@300 { + reg = <0 0x300 0 0x20>, <0 0x14 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; + }; + }; }; }; }; From patchwork Wed May 14 07:01:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao via B4 Relay X-Patchwork-Id: 890008 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A8F02153EA; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="a6FKA/A0" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8AAF6C4CEFD; Wed, 14 May 2025 07:01:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747206102; bh=Pm8RjpxsF/4T3Jz5C4xdzYDV9KddSNMY1eVaNkY9kdw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=a6FKA/A0VLcb5Wj9gVKWihgGWtje6S1HfASIniNVddjJB7LcLlpoH4C6ole4PKgfz In1mGbIPWTxxad//6ccgtWDwyzkyeVcTnQtTMwQmUd9xnqEedph7r8xh9GCL10un8h kIZlndFo2MgahMWmUW32bqguhUcJ/ZD/g/Vb9HKmMIVSr8Tag4Of/zoeSS2HhcV5Op xL1UxXxI5XQKCC8TnUBd/MDwiH0FzrUnx4QzU44IKrC8lx9Shqg0n7gkPuhCNA+OY2 q5g9Y8ZK0bvAXtx0uLbaOXEIicpMmy/biwOdNSxhR7AT+vpcq5DIbYoEUiHCEY2aJ9 SAWTMrmC2dhEw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80558C3DA4A; Wed, 14 May 2025 07:01:42 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 14 May 2025 15:01:35 +0800 Subject: [PATCH 8/8] dts: arm64: amlogic: add S6 pinctrl node Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-s6-s7-pinctrl-v1-8-39d368cad250@amlogic.com> References: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> In-Reply-To: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747206100; l=3610; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=LQtEhTH+4eGkcgIF+Vwy2luHuUbtEoQ8YiYPmKbSysk=; b=S8+ebZFd/3aLdScnhUNT2oKPoPi/XIvUCU86CBgbhCRKe7b7J6FzLOMCx5QjOuvMj9DIUAUUw Lz+sz4JJ1dwBZz+LtWhw6/woTdNSztnNVqS3qabFwUDOx1uSBwibmHm X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add pinctrl device to support Amlogic S6. Signed-off-by: Xianwei Zhao --- arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi | 97 +++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi index a8c90245c42a..5324079808c4 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { cpus { #address-cells = <2>; @@ -92,6 +93,102 @@ uart_b: serial@7a000 { clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; + + periphs_pinctrl: pinctrl { + compatible = "amlogic,pinctrl-s6"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>; + + gpioz: gpio@c0 { + reg = <0 0xc0 0 0x20>, <0 0x18 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 16>; + }; + + gpiox: gpio@100 { + reg = <0 0x100 0 0x30>, <0 0xc 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; + }; + + gpioh: gpio@140 { + reg = <0 0x140 0 0x20>, <0 0x2c 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 9>; + }; + + gpiod: gpio@180 { + reg = <0 0x180 0 0x20>, <0 0x8 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 7>; + }; + + gpiof: gpio@1a0 { + reg = <0 0x1a0 0 0x20>, <0 0x20 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_F<<8) 5>; + }; + + gpioe: gpio@1c0 { + reg = <0 0x1c0 0 0x20>, <0 0x48 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 3>; + }; + + gpioc: gpio@200 { + reg = <0 0x200 0 0x20>, <0 0x24 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>; + }; + + gpiob: gpio@240 { + reg = <0 0x240 0 0x20>, <0 0x0 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; + }; + + gpioa: gpio@280 { + reg = <0 0x280 0 0x20>, <0 0x40 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_A<<8) 16>; + }; + + test_n: gpio@2c0 { + reg = <0 0x2c0 0 0x20>; + reg-names = "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = + <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; + }; + + gpiocc: gpio@300 { + reg = <0 0x300 0 0x20>, <0 0x14 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; + }; + }; }; }; };