From patchwork Tue May 13 12:13:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 889796 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72C7228DEF8; Tue, 13 May 2025 12:13:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747138399; cv=none; b=oiW2KoOhd+KkyYOW/Kn+0K8/08aG1QrRrJzYLumTGbqyUcEEhuQBnVOX2kSR4JYcYdV/5B7qdwf5gjSJuwu6MJSzU6lsiuW7F+m/0q/mmeehNhQDBksot0yQMjwNdvOiKqcBBKkigxxJKLmStlvIZEH5yebILCEWOmdvadccUso= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747138399; c=relaxed/simple; bh=YbtaSFXvEqscgWdaWU4X/6cPyfGpueE1ti1NCjiITjk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mNODnFY17LuLCoyajGMkMFjSoMhwjPo0Tol77PGQZaafO/AopJm6Ug3irGpIzl24CRoaBCjk/c9RJbkW2nY/UHd9CGgzUTXtfdzayefsfmKrR6Q8HgRysf0bZ3X4xajxiegB9e+DrkLih2mQyUI4tbQ9sXIWUwT+IXuSnsnEx38= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rGu/rpH1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rGu/rpH1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2682AC4CEE9; Tue, 13 May 2025 12:13:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747138398; bh=YbtaSFXvEqscgWdaWU4X/6cPyfGpueE1ti1NCjiITjk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=rGu/rpH1MA164QuK0ou2pWRpUgfE8nHm0/S+vkfGUXEojYgwFCBX7UA0FJdpHp5h4 pfUXoH+olTdcGU6FcFuIXcDoBE6BaXU3T9C5Ln2BU/SJORHmixFatvIrYO70nlMqXy zzTawTnN/vdjd+8CCPlQJM9Hqk90gbqrfrgXIzPYoTMyMKoN4/k+XmwORCWmJg3kOm dEuoHRKo/+6HCZucD/4LBtBrv7MP1lnn5K1f/eub/tlDPjxYJu66oVReS9lv0cz0Uo a2SBdo0rV/S949rzCpqV9cdd+KLxgd/Pt9hdJM8QcPoA5MUL//thycZ2pXZ0MsBOtz Zp4Iaa8HOnF8A== From: Roger Quadros Date: Tue, 13 May 2025 15:13:06 +0300 Subject: [PATCH net-next v3 2/9] net: ethernet: ti: cpsw_ale: return ALE index in cpsw_ale_add_vlan() Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250513-am65-cpsw-rx-class-v3-2-492d9a2586b6@kernel.org> References: <20250513-am65-cpsw-rx-class-v3-0-492d9a2586b6@kernel.org> In-Reply-To: <20250513-am65-cpsw-rx-class-v3-0-492d9a2586b6@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , danishanwar@ti.com Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2474; i=rogerq@kernel.org; h=from:subject:message-id; bh=YbtaSFXvEqscgWdaWU4X/6cPyfGpueE1ti1NCjiITjk=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBoIzdU/MV48zcLrqcUBwzsULKToR4Nu+mp0Js7t j+Z3zXuA2uJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCaCM3VAAKCRDSWmvTvnYw k0S0D/sF9ukm9/9KfGdv+nlLyLExnkQR27fsvEdETZFKMEUnE7Ddldd34VTawbOtj22D3sbdGSy q20NRvbzh9in17YTCTsUzKNSfmmtI1m5NJu55tnVeVvLzPaali5+bLl38MYUCYcz+u1c4YT9Crx 5of7fYd/VMQ2scdAN8YgIW8SSMnlXCByGW904e0Z1kjgwBd1ic5YU3GNJh/y1AcYnRpBdFoHtsQ QX8Xvc5O7CURbX5kWsPGJ9O1mQfJ211nPGUrNLBgYiriGuvl8OPqxXMl50hFfSyWPi3JdYZSy07 UNgAXXqV0cCsQoB1kVmpXBpQe2uMPgVD0qJqleJOXj9DE7qr00hsH6ckacb58peR5MVsg0ZD6rX AeoXYK2JNlk/KyhSCZ2zIJ8ueKmYL8KoKF78POlPLUMV14fhKHMg4s3SK41gvO+txhAPpQaDcdc gsbGd9YmEXp7bJlLK0nGRlzCsucDNM0Km5zl64gp4frnHSXgRg9Ysb/SngnodBz+McYBNvo3CKR 3YfaPUifYXdZ9rHWBUVQdg2q9VsVjmN2YYUYFKM3KxzVD1nDuQ/K9PWPXCwJrGtpxonJs0pbl3G VeytGcQeZ23ITMoNpZ5AxUvjISEVR7jIyNtMuWC0yBYRrUzp/5wv6th17a2DFGSJvN6wA/i68yw z2leyUOuY6MRbbw== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Policer helpers will be interested to know what ALE index was used for the added VLAN entry. So return the ALE index instead of zero on success. Modify existing users to check for less than zero as error case. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw.c | 2 +- drivers/net/ethernet/ti/cpsw_ale.c | 6 +++--- drivers/net/ethernet/ti/cpsw_new.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index a984b7d84e5e..2d23cba557f3 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -1026,7 +1026,7 @@ static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask, unreg_mcast_mask); - if (ret != 0) + if (ret < 0) return ret; ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 7bb63aad7724..0bdc95552410 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -680,7 +680,7 @@ int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port_mask, int untag, return -ENOMEM; cpsw_ale_write(ale, idx, ale_entry); - return 0; + return idx; } static void cpsw_ale_vlan_del_modify_int(struct cpsw_ale *ale, u32 *ale_entry, @@ -803,14 +803,14 @@ int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask, ret = cpsw_ale_add_vlan(ale, vid, vlan_members, untag_members, reg_mcast_members, unreg_mcast_members); - if (ret) { + if (ret < 0) { dev_err(ale->params.dev, "Unable to add vlan\n"); return ret; } dev_dbg(ale->params.dev, "port mask 0x%x untag 0x%x\n", vlan_members, untag_mask); - return ret; + return 0; } void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, diff --git a/drivers/net/ethernet/ti/cpsw_new.c b/drivers/net/ethernet/ti/cpsw_new.c index 5b5b52e4e7a7..1516171352cd 100644 --- a/drivers/net/ethernet/ti/cpsw_new.c +++ b/drivers/net/ethernet/ti/cpsw_new.c @@ -417,7 +417,7 @@ static int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask, unreg_mcast_mask); - if (ret != 0) + if (ret < 0) return ret; ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, From patchwork Tue May 13 12:13:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 889795 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D85428EA42; Tue, 13 May 2025 12:13:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747138405; cv=none; b=jA6ebabjJy7fRwe26asez3N6POMUxvjsRSZt2glyHtjEMoweVMkMmAVSZRvuqPxgoJOluurTFiYGVe3nSGUTUCG+es+oCE7COYIBcKOim5oVlguDOrpIiKmFLuGnAMeRz1KWnuyXZBqnLmEucCcx4jS+EevmGIkfQKl2J18zn6A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747138405; c=relaxed/simple; bh=7wsQp+uaWY2u0ja4R/dpHDQPnssNtRTBw5npmaUzg0A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WGQTipQY2artUegVlXhDdZer/xbC4qdTCFJXzRLiBw7UwrwsnjNsVaTjAsn5MgZxVEeoz8shCN6ov88rdBsxJS8QIfap8UQ2n4WW2CFnWUjQxBn9weHAYbDVX4ql9kTNcLOpRY+yTGGX9tB2NnwtP4zU5q7TAEVXI7k/UAdAi2o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jCTxPgxY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jCTxPgxY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B19A9C4CEE9; Tue, 13 May 2025 12:13:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747138405; bh=7wsQp+uaWY2u0ja4R/dpHDQPnssNtRTBw5npmaUzg0A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=jCTxPgxY2Ep+4y3GZeO65nnVODtniLqng6IUn6R4NTuFpxXa9jDxCUfO3FdV1oxht xwlS2cH3eDUo3/lyOkAdewjCoHKBMeSc1kUeZMT7eGlSojGSIsNynfQQH/46BVodER Kx409AVDGXClpYY+fOXeV7kE8QILz3u/Y4SSqIBc/8X+Tdf14A39FJaR1e0aLoD7Ir XZxfYlzs+JpSkbcDIkbKWNHPkF7nt9n/7e6ykBi3uTmCs6u3nHJT1F5O9zOiDBpnxt Gl7RahqziB12eiNoYJ5acT5l6+9ePaR3IuQ+Xs0jk8SG/1QXhDrBJ1jD/7l6QgG8R8 cLL+tbp5Menlg== From: Roger Quadros Date: Tue, 13 May 2025 15:13:08 +0300 Subject: [PATCH net-next v3 4/9] net: ethernet: ti: cpsw_ale: return ALE index in cpsw_ale_add_ucast() Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250513-am65-cpsw-rx-class-v3-4-492d9a2586b6@kernel.org> References: <20250513-am65-cpsw-rx-class-v3-0-492d9a2586b6@kernel.org> In-Reply-To: <20250513-am65-cpsw-rx-class-v3-0-492d9a2586b6@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , danishanwar@ti.com Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1944; i=rogerq@kernel.org; h=from:subject:message-id; bh=7wsQp+uaWY2u0ja4R/dpHDQPnssNtRTBw5npmaUzg0A=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBoIzdUxoNSaPutkFDBr5PO78ZpocZsn3PhC9H9M /QSAtTDJlqJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCaCM3VAAKCRDSWmvTvnYw k2RzEACZx1NGXFXO4S5uRG5HmcDTApUFrR/l27nMHbtntvvtUmCswJ6PP8y0kg8Jzqb7lf/Lypw +zGOZal4G+jG1fe6BQscKAG4uEs9Qn/eQGi37B949kpSCNKnO7Zs2Ctgi9PpKtBEcc+FgeTiMyg pBhjgGObPKpSLQY4wBGeZDOPPmXc+btTJU+qFlVPDSESSMZn90i/4Aa687LGzw4p5TyVw+/Irjh 4NFeZGlHZu/WZjH+k2vVgTaY1Cjzx2LEahHp11VzV+GFGvrbC8SMybtumA0DhZfe0bE8gc8ys7G XQwOpMh8VJdHx2s79HbUnJfRVFiOVZ0+QVWXMyhfMA38ed6k+tRyIpno3Dz8TLikRs3SX4jWCB5 ZY6SsYxgs+FEwcz0VTOYU0NSvQ/QUePRBGyLsBNMuumvsFIPbCzcnfeG9e2eXwnoJUFHsJzRSWJ NrKyV/bDd+ovUIEggp/7iXEl7fAZCACm94ehIHeeWo7t9lOKZpAomYvyRsVbM1S/P4ZCsvku8HG nsN1JmGmwznAQ5/zt5aPkkdRcNOBHwbhR9y/VEiPD1zM+jB1G01zl0kXxkZlG63dH/OUBx+68vN NxFSqd0pluosaChQtVkXt9ggzQ49fbkfOjuTPOTKTEqHdEgqqtzNj+7ITuEeLTgocQuisvp+HdT S7T83X+hEWej3YA== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Policer helpers will need to know what ALE index was used for the added unicast entry. So return the ALE index instead of zero on success. Modify existing users to check for less than zero as error case. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw.c | 2 +- drivers/net/ethernet/ti/cpsw_ale.c | 2 +- drivers/net/ethernet/ti/cpsw_new.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 2d23cba557f3..d1abd2fb63c9 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -1031,7 +1031,7 @@ static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, ALE_VLAN, vid); - if (ret != 0) + if (ret < 0) goto clean_vid; ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 952444b0c436..74dc431f1c1b 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -534,7 +534,7 @@ int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port, return -ENOMEM; cpsw_ale_write(ale, idx, ale_entry); - return 0; + return idx; } int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port, diff --git a/drivers/net/ethernet/ti/cpsw_new.c b/drivers/net/ethernet/ti/cpsw_new.c index 1516171352cd..944fa3db94a2 100644 --- a/drivers/net/ethernet/ti/cpsw_new.c +++ b/drivers/net/ethernet/ti/cpsw_new.c @@ -422,7 +422,7 @@ static int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, ALE_VLAN, vid); - if (ret != 0) + if (ret < 0) goto clean_vid; ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, From patchwork Tue May 13 12:13:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 889794 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 807EF2918FE; Tue, 13 May 2025 12:13:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747138412; cv=none; b=POMZlQnjdwLPADf6hDiHhZ9Gxx6qr/FKpwxjUEQ5tRvmae6kXUKCWjDMdi0Fr5Smo0j0gjgcYc6IySXMGiiCKqftfcijDuR/t+3nYQX+gvNaZf1+rrG7EbPCr/yPVCWYQPd5wyliC+X6fYKuDfvRkyw/9TsoPwPsbC4rtK7BQLc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747138412; c=relaxed/simple; bh=yvDolz4DU7x4F3IPiMMAYL9Zyt+CPJcn+6QaEzC3KRo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KhKBPA/oNhyaRVPmj3l+JBySsvs+NHQkl4x7pujJGMwF/H0KW3x+Pqr7WZe02RW+W9zDtxt+e9ZcIkznwSM0g9aJuOnXIHgs3zkzrAh3YrN3SeMGYojMCQXZTRpu0SLAqGediM/+9wcaJgpryA32vBxpaiYtN3h6jeuUrdLVdiM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SCi6nTE7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SCi6nTE7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 41BB4C4CEE9; Tue, 13 May 2025 12:13:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747138412; bh=yvDolz4DU7x4F3IPiMMAYL9Zyt+CPJcn+6QaEzC3KRo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SCi6nTE7vWPpa+nQF75ckP6M4xm3T8IZOsDLBP2a5++9LZZhR9kh8STeOTrKMTzx1 JXAgT2vPwpFQRfTz05nJCvImnL/GSHv1d24WhzqNTrZJxLSDtgybU4W6beAXtHF5xa fZZzdoBiKP3fQ88f4qjCRzclairKMQa8g6E0ARZSVihVy7NMkBaNJ1D24TSspTVhWZ U6y3Ak9GBjaj97wDhA5STCvK1Apf/9gKAiTS4bPe1IItkdFRtWbwfDDLI9yrDcP7yf hPsqlFavbSwCayliLRGfjs9dgJax4L6ViA3R9AuJg2wSK5iVrxZCmU5cC/rQr+lHSi rWe8ZrxT3W5Gg== From: Roger Quadros Date: Tue, 13 May 2025 15:13:10 +0300 Subject: [PATCH net-next v3 6/9] net: ethernet: ti: cpsw_ale: add cpsw_ale_policer_set/clr_entry() Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250513-am65-cpsw-rx-class-v3-6-492d9a2586b6@kernel.org> References: <20250513-am65-cpsw-rx-class-v3-0-492d9a2586b6@kernel.org> In-Reply-To: <20250513-am65-cpsw-rx-class-v3-0-492d9a2586b6@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , danishanwar@ti.com Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4792; i=rogerq@kernel.org; h=from:subject:message-id; bh=yvDolz4DU7x4F3IPiMMAYL9Zyt+CPJcn+6QaEzC3KRo=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBoIzdUIOAkf0rCRrXSTkxRG28hS5N++qn988J4i xOyHqfDg3CJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCaCM3VAAKCRDSWmvTvnYw k9qjD/9Z/iAkbCUN0/VspWgI7UaDU9wW0hJxzHixu6cI+lmxUtYrWf0jEG1TnD044TGRHA459Ee Q7tagqRZnSeEF13Y90I5lDpCoAG5u5U+McpCye3rTZVIQB4kZcHqZACavwhxZMGaa/0MZkEvV8W grJ0tVMle+SGqYsNdsnUOvS2qyzGGE/9y6JVlbOinlKVpGCvTCje4RAaArdAfMFTVUd/f8Mbbs1 +TlnwNZKIn+V2kFYIt6Bvob7XEweEh/O6vCLTjR6/j+M3Bv73TR95tA93CIvLYeyD3TBSc1f5SD Rc7qFp6SNstc47vXFj9pm5wciB6kY8DWnHvzXlSdwHUkQba1LdgVeYofXurhaXrz1rW7s2anNGC 6pVm6ORghKrlw8YyC90sFzQxwnGET/tjcQBs/ujPUcPCHMzRp9oP8QCxrBKFMNhp4LK27REUPyA 1ppKMSk1Rq9L/Y+SL11sfrg6AtaEZADVX8w0zWv/EvQ4MZSKpPnlQLmaO7n7VZqZdyT0ALI1MnR dVau+8T83bL/P+GpYq/M9sv4f4BP0TdIOyPtMAA/N9Y17o7OME0uSrTluQWZ3HaaHC1KYrjTouF CbSOXFvMEcguYioNImgJ8pCVzZI0M3cvV1le7bIqKSzgOffU3e3z8JeHydU3qJL6bWa+V5N++tQ SiYqkp20leMBeag== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Add cpsw_ale_policer_set/clr_entry() helpers. So far Raw Ethernet matching based on Source/Destination address and VLAN Priority (PCP) is supported. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw_ale.c | 77 ++++++++++++++++++++++++++++++++++++++ drivers/net/ethernet/ti/cpsw_ale.h | 28 ++++++++++++++ 2 files changed, 105 insertions(+) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 49ea1c00be3d..ce216606d915 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -1746,3 +1746,80 @@ void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch) 1); } } + +#define HOST_PORT_NUM 0 + +/* Clear Policer and associated ALE table entries */ +void cpsw_ale_policer_clr_entry(struct cpsw_ale *ale, u32 policer_idx, + struct cpsw_ale_policer_cfg *cfg) +{ + cpsw_ale_policer_reset_entry(ale, policer_idx); + + /* We do not delete ALE entries that were added in set_entry + * as they might still be in use by the port e.g. VLAN id + * or port MAC address + */ + + /* clear BLOCKED in case we set it */ + if ((cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACSRC) && cfg->drop) + cpsw_ale_add_ucast(ale, cfg->src_addr, HOST_PORT_NUM, 0, 0); + + if ((cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACDST) && cfg->drop) + cpsw_ale_add_ucast(ale, cfg->dst_addr, HOST_PORT_NUM, 0, 0); +} + +int cpsw_ale_policer_set_entry(struct cpsw_ale *ale, u32 policer_idx, + struct cpsw_ale_policer_cfg *cfg) +{ + int ale_idx; + u16 ale_flags = cfg->drop ? ALE_BLOCKED : 0; + + /* A single policer can support multiple match types simultaneously + * There can be only one ALE entry per address + */ + cpsw_ale_policer_reset_entry(ale, policer_idx); + cpsw_ale_policer_read_idx(ale, policer_idx); + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACSRC) { + ale_idx = cpsw_ale_add_ucast(ale, cfg->src_addr, HOST_PORT_NUM, + ale_flags, 0); + if (ale_idx < 0) + return -ENOENT; + + /* update policer entry */ + regmap_field_write(ale->fields[POL_SRC_INDEX], ale_idx); + regmap_field_write(ale->fields[POL_SRC_MEN], 1); + } + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACDST) { + ale_idx = cpsw_ale_add_ucast(ale, cfg->dst_addr, HOST_PORT_NUM, + ale_flags, 0); + if (ale_idx < 0) + return -ENOENT; + + /* update policer entry */ + regmap_field_write(ale->fields[POL_DST_INDEX], ale_idx); + regmap_field_write(ale->fields[POL_DST_MEN], 1); + } + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_OVLAN) { + /* VLAN ID based flow routing not yet working, + * only PCP matching for now + */ + if (cfg->vid > 0) + return -EINVAL; + + regmap_field_write(ale->fields[POL_PRI_VAL], cfg->vlan_prio); + regmap_field_write(ale->fields[POL_PRI_MEN], 1); + } + + cpsw_ale_policer_write_idx(ale, policer_idx); + + /* Map to thread id provided by the config */ + if (!cfg->drop) { + cpsw_ale_policer_thread_idx_enable(ale, policer_idx, + cfg->thread_id, true); + } + + return 0; +} diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index ce59fec75774..11d333bf5a52 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -159,6 +159,30 @@ enum cpsw_ale_port_state { /* Policer */ #define CPSW_ALE_POLICER_ENTRY_WORDS 8 +/* Policer match flags */ +#define CPSW_ALE_POLICER_MATCH_PORT BIT(0) +#define CPSW_ALE_POLICER_MATCH_PRI BIT(1) +#define CPSW_ALE_POLICER_MATCH_OUI BIT(2) +#define CPSW_ALE_POLICER_MATCH_MACDST BIT(3) +#define CPSW_ALE_POLICER_MATCH_MACSRC BIT(4) +#define CPSW_ALE_POLICER_MATCH_OVLAN BIT(5) +#define CPSW_ALE_POLICER_MATCH_IVLAN BIT(6) +#define CPSW_ALE_POLICER_MATCH_ETHTYPE BIT(7) +#define CPSW_ALE_POLICER_MATCH_IPSRC BIT(8) +#define CPSW_ALE_POLICER_MATCH_IPDST BIT(9) + +struct cpsw_ale_policer_cfg { + u32 match_flags; + u16 ether_type; + u16 vid; + u8 vlan_prio; + u8 src_addr[ETH_ALEN]; + u8 dst_addr[ETH_ALEN]; + bool drop; + u64 thread_id; + int port_id; +}; + struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params); void cpsw_ale_start(struct cpsw_ale *ale); @@ -199,5 +223,9 @@ void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, bool add); void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch); void cpsw_ale_policer_reset(struct cpsw_ale *ale); +int cpsw_ale_policer_set_entry(struct cpsw_ale *ale, u32 policer_idx, + struct cpsw_ale_policer_cfg *cfg); +void cpsw_ale_policer_clr_entry(struct cpsw_ale *ale, u32 policer_idx, + struct cpsw_ale_policer_cfg *cfg); #endif From patchwork Tue May 13 12:13:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 889793 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D67E293757; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TF7/mhD1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C7408C4CEE9; Tue, 13 May 2025 12:13:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747138418; bh=bjLnaVODUDF0adr7eVsh4RznNnU2iefPfibT9eAOhzU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TF7/mhD107udPSfHJYtKZnaiDNPfXu7O+1gutkZ9MXqGd3baCGFjUTaOoD/+uDo6e gXNP3kiy2omIhw5TKMzvDzqHhfNBV32mX1YOCHWe/NrMi9G98eXrTaulHdy74LZSDw pdRa8qMWJAyRKdkrPtttbswIaWxbiS/rzHH398um4eE9UqhGIVIoGuXQLMBxI9oG+H mDLvx6l/upVVzLMeHl9V6CnWIDkSSWwDIDJ8C8GJJosPY7MjlVE2ivlEXYdQTHrqRc nNuRCAbjeEaFuSZdeGkONt0qgqkt+h5X2W1xgJzaWXftGelXAcQYLsU2JvDyMTjahW EIow90WlO0z3w== From: Roger Quadros Date: Tue, 13 May 2025 15:13:12 +0300 Subject: [PATCH net-next v3 8/9] net: ethernet: ti: am65-cpsw: add network flow classification support Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250513-am65-cpsw-rx-class-v3-8-492d9a2586b6@kernel.org> References: <20250513-am65-cpsw-rx-class-v3-0-492d9a2586b6@kernel.org> In-Reply-To: <20250513-am65-cpsw-rx-class-v3-0-492d9a2586b6@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , danishanwar@ti.com Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=13803; i=rogerq@kernel.org; h=from:subject:message-id; bh=bjLnaVODUDF0adr7eVsh4RznNnU2iefPfibT9eAOhzU=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBoIzdVNAoSqYMoYNJISPUTGOYawZNeZ824j+QTy NmYUVWKjJiJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCaCM3VQAKCRDSWmvTvnYw k1vPEADR0/6T/9xKevlEks7UDpCmEorH3zKuhliGMVeq2/cuBLf+4elDibNsO4mk+iunohf0B9Z llAOPpphjzKriLsIB1mLLzcqxqXu1pq/XS685ZZLqveGIo7X7KAQFpmNdDIR5dyAPzCRrjCqprk 63e80G8QAsqRSB/BP625f1TUAPojVV0c4BK1fI17/U+/j/z5xe0k/J9mR0nThbUZG/YuO4ojbh8 SE2gppXztVltiPlZM/3Y89kTwGiq6uCJcidURk6N2MIpibXGHn0LrC9qufEta2+b7KnFOOhb5de LQllnB2haU16dlOSZe7acmNXHXxaa/ebaWysVVFew0tTf0wiXbyLx0T6/dk/CshMP0HjQumHRHU qRnC7EnSbNcE8xkNemF2K/VMbsjP7ouhJU8v+0uxKoHzpwWi/Fmgo3Co+iRaC666CIqqCBRuOj4 Ql86SJazkNrXKmequLbO44wbsIGwQqS1Fg2XbU+Vo/HhDi43BNVxPovlrFZWwAmGGjZL/pGh6ow tHVChT9ZokOEMOpO4poYVVSoAUB3p7dioMe91E8eZNg/WFriFRw6Qr4/vNFK5VdkOHcnKi2XVpO Pmddz6xW6GGXKRvhmvZmP1ZCnYbNxl6A3/qqYsK2CkNLkQO+dgVPvTBzgdx58FpQafmp9Vwauaw HRhh00K4fcMnaTQ== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Adds support for -N/--config-nfc ethtool command for configuring RX classfiers. Currently only raw Ethernet (flow-type ether) matching is added based on source/destination addresses and VLAN Priority (PCP). The ALE policer engine is used to perform the matching and routing to a specific RX channel. The TRM doesn't mention anything about order of evaluation of the classifier rules however it does mention in [1] "if multiple classifier matches occur, the highest match with thread enable bit set will be used." [1] 3.1.4.6.1.12.3.1 Classifier to CPPI Transmit Flow ID Mapping in AM62x TRM https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/am65-cpsw-ethtool.c | 353 ++++++++++++++++++++++++++++ drivers/net/ethernet/ti/am65-cpsw-nuss.c | 3 + drivers/net/ethernet/ti/am65-cpsw-nuss.h | 15 ++ 3 files changed, 371 insertions(+) diff --git a/drivers/net/ethernet/ti/am65-cpsw-ethtool.c b/drivers/net/ethernet/ti/am65-cpsw-ethtool.c index 9032444435e9..29c3f75e3c90 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-ethtool.c +++ b/drivers/net/ethernet/ti/am65-cpsw-ethtool.c @@ -970,6 +970,357 @@ static int am65_cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coales return am65_cpsw_set_per_queue_coalesce(ndev, 0, coal); } +#define AM65_CPSW_FLOW_TYPE(f) ((f) & ~(FLOW_EXT | FLOW_MAC_EXT)) + +/* rxnfc_lock must be held */ +static struct am65_cpsw_rxnfc_rule *am65_cpsw_get_rule(struct am65_cpsw_port *port, + int location) +{ + struct am65_cpsw_rxnfc_rule *rule; + + list_for_each_entry(rule, &port->rxnfc_rules, list) { + if (rule->location == location) + return rule; + } + + return NULL; +} + +/* rxnfc_lock must be held */ +static void am65_cpsw_del_rule(struct am65_cpsw_port *port, + struct am65_cpsw_rxnfc_rule *rule) +{ + cpsw_ale_policer_clr_entry(port->common->ale, rule->location, + &rule->cfg); + list_del(&rule->list); + port->rxnfc_count--; + devm_kfree(port->common->dev, rule); +} + +/* rxnfc_lock must be held */ +static int am65_cpsw_add_rule(struct am65_cpsw_port *port, + struct am65_cpsw_rxnfc_rule *rule) +{ + struct am65_cpsw_rxnfc_rule *prev = NULL, *cur; + int ret; + + ret = cpsw_ale_policer_set_entry(port->common->ale, rule->location, + &rule->cfg); + if (ret) + return ret; + + list_for_each_entry(cur, &port->rxnfc_rules, list) { + if (cur->location >= rule->location) + break; + prev = cur; + } + + list_add(&rule->list, prev ? &prev->list : &port->rxnfc_rules); + port->rxnfc_count++; + + return 0; +} + +#define ETHER_TYPE_FULL_MASK cpu_to_be16(FIELD_MAX(U16_MAX)) +#define VLAN_TCI_FULL_MASK ETHER_TYPE_FULL_MASK + +static int am65_cpsw_rxnfc_get_rule(struct am65_cpsw_port *port, + struct ethtool_rxnfc *rxnfc) +{ + struct ethtool_rx_flow_spec *fs = &rxnfc->fs; + struct am65_cpsw_rxnfc_rule *rule; + struct cpsw_ale_policer_cfg *cfg; + + mutex_lock(&port->rxnfc_lock); + rule = am65_cpsw_get_rule(port, fs->location); + if (!rule) { + mutex_unlock(&port->rxnfc_lock); + return -ENOENT; + } + + cfg = &rule->cfg; + + /* build flowspec from policer_cfg */ + fs->flow_type = ETHER_FLOW; + fs->ring_cookie = cfg->thread_id; + + /* clear all masks. Seems to be inverted */ + eth_broadcast_addr(fs->m_u.ether_spec.h_dest); + eth_broadcast_addr(fs->m_u.ether_spec.h_source); + fs->m_u.ether_spec.h_proto = ETHER_TYPE_FULL_MASK; + fs->m_ext.vlan_tci = htons(0xFFFF); + fs->m_ext.vlan_etype = ETHER_TYPE_FULL_MASK; + fs->m_ext.data[0] = cpu_to_be32(FIELD_MAX(U32_MAX)); + fs->m_ext.data[1] = cpu_to_be32(FIELD_MAX(U32_MAX)); + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACDST) { + ether_addr_copy(fs->h_u.ether_spec.h_dest, + cfg->dst_addr); + eth_zero_addr(fs->m_u.ether_spec.h_dest); + } + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACSRC) { + ether_addr_copy(fs->h_u.ether_spec.h_source, + cfg->src_addr); + eth_zero_addr(fs->m_u.ether_spec.h_source); + } + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_OVLAN) { + fs->flow_type |= FLOW_EXT; + fs->h_ext.vlan_tci = htons(FIELD_PREP(VLAN_VID_MASK, cfg->vid) + | FIELD_PREP(VLAN_PRIO_MASK, cfg->vlan_prio)); + fs->m_ext.vlan_tci = 0; + } + + mutex_unlock(&port->rxnfc_lock); + + return 0; +} + +static int am65_cpsw_rxnfc_get_all(struct am65_cpsw_port *port, + struct ethtool_rxnfc *rxnfc, + u32 *rule_locs) +{ + struct am65_cpsw_rxnfc_rule *rule; + int count = 0; + + rxnfc->data = port->rxnfc_max; + mutex_lock(&port->rxnfc_lock); + + list_for_each_entry(rule, &port->rxnfc_rules, list) { + if (count == rxnfc->rule_cnt) { + mutex_unlock(&port->rxnfc_lock); + return -EMSGSIZE; + } + + rule_locs[count] = rule->location; + count++; + } + + mutex_unlock(&port->rxnfc_lock); + rxnfc->rule_cnt = count; + + return 0; +} + +static int am65_cpsw_get_rxnfc(struct net_device *ndev, + struct ethtool_rxnfc *rxnfc, + u32 *rule_locs) +{ + struct am65_cpsw_common *common = am65_ndev_to_common(ndev); + struct am65_cpsw_port *port = am65_ndev_to_port(ndev); + + switch (rxnfc->cmd) { + case ETHTOOL_GRXRINGS: + rxnfc->data = common->rx_ch_num_flows; + return 0; + case ETHTOOL_GRXCLSRLCNT: /* Get RX classification rule count */ + rxnfc->rule_cnt = port->rxnfc_count; + rxnfc->data = port->rxnfc_max; + return 0; + case ETHTOOL_GRXCLSRULE: /* Get RX classification rule */ + return am65_cpsw_rxnfc_get_rule(port, rxnfc); + case ETHTOOL_GRXCLSRLALL: /* Get all RX classification rules */ + return am65_cpsw_rxnfc_get_all(port, rxnfc, rule_locs); + default: + return -EOPNOTSUPP; + } +} + +/* validate the rxnfc rule and convert it to policer config */ +static int am65_cpsw_rxnfc_validate(struct am65_cpsw_port *port, + struct ethtool_rxnfc *rxnfc, + struct cpsw_ale_policer_cfg *cfg) +{ + struct ethtool_rx_flow_spec *fs = &rxnfc->fs; + struct ethhdr *eth_mask; + int flow_type; + + flow_type = AM65_CPSW_FLOW_TYPE(fs->flow_type); + memset(cfg, 0, sizeof(*cfg)); + + if (flow_type & FLOW_RSS) + return -EINVAL; + + if (fs->location == RX_CLS_LOC_ANY || + fs->location >= port->rxnfc_max) + return -EINVAL; + + if (fs->ring_cookie == RX_CLS_FLOW_DISC) + cfg->drop = true; + else if (fs->ring_cookie > AM65_CPSW_MAX_QUEUES) + return -EINVAL; + + cfg->port_id = port->port_id; + cfg->thread_id = fs->ring_cookie; + + switch (flow_type) { + case ETHER_FLOW: + eth_mask = &fs->m_u.ether_spec; + + /* etherType matching is supported by h/w but not yet here */ + if (eth_mask->h_proto) + return -EINVAL; + + /* Only support source matching addresses by full mask */ + if (is_broadcast_ether_addr(eth_mask->h_source)) { + cfg->match_flags |= CPSW_ALE_POLICER_MATCH_MACSRC; + ether_addr_copy(cfg->src_addr, + fs->h_u.ether_spec.h_source); + } + + /* Only support destination matching addresses by full mask */ + if (is_broadcast_ether_addr(eth_mask->h_dest)) { + cfg->match_flags |= CPSW_ALE_POLICER_MATCH_MACDST; + ether_addr_copy(cfg->dst_addr, + fs->h_u.ether_spec.h_dest); + } + + if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { + /* Don't yet support vlan ethertype */ + if (fs->m_ext.vlan_etype) + return -EINVAL; + + if (fs->m_ext.vlan_tci != VLAN_TCI_FULL_MASK) + return -EINVAL; + + cfg->vid = FIELD_GET(VLAN_VID_MASK, + ntohs(fs->h_ext.vlan_tci)); + cfg->vlan_prio = FIELD_GET(VLAN_PRIO_MASK, + ntohs(fs->h_ext.vlan_tci)); + cfg->match_flags |= CPSW_ALE_POLICER_MATCH_OVLAN; + } + + break; + default: + return -EINVAL; + } + + return 0; +} + +/* rxnfc_lock must be held */ +static int am65_cpsw_policer_find_match(struct am65_cpsw_port *port, + struct cpsw_ale_policer_cfg *cfg) +{ + struct am65_cpsw_rxnfc_rule *rule; + int loc = -EINVAL; + + list_for_each_entry(rule, &port->rxnfc_rules, list) { + if (!memcmp(&rule->cfg, cfg, sizeof(*cfg))) { + loc = rule->location; + break; + } + } + + mutex_unlock(&port->rxnfc_lock); + + return loc; +} + +static int am65_cpsw_rxnfc_add_rule(struct am65_cpsw_port *port, + struct ethtool_rxnfc *rxnfc) +{ + struct ethtool_rx_flow_spec *fs = &rxnfc->fs; + struct am65_cpsw_rxnfc_rule *rule; + struct cpsw_ale_policer_cfg cfg; + int loc, ret; + + if (am65_cpsw_rxnfc_validate(port, rxnfc, &cfg)) + return -EINVAL; + + /* need to check if similar rule is already present at another location, + * if yes error out + */ + mutex_lock(&port->rxnfc_lock); + loc = am65_cpsw_policer_find_match(port, &cfg); + if (loc >= 0 && loc != fs->location) { + netdev_info(port->ndev, + "rule already exists in location %d. not adding\n", + loc); + mutex_unlock(&port->rxnfc_lock); + return -EINVAL; + } + + /* delete exisiting rule */ + if (loc >= 0) { + rule = am65_cpsw_get_rule(port, loc); + if (rule) + am65_cpsw_del_rule(port, rule); + } + + rule = devm_kzalloc(port->common->dev, sizeof(*rule), GFP_KERNEL); + if (!rule) + return -ENOMEM; + + INIT_LIST_HEAD(&rule->list); + memcpy(&rule->cfg, &cfg, sizeof(cfg)); + rule->location = fs->location; + ret = am65_cpsw_add_rule(port, rule); + mutex_unlock(&port->rxnfc_lock); + + return ret; +} + +static int am65_cpsw_rxnfc_del_rule(struct am65_cpsw_port *port, + struct ethtool_rxnfc *rxnfc) +{ + struct ethtool_rx_flow_spec *fs = &rxnfc->fs; + struct am65_cpsw_rxnfc_rule *rule; + + mutex_lock(&port->rxnfc_lock); + rule = am65_cpsw_get_rule(port, fs->location); + if (!rule) { + mutex_unlock(&port->rxnfc_lock); + return -ENOENT; + } + + am65_cpsw_del_rule(port, rule); + mutex_unlock(&port->rxnfc_lock); + + return 0; +} + +void am65_cpsw_rxnfc_init(struct am65_cpsw_port *port) +{ + struct cpsw_ale *ale = port->common->ale; + + mutex_init(&port->rxnfc_lock); + INIT_LIST_HEAD(&port->rxnfc_rules); + port->rxnfc_max = ale->params.num_policers; + + /* disable all rules */ + cpsw_ale_policer_reset(ale); +} + +void am65_cpsw_rxnfc_cleanup(struct am65_cpsw_port *port) +{ + struct am65_cpsw_rxnfc_rule *rule, *tmp; + + mutex_lock(&port->rxnfc_lock); + + list_for_each_entry_safe(rule, tmp, &port->rxnfc_rules, list) + am65_cpsw_del_rule(port, rule); + + mutex_unlock(&port->rxnfc_lock); +} + +static int am65_cpsw_set_rxnfc(struct net_device *ndev, + struct ethtool_rxnfc *rxnfc) +{ + struct am65_cpsw_port *port = am65_ndev_to_port(ndev); + + netdev_info(ndev, "set_rxnfc %d\n", rxnfc->cmd); + switch (rxnfc->cmd) { + case ETHTOOL_SRXCLSRLINS: + return am65_cpsw_rxnfc_add_rule(port, rxnfc); + case ETHTOOL_SRXCLSRLDEL: + return am65_cpsw_rxnfc_del_rule(port, rxnfc); + default: + return -EOPNOTSUPP; + } +} + const struct ethtool_ops am65_cpsw_ethtool_ops_slave = { .begin = am65_cpsw_ethtool_op_begin, .complete = am65_cpsw_ethtool_op_complete, @@ -1007,4 +1358,6 @@ const struct ethtool_ops am65_cpsw_ethtool_ops_slave = { .get_mm = am65_cpsw_get_mm, .set_mm = am65_cpsw_set_mm, .get_mm_stats = am65_cpsw_get_mm_stats, + .get_rxnfc = am65_cpsw_get_rxnfc, + .set_rxnfc = am65_cpsw_set_rxnfc, }; diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 07df61f343d3..cdb83ae54656 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -2758,6 +2758,7 @@ am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) return -ENOMEM; } + am65_cpsw_rxnfc_init(port); ndev_priv = netdev_priv(port->ndev); ndev_priv->port = port; ndev_priv->msg_enable = AM65_CPSW_DEBUG; @@ -2870,6 +2871,7 @@ static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) unregister_netdev(port->ndev); free_netdev(port->ndev); port->ndev = NULL; + am65_cpsw_rxnfc_cleanup(port); } } @@ -3172,6 +3174,7 @@ static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, /* clean up ALE table */ cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); + cpsw_ale_policer_reset(cpsw->ale); if (switch_en) { dev_info(cpsw->dev, "Enable switch mode\n"); diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.h b/drivers/net/ethernet/ti/am65-cpsw-nuss.h index 61daa5db12e6..8b83c9a0965d 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.h +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.h @@ -16,6 +16,7 @@ #include #include #include "am65-cpsw-qos.h" +#include "cpsw_ale.h" struct am65_cpts; @@ -40,6 +41,12 @@ struct am65_cpsw_slave_data { struct phylink_config phylink_config; }; +struct am65_cpsw_rxnfc_rule { + struct list_head list; + unsigned int location; + struct cpsw_ale_policer_cfg cfg; +}; + struct am65_cpsw_port { struct am65_cpsw_common *common; struct net_device *ndev; @@ -59,6 +66,11 @@ struct am65_cpsw_port { struct xdp_rxq_info xdp_rxq[AM65_CPSW_MAX_QUEUES]; /* Only for suspend resume context */ u32 vid_context; + /* Classifier flows */ + struct mutex rxnfc_lock; + struct list_head rxnfc_rules; + int rxnfc_count; + int rxnfc_max; }; enum am65_cpsw_tx_buf_type { @@ -229,4 +241,7 @@ int am65_cpsw_nuss_update_tx_rx_chns(struct am65_cpsw_common *common, bool am65_cpsw_port_dev_check(const struct net_device *dev); +void am65_cpsw_rxnfc_init(struct am65_cpsw_port *port); +void am65_cpsw_rxnfc_cleanup(struct am65_cpsw_port *port); + #endif /* AM65_CPSW_NUSS_H_ */