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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id d23sm4381451ioj.22.2017.06.30.10.42.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 30 Jun 2017 10:42:02 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Subject: [PATCH 1/5] coresight: Correct buffer lost increment Date: Fri, 30 Jun 2017 11:41:55 -0600 Message-Id: <1498844519-8845-2-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498844519-8845-1-git-send-email-mathieu.poirier@linaro.org> References: <1498844519-8845-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Many conditions may cause synchronisation to be lost when updating the perf ring buffer but the end result is still the same: synchronisation is lost. As such there is no need to increment the lost count for each condition, just once will suffice. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 10 +++++++--- drivers/hwtracing/coresight/coresight-tmc-etf.c | 8 ++++++-- 2 files changed, 13 insertions(+), 5 deletions(-) -- 2.7.4 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index d5b96423e1a5..d9c233135d6d 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -353,6 +353,7 @@ static void etb_update_buffer(struct coresight_device *csdev, struct perf_output_handle *handle, void *sink_config) { + bool lost = false; int i, cur; u8 *buf_ptr; u32 read_ptr, write_ptr, capacity; @@ -384,7 +385,7 @@ static void etb_update_buffer(struct coresight_device *csdev, (unsigned long)write_ptr); write_ptr &= ~(ETB_FRAME_SIZE_WORDS - 1); - perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); + lost = true; } /* @@ -395,7 +396,7 @@ static void etb_update_buffer(struct coresight_device *csdev, */ status = readl_relaxed(drvdata->base + ETB_STATUS_REG); if (status & ETB_STATUS_RAM_FULL) { - perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); + lost = true; to_read = capacity; read_ptr = write_ptr; } else { @@ -428,9 +429,12 @@ static void etb_update_buffer(struct coresight_device *csdev, if (read_ptr > (drvdata->buffer_depth - 1)) read_ptr -= drvdata->buffer_depth; /* let the decoder know we've skipped ahead */ - perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); + lost = true; } + if (lost) + perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); + /* finally tell HW where we want to start reading from */ writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index e3b9fb82eb8d..2e0fb5b9372c 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -369,6 +369,7 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev, struct perf_output_handle *handle, void *sink_config) { + bool lost = false; int i, cur; u32 *buf_ptr; u32 read_ptr, write_ptr; @@ -397,7 +398,7 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev, */ status = readl_relaxed(drvdata->base + TMC_STS); if (status & TMC_STS_FULL) { - perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); + lost = true; to_read = drvdata->size; } else { to_read = CIRC_CNT(write_ptr, read_ptr, drvdata->size); @@ -442,9 +443,12 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev, read_ptr -= drvdata->size; /* Tell the HW */ writel_relaxed(read_ptr, drvdata->base + TMC_RRP); - perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); + lost = true; } + if (lost) + perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); + cur = buf->cur; offset = buf->offset; From patchwork Fri Jun 30 17:41:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 106762 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp2614473qge; Fri, 30 Jun 2017 10:43:38 -0700 (PDT) X-Received: by 10.99.154.18 with SMTP id o18mr21935298pge.251.1498844618837; Fri, 30 Jun 2017 10:43:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498844618; cv=none; d=google.com; s=arc-20160816; b=FFTgTW7IJOYUe+AorjoZsQ6sWxB/qQF+zzRnpUAvHfa4gAvRwJtDowliUQqPC/9qmI x3VWqbudF02Bm3EVgFlBArpDQOQ7Yss13YFlqQodqyvmbZ27uk8kAmuQKq15d9lZcAxN ZnqbMdZi25bTb3kyyscqLlAleumI6BElYLPMiROPbb4rrFs4uLbTIuV3uZdvVbHH5tgc XURCCxZGc6NaQXVccj9MxoLGwATTwEn1VJz+MljbMoKuJNJ3F+ifyG597X1C7nlkY5vs Unoivt2ZMIGmqNWc/hODbPT4ARaRMPaf8z9zamVPntYCnlSbYkdO9ah8+uFujteMqhXa gJjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=CXQDoW7VxjFlQN2bFUHlbxUVb8/hzwdlNyS5tnTNtqI=; b=qe4L1yI8yEWjsJ881j8DhyHK+QmuCQcavlmgBaCYaAJl73AYFQWbMMzvmSav4k/wEX PkjkRRQCXyxCJnDIKvnQAOtHhYNM/3wGjfFs5eioKAaJNTYWY1lJcj+96jucCgwPWVcs XuEq+HCI7SK/ydU0l4viUamzRIc0IFgLzNduRVrsEyBXuuoZz7Bw4dvmFiXTgfWQMjJP nD5srAB05zL4zQmDy/euQhh9NYXR6WVlWFTdyZyeqfxt+8vD1hruXpBje1WeSeqrJSVS kvhlEdIoZUs7oy8X/BzNdLwYiFEI0KCA20ziUXDOvoN8bsxGD9gHyyM1+jiXbGIU3srZ CAcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=aVTlY2SL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id d23sm4381451ioj.22.2017.06.30.10.42.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 30 Jun 2017 10:42:03 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Subject: [PATCH 2/5] coresight: etb10: Remove useless conversion to LE Date: Fri, 30 Jun 2017 11:41:56 -0600 Message-Id: <1498844519-8845-3-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498844519-8845-1-git-send-email-mathieu.poirier@linaro.org> References: <1498844519-8845-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Internal CoreSight components are rendering trace data in little-endian format. As such there is no need to convert the data once more, hence removing the extra step. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) -- 2.7.4 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index d9c233135d6d..50f4846e6271 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -233,10 +233,8 @@ static void etb_dump_hw(struct etb_drvdata *drvdata) for (i = 0; i < depth; i++) { read_data = readl_relaxed(drvdata->base + ETB_RAM_READ_DATA_REG); - *buf_ptr++ = read_data >> 0; - *buf_ptr++ = read_data >> 8; - *buf_ptr++ = read_data >> 16; - *buf_ptr++ = read_data >> 24; + *(u32 *)buf_ptr = read_data; + buf_ptr += 4; } if (frame_off) { @@ -444,10 +442,8 @@ static void etb_update_buffer(struct coresight_device *csdev, buf_ptr = buf->data_pages[cur] + offset; read_data = readl_relaxed(drvdata->base + ETB_RAM_READ_DATA_REG); - *buf_ptr++ = read_data >> 0; - *buf_ptr++ = read_data >> 8; - *buf_ptr++ = read_data >> 16; - *buf_ptr++ = read_data >> 24; + *(u32 *)buf_ptr = read_data; + buf_ptr += 4; offset += 4; if (offset >= PAGE_SIZE) { From patchwork Fri Jun 30 17:41:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 106759 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp2613468qge; Fri, 30 Jun 2017 10:42:28 -0700 (PDT) X-Received: by 10.99.181.7 with SMTP id y7mr1141688pge.212.1498844548288; Fri, 30 Jun 2017 10:42:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498844548; cv=none; d=google.com; s=arc-20160816; b=aGiT8tN1kAh1/hrIHvb/9FUQB5X7VfUpRP2Nd17FXdqZ38pPIBBNDIkt6vuu0HuLTF jyXs8RJCak4xWUCeqcfyMIDVUGvY3LwB/PMks3NsylfL4I1ZRkeS6hfNGchw1cp6f/YT aFJWR8wSgiPt/S8EUFkqolV0z8C4i6aClBxUtRUp9uoJ3/geBpKJ1dn9pKcc2/u7lnfC t2sgLVABN4ELpFY3es1xouAcqoSCjBQZduAA8UofypWuN2J45oEv64B33fGKfB6QdEbL lYqZrYz9eKeZoZC858t3dwQAK6GQFYYBDjUqnVdH2zXNpiOTC2GV8NzErjUwMizDgleV qZFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=ZvUjrZ6h/7tVU9pQj41ekRgCPhP8nH6bMsBFBRcFeT8=; b=YeEYM7eJmd6hA7O9+WV7kO5vxBo5JGZ+PPLZIQdobmfmrUeS3VCjTrP+yMrFy3pbae xkgACiasAkyKnANDpPefxz8Fjv9HBttegEm9CjGBk3APL1w2MKMfLGOrixaXzbuIX8jz 1NGVyF+SSf65UQz1qIn8yArxXxa8OusEchcvNf6eShTRTCWI/jniRteyQRzpriZR8eA6 Kt81st6rVFatUchamBVIJ5ak3eWNd2I4Y8/86Nj5WuXzNBVQUe37NkMTkYUkkKZgs/12 9pfcnvM9nZMTlaXrd7kruyT4Fvg+E/Yy7OB1PC0wjzs4w/HnlQc9O2TxFhU4pfh697z2 veXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=XwNsoY+z; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id d23sm4381451ioj.22.2017.06.30.10.42.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 30 Jun 2017 10:42:04 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Subject: [PATCH 3/5] coresight: Add barrier packet for synchronisation Date: Fri, 30 Jun 2017 11:41:57 -0600 Message-Id: <1498844519-8845-4-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498844519-8845-1-git-send-email-mathieu.poirier@linaro.org> References: <1498844519-8845-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When a buffer overflow happens the synchronisation patckets usually present at the beginning of the buffer are lost, a situation that prevents the decoder from knowing the context of the traces being decoded. This patch adds a barrier packet to be used by sink IPs when a buffer overflow condition is detected. These barrier packets are then used by the decoding library as markers to force re-synchronisation. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 22 +++++++++++++++++++-- drivers/hwtracing/coresight/coresight-priv.h | 2 ++ drivers/hwtracing/coresight/coresight-tmc-etf.c | 26 ++++++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tmc-etr.c | 12 ++++++++++++ drivers/hwtracing/coresight/coresight.c | 8 ++++++++ 5 files changed, 67 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 50f4846e6271..42360306f049 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -200,8 +200,10 @@ static void etb_disable_hw(struct etb_drvdata *drvdata) static void etb_dump_hw(struct etb_drvdata *drvdata) { + bool lost = false; int i; u8 *buf_ptr; + const u32 *barrier; u32 read_data, depth; u32 read_ptr, write_ptr; u32 frame_off, frame_endoff; @@ -223,16 +225,24 @@ static void etb_dump_hw(struct etb_drvdata *drvdata) } if ((readl_relaxed(drvdata->base + ETB_STATUS_REG) - & ETB_STATUS_RAM_FULL) == 0) + & ETB_STATUS_RAM_FULL) == 0) { writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); - else + } else { writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER); + lost = true; + } depth = drvdata->buffer_depth; buf_ptr = drvdata->buf; + barrier = barrier_pkt; for (i = 0; i < depth; i++) { read_data = readl_relaxed(drvdata->base + ETB_RAM_READ_DATA_REG); + if (lost && *barrier) { + read_data = *barrier; + barrier++; + } + *(u32 *)buf_ptr = read_data; buf_ptr += 4; } @@ -354,6 +364,7 @@ static void etb_update_buffer(struct coresight_device *csdev, bool lost = false; int i, cur; u8 *buf_ptr; + const u32 *barrier; u32 read_ptr, write_ptr, capacity; u32 status, read_data, to_read; unsigned long offset; @@ -438,10 +449,17 @@ static void etb_update_buffer(struct coresight_device *csdev, cur = buf->cur; offset = buf->offset; + barrier = barrier_pkt; + for (i = 0; i < to_read; i += 4) { buf_ptr = buf->data_pages[cur] + offset; read_data = readl_relaxed(drvdata->base + ETB_RAM_READ_DATA_REG); + if (lost && *barrier) { + read_data = *barrier; + barrier++; + } + *(u32 *)buf_ptr = read_data; buf_ptr += 4; diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 5f662d82052c..3e25b1dd1a1a 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -56,6 +56,8 @@ static ssize_t name##_show(struct device *_dev, \ } \ static DEVICE_ATTR_RO(name) +extern const u32 barrier_pkt[5]; + enum etm_addr_type { ETM_ADDR_TYPE_NONE, ETM_ADDR_TYPE_SINGLE, diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 2e0fb5b9372c..d189b28bd5c4 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -43,17 +43,34 @@ static void tmc_etb_enable_hw(struct tmc_drvdata *drvdata) static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata) { + bool lost = false; char *bufp; - u32 read_data; + const u32 *barrier; + u32 read_data, status; int i; + /* + * Get a hold of the status register and see if a wrap around + * has occurred. + */ + status = readl_relaxed(drvdata->base + TMC_STS); + if (status & TMC_STS_FULL) + lost = true; + bufp = drvdata->buf; drvdata->len = 0; + barrier = barrier_pkt; while (1) { for (i = 0; i < drvdata->memwidth; i++) { read_data = readl_relaxed(drvdata->base + TMC_RRD); if (read_data == 0xFFFFFFFF) return; + + if (lost && *barrier) { + read_data = *barrier; + barrier++; + } + memcpy(bufp, &read_data, 4); bufp += 4; drvdata->len += 4; @@ -371,6 +388,7 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev, { bool lost = false; int i, cur; + const u32 *barrier; u32 *buf_ptr; u32 read_ptr, write_ptr; u32 status, to_read; @@ -451,12 +469,18 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev, cur = buf->cur; offset = buf->offset; + barrier = barrier_pkt; /* for every byte to read */ for (i = 0; i < to_read; i += 4) { buf_ptr = buf->data_pages[cur] + offset; *buf_ptr = readl_relaxed(drvdata->base + TMC_RRD); + if (lost && *barrier) { + *buf_ptr = *barrier; + barrier++; + } + offset += 4; if (offset >= PAGE_SIZE) { offset = 0; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 5d312699b3b9..b8fb981de7b6 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -59,6 +59,8 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata) static void tmc_etr_dump_hw(struct tmc_drvdata *drvdata) { + const u32 *barrier; + u32 *temp; u32 rwp, val; rwp = readl_relaxed(drvdata->base + TMC_RWP); @@ -71,6 +73,16 @@ static void tmc_etr_dump_hw(struct tmc_drvdata *drvdata) if (val & TMC_STS_FULL) { drvdata->buf = drvdata->vaddr + rwp - drvdata->paddr; drvdata->len = drvdata->size; + + barrier = barrier_pkt; + temp = (u32 *)drvdata->buf; + + while (*barrier) { + *temp = *barrier; + temp++; + barrier++; + } + } else { drvdata->buf = drvdata->vaddr; drvdata->len = rwp - drvdata->paddr; diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index 6a0202b7384f..b8091bef21dc 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -53,6 +53,14 @@ static DEFINE_PER_CPU(struct list_head *, tracer_path); */ static struct list_head *stm_path; +/* + * When losing synchronisation a new barrier packet needs to be inserted at the + * beginning of the data collected in a buffer. That way the decoder knows that + * it needs to look for another sync sequence. + */ +const u32 barrier_pkt[5] = {0x7fffffff, 0x7fffffff, + 0x7fffffff, 0x7fffffff, 0x0}; + static int coresight_id_match(struct device *dev, void *data) { int trace_id, i_trace_id; From patchwork Fri Jun 30 17:41:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 106760 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp2613479qge; Fri, 30 Jun 2017 10:42:29 -0700 (PDT) X-Received: by 10.98.192.204 with SMTP id g73mr23236918pfk.26.1498844549263; Fri, 30 Jun 2017 10:42:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498844549; cv=none; d=google.com; s=arc-20160816; b=S9LhKgKSD61AfixqkMkwANgCJ/nXYzV4/dtMgl6CV29IaZLEv2Kv2fKTeBZnRvFNaE Qe3gl/ek5M661Ot70Rpdm+o9zOC4ZsNjPDf9euJGPdN75IWpjSOzFAeGPxDpoNvMmRu1 wPGJ2+OiLkHUUS6Nl30O5QBTXBGFCTIqK6ydHcSPmAubc/271QxxjU2xfRU0C8AAW+8s YoOsKN+6lWTgpFe6q5IH76t0GgJL6Mfcb4RtObQwtAVECqv4fVnbELvDc0tQoKFoF4RP O7CEls05C9375uBlmQSwMhsm19ItgD3/GgIaG1KLMJ3FzKjiOJIDJK1BLFzLBbzozAvC AVPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=pmhkwVdEuAIaGm/mPToB6JoRcAsRGADAFEXdMsqjieA=; b=A84M+RUts/jYgUNHysGCjJdT1nh29HCl+pZ7pz/aFKzVz1IZJW//PaVRtKP5istQz2 dBai4zFJjJuMwGgUEcMNIvhxuJc7za5T5misfxjFMXCpbWnp01C8PoNcPzd5TTaR4JS5 Jv3p8Xs/uRwIIYS3JzvYkGCDlq09qHgVDAg691IO2n6wexMxcST7rmaBh/AKGxo9XSSc FvTsXy6xNuSJPaRNdq64ovB9T4q7BURffK4bSMgMz7N1OVeRcWa+dM9JnqT4KWOXB2zx KRkAeAvT1+g6x8lh9smjPGRxnn1vR98vzwvGuDG8lBq/Qi8osEXwxPIQhHcflBcWzmJ6 +kWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=J0YP3fPm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id d23sm4381451ioj.22.2017.06.30.10.42.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 30 Jun 2017 10:42:05 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Subject: [PATCH 4/5] coresight: etb10: Move etb_disable_hw() outside of lock Date: Fri, 30 Jun 2017 11:41:58 -0600 Message-Id: <1498844519-8845-5-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498844519-8845-1-git-send-email-mathieu.poirier@linaro.org> References: <1498844519-8845-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Function etb_disable_hw() is already taking care of unlocking and locking the coresight access register and as such doesn't need to be placed within the unlock/lock of function etb_update_buffer(). Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 42360306f049..d0d186575c5d 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -376,8 +376,8 @@ static void etb_update_buffer(struct coresight_device *csdev, capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS; - CS_UNLOCK(drvdata->base); etb_disable_hw(drvdata); + CS_UNLOCK(drvdata->base); /* unit is in words, not bytes */ read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER); From patchwork Fri Jun 30 17:41:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 106761 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp2613686qge; Fri, 30 Jun 2017 10:42:43 -0700 (PDT) X-Received: by 10.99.184.25 with SMTP id p25mr22248481pge.22.1498844562797; Fri, 30 Jun 2017 10:42:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498844562; cv=none; d=google.com; s=arc-20160816; b=S8f9XCMYrnGXntTVwA9/2a08qKD4aPo0uXZ3H1BetvhRYhVETBeA5fkaLEli5aLnP5 YZopQ69mMDEnSXO/46xVS9rq2taNi+eNjPkJ+ZLm4AyPSeUxP3JPtU2kmUF8xiNDQ2hG zSwFXJlKnp1+M0dIgE2jkd8QLVxdzLeMubNQFh8rSgAncsayRApwSqSzmst8hP8fUfmC ddqz2f28/+gzoMMIK1ItGfqKb2YC0fAJphCKBgP8bxvMg3WnbWdrc85/h/T1ibHKXp5/ 2Y3I3NV1POG1evxtHC7N/qMPnxIjvATrfBIQXN1NTjMvQTpxNsWIBItjKv38QNeFBEvJ 6P1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=t8v32PRpXEL79rkfJvJc7h31HjN97kPc9P8wf+sZeHY=; b=cG/zgnTY/Z2Dh0D+mFd6ObDzgwwd7WePb3KYk1EWsZHijmIix9/r1JRbYtBm8ht1zD p2gqUxrZjgxFg/d0cC2jeRff7Duuq+FD6WXxnTxFWHTeCBD5P7Mp7ASwZzhNBdePnR2F Xie9bGs9ygb/vujcIlXdkLvD3R3u+ZiM646YPh4675l+SXU1dlfMo49247k5wkJXNoZ/ nvdiMTOv/0nIk3k2rspjKpS5R03/K461X3lZaJ+XmyqYu2Ud33Y3PgtvlLMPK+b5003Z 5TpNktEgpek0fhfIT7Uocu7A9JBJltQ4u1eRVVGvj/UksNAaq+mmfV5BuiLxRwlfGp3n qbpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=YGWEcnTY; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id d23sm4381451ioj.22.2017.06.30.10.42.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 30 Jun 2017 10:42:06 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Subject: [PATCH 5/5] coresight: etm3x: Set synchronisation frequencty to TRM default Date: Fri, 30 Jun 2017 11:41:59 -0600 Message-Id: <1498844519-8845-6-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498844519-8845-1-git-send-email-mathieu.poirier@linaro.org> References: <1498844519-8845-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Register ETMSYNCFR holds the number of by that need to be generated before periodic synchronisation packets are inserted in the trace stream. By zeroing out the config structure, the current code effectively disable periodic synchronization. This patch simply initialise the recommended value for this register as specified in the technical reference manual. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm3x.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.7.4 diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index a51b6b64ecdf..b67122acea7a 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -243,6 +243,8 @@ void etm_set_default(struct etm_config *config) } config->ctxid_mask = 0x0; + /* Setting default to 1024 as per TRM recommendation */ + config->sync_freq = 0x400; } void etm_config_trace_mode(struct etm_config *config)