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Fri, 09 May 2025 04:06:55 -0700 (PDT) Received: from ho-tower-lan.lan ([77.81.75.81]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58ecadfsm2914797f8f.22.2025.05.09.04.06.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 May 2025 04:06:55 -0700 (PDT) From: James Clark Date: Fri, 09 May 2025 12:05:48 +0100 Subject: [PATCH 01/14] spi: spi-fsl-dspi: Define regmaps per device Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250509-james-nxp-spi-v1-1-32bfcd2fea11@linaro.org> References: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> In-Reply-To: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> To: Vladimir Oltean , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , larisa.grigore@nxp.com, arnd@linaro.org, andrei.stefanescu@nxp.com, dan.carpenter@linaro.org Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Clark X-Mailer: b4 0.14.0 Refactor the regmaps so they can be defined per device rather than programmatically. This will allow us to add two new regmaps for S32G in a later commit. No functional changes. Signed-off-by: James Clark Reviewed-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 121 ++++++++++++++++++++++++--------------------- 1 file changed, 66 insertions(+), 55 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 067c954cb6ea..31ea8ce81e98 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -121,6 +121,7 @@ struct fsl_dspi_devtype_data { enum dspi_trans_mode trans_mode; u8 max_clock_factor; int fifo_size; + const struct regmap_config *regmap; }; enum { @@ -136,60 +137,123 @@ enum { VF610, }; +static const struct regmap_range dspi_volatile_ranges[] = { + regmap_reg_range(SPI_MCR, SPI_TCR), + regmap_reg_range(SPI_SR, SPI_SR), + regmap_reg_range(SPI_PUSHR, SPI_RXFR3), +}; + +static const struct regmap_access_table dspi_volatile_table = { + .yes_ranges = dspi_volatile_ranges, + .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges), +}; + +static const struct regmap_range dspi_xspi_volatile_ranges[] = { + regmap_reg_range(SPI_MCR, SPI_TCR), + regmap_reg_range(SPI_SR, SPI_SR), + regmap_reg_range(SPI_PUSHR, SPI_RXFR3), + regmap_reg_range(SPI_SREX, SPI_SREX), +}; + +static const struct regmap_access_table dspi_xspi_volatile_table = { + .yes_ranges = dspi_xspi_volatile_ranges, + .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges), +}; + +enum { + DSPI_REGMAP, + DSPI_XSPI_REGMAP, + DSPI_PUSHR +}; + +static const struct regmap_config dspi_regmap_config[] = { + [DSPI_REGMAP] = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0x88, + .volatile_table = &dspi_volatile_table + }, + [DSPI_XSPI_REGMAP] = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0x13c, + .volatile_table = &dspi_xspi_volatile_table + }, + [DSPI_PUSHR] = { + .name = "pushr", + .reg_bits = 16, + .val_bits = 16, + .reg_stride = 2, + .max_register = 0x2 + } +}; + static const struct fsl_dspi_devtype_data devtype_data[] = { [VF610] = { .trans_mode = DSPI_DMA_MODE, .max_clock_factor = 2, .fifo_size = 4, + .regmap = &dspi_regmap_config[DSPI_REGMAP] }, [LS1021A] = { /* Has A-011218 DMA erratum */ .trans_mode = DSPI_XSPI_MODE, .max_clock_factor = 8, .fifo_size = 4, + .regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP] }, [LS1012A] = { /* Has A-011218 DMA erratum */ .trans_mode = DSPI_XSPI_MODE, .max_clock_factor = 8, .fifo_size = 16, + .regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP] }, [LS1028A] = { .trans_mode = DSPI_XSPI_MODE, .max_clock_factor = 8, .fifo_size = 4, + .regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP] }, [LS1043A] = { /* Has A-011218 DMA erratum */ .trans_mode = DSPI_XSPI_MODE, .max_clock_factor = 8, .fifo_size = 16, + .regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP] }, [LS1046A] = { /* Has A-011218 DMA erratum */ .trans_mode = DSPI_XSPI_MODE, .max_clock_factor = 8, .fifo_size = 16, + .regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP] }, [LS2080A] = { .trans_mode = DSPI_XSPI_MODE, .max_clock_factor = 8, .fifo_size = 4, + .regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP] }, [LS2085A] = { .trans_mode = DSPI_XSPI_MODE, .max_clock_factor = 8, .fifo_size = 4, + .regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP] }, [LX2160A] = { .trans_mode = DSPI_XSPI_MODE, .max_clock_factor = 8, .fifo_size = 4, + .regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP] }, [MCF5441X] = { .trans_mode = DSPI_DMA_MODE, .max_clock_factor = 8, .fifo_size = 16, + .regmap = &dspi_regmap_config[DSPI_REGMAP] }, }; @@ -1167,54 +1231,6 @@ static int dspi_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume); -static const struct regmap_range dspi_volatile_ranges[] = { - regmap_reg_range(SPI_MCR, SPI_TCR), - regmap_reg_range(SPI_SR, SPI_SR), - regmap_reg_range(SPI_PUSHR, SPI_RXFR3), -}; - -static const struct regmap_access_table dspi_volatile_table = { - .yes_ranges = dspi_volatile_ranges, - .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges), -}; - -static const struct regmap_config dspi_regmap_config = { - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .max_register = 0x88, - .volatile_table = &dspi_volatile_table, -}; - -static const struct regmap_range dspi_xspi_volatile_ranges[] = { - regmap_reg_range(SPI_MCR, SPI_TCR), - regmap_reg_range(SPI_SR, SPI_SR), - regmap_reg_range(SPI_PUSHR, SPI_RXFR3), - regmap_reg_range(SPI_SREX, SPI_SREX), -}; - -static const struct regmap_access_table dspi_xspi_volatile_table = { - .yes_ranges = dspi_xspi_volatile_ranges, - .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges), -}; - -static const struct regmap_config dspi_xspi_regmap_config[] = { - { - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .max_register = 0x13c, - .volatile_table = &dspi_xspi_volatile_table, - }, - { - .name = "pushr", - .reg_bits = 16, - .val_bits = 16, - .reg_stride = 2, - .max_register = 0x2, - }, -}; - static int dspi_init(struct fsl_dspi *dspi) { unsigned int mcr; @@ -1272,7 +1288,6 @@ static int dspi_target_abort(struct spi_controller *host) static int dspi_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; - const struct regmap_config *regmap_config; struct fsl_dspi_platform_data *pdata; struct spi_controller *ctlr; int ret, cs_num, bus_num = -1; @@ -1355,11 +1370,7 @@ static int dspi_probe(struct platform_device *pdev) goto out_ctlr_put; } - if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) - regmap_config = &dspi_xspi_regmap_config[0]; - else - regmap_config = &dspi_regmap_config; - dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config); 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Fri, 09 May 2025 04:06:57 -0700 (PDT) Received: from ho-tower-lan.lan ([77.81.75.81]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58ecadfsm2914797f8f.22.2025.05.09.04.06.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 May 2025 04:06:56 -0700 (PDT) From: James Clark Date: Fri, 09 May 2025 12:05:49 +0100 Subject: [PATCH 02/14] spi: spi-fsl-dspi: Re-use one volatile regmap for both device types Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250509-james-nxp-spi-v1-2-32bfcd2fea11@linaro.org> References: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> In-Reply-To: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> To: Vladimir Oltean , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , larisa.grigore@nxp.com, arnd@linaro.org, andrei.stefanescu@nxp.com, dan.carpenter@linaro.org Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Clark X-Mailer: b4 0.14.0 max_register overrides anything in the volatile ranges, so we can get away with sharing the same one for both types. In a later commit we'll add more devices and also read/write ranges which also override volatile ranges so this avoids adding even more duplication. No functional changes. Signed-off-by: James Clark --- drivers/spi/spi-fsl-dspi.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 31ea8ce81e98..cb0e55a49eea 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -141,6 +141,7 @@ static const struct regmap_range dspi_volatile_ranges[] = { regmap_reg_range(SPI_MCR, SPI_TCR), regmap_reg_range(SPI_SR, SPI_SR), regmap_reg_range(SPI_PUSHR, SPI_RXFR3), + regmap_reg_range(SPI_SREX, SPI_SREX) }; static const struct regmap_access_table dspi_volatile_table = { @@ -148,18 +149,6 @@ static const struct regmap_access_table dspi_volatile_table = { .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges), }; -static const struct regmap_range dspi_xspi_volatile_ranges[] = { - regmap_reg_range(SPI_MCR, SPI_TCR), - regmap_reg_range(SPI_SR, SPI_SR), - regmap_reg_range(SPI_PUSHR, SPI_RXFR3), - regmap_reg_range(SPI_SREX, SPI_SREX), -}; - -static const struct regmap_access_table dspi_xspi_volatile_table = { - .yes_ranges = dspi_xspi_volatile_ranges, - .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges), -}; 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Fri, 09 May 2025 04:06:58 -0700 (PDT) Received: from ho-tower-lan.lan ([77.81.75.81]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58ecadfsm2914797f8f.22.2025.05.09.04.06.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 May 2025 04:06:58 -0700 (PDT) From: James Clark Date: Fri, 09 May 2025 12:05:50 +0100 Subject: [PATCH 03/14] spi: spi-fsl-dspi: restrict register range for regmap access Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250509-james-nxp-spi-v1-3-32bfcd2fea11@linaro.org> References: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> In-Reply-To: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> To: Vladimir Oltean , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , larisa.grigore@nxp.com, arnd@linaro.org, andrei.stefanescu@nxp.com, dan.carpenter@linaro.org Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xulin Sun , James Clark X-Mailer: b4 0.14.0 From: Larisa Grigore DSPI registers are NOT continuous, some registers are reserved and accessing them from userspace will trigger external abort, add regmap register access table to avoid below abort: Internal error: synchronous external abort: 96000210 1 PREEMPT SMP Modules linked in: fuse dummy tun hse sch_fq_codel openvswitch nsh nf_conncount nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 CPU: 2 PID: 18231 Comm: read_all Not tainted 5.2.33-yocto-standard #1 Hardware name: Freescale S32G275 (DT) pstate: 20000085 (nzCv daIf -PAN -UAO) pc : regmap_mmio_read32le+0x24/0x48 lr : regmap_mmio_read+0x48/0x70 sp : ffffff801123bb70 x29: ffffff801123bb70 x28: ffffffc873b5c000 x27: ffffff8010b408f0 x26: 0000000000000001 x25: 000000000000013c x24: ffffff801123be40 x23: 00000000000003ff x22: ffffff801123bcfc x21: ffffff801123bcfc x20: ffffffc873a9e500 x19: 0000000000000024 x18: 0000000000000020 x17: 0000000000000000 x16: 0000000000000000 x15: ffffffc876189160 x14: 0000000000000003 x13: ffffffc873bf73ff x12: ffffffc873bf707e x11: 0000000000000000 x10: 0000000000000000 x9 : 0000000000000000 x8 : ffffffc83fca4e00 x7 : 000000000000000f x6 : ffffffc873bf7083 x5 : 00000000fffffff9 x4 : 0000000000000002 x3 : ffffff801061f058 x2 : ffffff801061ee18 x1 : 0000000000000024 x0 : ffffff8011490024 Call trace: regmap_mmio_read32le+0x24/0x48 regmap_mmio_read+0x48/0x70 _regmap_bus_reg_read+0x38/0x48 _regmap_read+0x68/0x1b0 regmap_read+0x50/0x78 regmap_read_debugfs+0x120/0x338 regmap_map_read_file+0x44/0x58 full_proxy_read+0x68/0x98 __vfs_read+0x48/0x90 vfs_read+0xb0/0x130 ksys_read+0x7c/0x108 __arm64_sys_read+0x24/0x30 el0_svc_common.constprop.0+0x74/0x168 el0_svc_handler+0x70/0x90 el0_svc+0x8/0xc Co-developed-by: Xulin Sun Signed-off-by: Xulin Sun Signed-off-by: Larisa Grigore Signed-off-by: James Clark --- drivers/spi/spi-fsl-dspi.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index cb0e55a49eea..701cf56d28e7 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ // // Copyright 2013 Freescale Semiconductor, Inc. -// Copyright 2020 NXP +// Copyright 2020-2025 NXP // // Freescale DSPI driver // This file contains a driver for the Freescale DSPI @@ -137,6 +137,20 @@ enum { VF610, }; +static const struct regmap_range dspi_yes_ranges[] = { + regmap_reg_range(SPI_MCR, SPI_MCR), + regmap_reg_range(SPI_TCR, SPI_CTAR(3)), + regmap_reg_range(SPI_SR, SPI_TXFR3), + regmap_reg_range(SPI_RXFR0, SPI_RXFR3), + regmap_reg_range(SPI_CTARE(0), SPI_CTARE(3)), + regmap_reg_range(SPI_SREX, SPI_SREX), +}; + +static const struct regmap_access_table dspi_access_table = { + .yes_ranges = dspi_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(dspi_yes_ranges), +}; + static const struct regmap_range dspi_volatile_ranges[] = { regmap_reg_range(SPI_MCR, SPI_TCR), regmap_reg_range(SPI_SR, SPI_SR), @@ -161,14 +175,18 @@ static const struct regmap_config dspi_regmap_config[] = { .val_bits = 32, .reg_stride = 4, .max_register = 0x88, - .volatile_table = &dspi_volatile_table + .volatile_table = &dspi_volatile_table, + .wr_table = &dspi_access_table, + .rd_table = &dspi_access_table }, [DSPI_XSPI_REGMAP] = { .reg_bits = 32, .val_bits = 32, .reg_stride = 4, .max_register = 0x13c, - .volatile_table = &dspi_volatile_table + .volatile_table = &dspi_volatile_table, + .wr_table = &dspi_access_table, + .rd_table = &dspi_access_table }, [DSPI_PUSHR] = { .name = "pushr", From patchwork Fri May 9 11:05:51 2025 Content-Type: text/plain; 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Fri, 09 May 2025 04:07:00 -0700 (PDT) Received: from ho-tower-lan.lan ([77.81.75.81]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58ecadfsm2914797f8f.22.2025.05.09.04.06.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 May 2025 04:06:59 -0700 (PDT) From: James Clark Date: Fri, 09 May 2025 12:05:51 +0100 Subject: [PATCH 04/14] spi: spi-fsl-dspi: Add config and regmaps for S32G platforms Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250509-james-nxp-spi-v1-4-32bfcd2fea11@linaro.org> References: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> In-Reply-To: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> To: Vladimir Oltean , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , larisa.grigore@nxp.com, arnd@linaro.org, andrei.stefanescu@nxp.com, dan.carpenter@linaro.org Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Clark X-Mailer: b4 0.14.0 From: Larisa Grigore S32G adds SPI_{T,R}XFR4 and extends SPI_CTAR registers to 5. Add the new regmaps, configs and bits. dspi_volatile_ranges gets SPI_{T,R}XFR4 added which affects all platforms, however they are further limited by dspi_yes_ranges. Signed-off-by: Larisa Grigore Signed-off-by: James Clark --- drivers/spi/spi-fsl-dspi.c | 39 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 701cf56d28e7..df6f85122bfe 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -35,7 +35,7 @@ #define SPI_TCR 0x08 #define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16) -#define SPI_CTAR(x) (0x0c + (((x) & GENMASK(1, 0)) * 4)) +#define SPI_CTAR(x) (0x0c + (((x) & GENMASK(2, 0)) * 4)) #define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27)) #define SPI_CTAR_CPOL BIT(26) #define SPI_CTAR_CPHA BIT(25) @@ -92,12 +92,14 @@ #define SPI_TXFR1 0x40 #define SPI_TXFR2 0x44 #define SPI_TXFR3 0x48 +#define SPI_TXFR4 0x4C #define SPI_RXFR0 0x7c #define SPI_RXFR1 0x80 #define SPI_RXFR2 0x84 #define SPI_RXFR3 0x88 +#define SPI_RXFR4 0x8C -#define SPI_CTARE(x) (0x11c + (((x) & GENMASK(1, 0)) * 4)) +#define SPI_CTARE(x) (0x11c + (((x) & GENMASK(2, 0)) * 4)) #define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16) #define SPI_CTARE_DTCP(x) ((x) & 0x7ff) @@ -135,6 +137,7 @@ enum { LX2160A, MCF5441X, VF610, + S32G }; static const struct regmap_range dspi_yes_ranges[] = { @@ -146,15 +149,29 @@ static const struct regmap_range dspi_yes_ranges[] = { regmap_reg_range(SPI_SREX, SPI_SREX), }; +static const struct regmap_range s32g_dspi_yes_ranges[] = { + regmap_reg_range(SPI_MCR, SPI_MCR), + regmap_reg_range(SPI_TCR, SPI_CTAR(5)), + regmap_reg_range(SPI_SR, SPI_TXFR4), + regmap_reg_range(SPI_RXFR0, SPI_RXFR4), + regmap_reg_range(SPI_CTARE(0), SPI_CTARE(5)), + regmap_reg_range(SPI_SREX, SPI_SREX), +}; + static const struct regmap_access_table dspi_access_table = { .yes_ranges = dspi_yes_ranges, .n_yes_ranges = ARRAY_SIZE(dspi_yes_ranges), }; +static const struct regmap_access_table s32g_dspi_access_table = { + .yes_ranges = s32g_dspi_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(s32g_dspi_yes_ranges), +}; + static const struct regmap_range dspi_volatile_ranges[] = { regmap_reg_range(SPI_MCR, SPI_TCR), regmap_reg_range(SPI_SR, SPI_SR), - regmap_reg_range(SPI_PUSHR, SPI_RXFR3), + regmap_reg_range(SPI_PUSHR, SPI_RXFR4), regmap_reg_range(SPI_SREX, SPI_SREX) }; @@ -166,6 +183,7 @@ static const struct regmap_access_table dspi_volatile_table = { enum { DSPI_REGMAP, DSPI_XSPI_REGMAP, + S32G_DSPI_XSPI_REGMAP, DSPI_PUSHR }; @@ -188,6 +206,15 @@ static const struct regmap_config dspi_regmap_config[] = { .wr_table = &dspi_access_table, .rd_table = &dspi_access_table }, + [S32G_DSPI_XSPI_REGMAP] = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0x13c, + .volatile_table = &dspi_volatile_table, + .wr_table = &s32g_dspi_access_table, + .rd_table = &s32g_dspi_access_table, + }, [DSPI_PUSHR] = { .name = "pushr", .reg_bits = 16, @@ -262,6 +289,12 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { .fifo_size = 16, .regmap = &dspi_regmap_config[DSPI_REGMAP] }, + [S32G] = { + .trans_mode = DSPI_XSPI_MODE, + .max_clock_factor = 1, + .fifo_size = 5, + .regmap = &dspi_regmap_config[S32G_DSPI_XSPI_REGMAP] + } }; struct fsl_dspi_dma { From patchwork Fri May 9 11:05:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Clark X-Patchwork-Id: 889038 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BE7428FFE9 for ; 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This also sets ctlr->target automatically so delete that line. Signed-off-by: Marius Trifu Signed-off-by: Larisa Grigore Signed-off-by: James Clark --- drivers/spi/spi-fsl-dspi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index df6f85122bfe..f7f9425a19e1 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -1340,7 +1340,10 @@ static int dspi_probe(struct platform_device *pdev) if (!dspi) return -ENOMEM; - ctlr = spi_alloc_host(&pdev->dev, 0); + if (of_property_read_bool(np, "spi-slave")) + ctlr = spi_alloc_target(&pdev->dev, 0); + else + ctlr = spi_alloc_host(&pdev->dev, 0); if (!ctlr) return -ENOMEM; @@ -1379,9 +1382,6 @@ static int dspi_probe(struct platform_device *pdev) of_property_read_u32(np, "bus-num", &bus_num); ctlr->bus_num = bus_num; - if (of_property_read_bool(np, "spi-slave")) - ctlr->target = true; - dspi->devtype_data = of_device_get_match_data(&pdev->dev); if (!dspi->devtype_data) { dev_err(&pdev->dev, "can't get devtype_data\n"); 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Signed-off-by: Larisa Grigore Signed-off-by: James Clark --- drivers/spi/spi-fsl-dspi.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index f7f9425a19e1..902bf23d276a 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -849,8 +849,8 @@ static void dspi_setup_accel(struct fsl_dspi *dspi) struct spi_transfer *xfer = dspi->cur_transfer; bool odd = !!(dspi->len & 1); - /* No accel for frames not multiple of 8 bits at the moment */ - if (xfer->bits_per_word % 8) + /* No accel for DMA transfers or frames not multiples of 8 bits at the moment */ + if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE || xfer->bits_per_word % 8) goto no_accel; if (!odd && dspi->len <= dspi->devtype_data->fifo_size * 2) { @@ -859,10 +859,7 @@ static void dspi_setup_accel(struct fsl_dspi *dspi) dspi->oper_bits_per_word = 8; } else { /* Start off with maximum supported by hardware */ - if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) - dspi->oper_bits_per_word = 32; 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Fri, 09 May 2025 04:07:04 -0700 (PDT) Received: from ho-tower-lan.lan ([77.81.75.81]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58ecadfsm2914797f8f.22.2025.05.09.04.07.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 May 2025 04:07:03 -0700 (PDT) From: James Clark Date: Fri, 09 May 2025 12:05:54 +0100 Subject: [PATCH 07/14] spi: spi-fsl-dspi: Reset SR flags before sending a new message Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250509-james-nxp-spi-v1-7-32bfcd2fea11@linaro.org> References: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> In-Reply-To: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> To: Vladimir Oltean , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , larisa.grigore@nxp.com, arnd@linaro.org, andrei.stefanescu@nxp.com, dan.carpenter@linaro.org Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Clark X-Mailer: b4 0.14.0 From: Larisa Grigore If, in a previous transfer, the controller sends more data than expected by the DSPI target, SR.RFDF (RX FIFO is not empty) will remain asserted. When flushing the FIFOs at the beginning of a new transfer (writing 1 into MCR.CLR_TXF and MCR.CLR_RXF), SR.RFDF should also be cleared. Otherwise, when running in target mode with DMA, if SR.RFDF remains asserted, the DMA callback will be fired before the controller sends any data. Take this opportunity to reset all Status Register fields. This is required for enabling target mode for S32G in a later commit. Signed-off-by: Larisa Grigore Signed-off-by: James Clark --- drivers/spi/spi-fsl-dspi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 902bf23d276a..b7363cfc649d 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -1063,6 +1063,8 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); + regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); + spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer, dspi->progress, !dspi->irq); From patchwork Fri May 9 11:05:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Clark X-Patchwork-Id: 889123 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F8D3290D8B for ; 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Fri, 09 May 2025 04:07:05 -0700 (PDT) Received: from ho-tower-lan.lan ([77.81.75.81]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58ecadfsm2914797f8f.22.2025.05.09.04.07.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 May 2025 04:07:05 -0700 (PDT) From: James Clark Date: Fri, 09 May 2025 12:05:55 +0100 Subject: [PATCH 08/14] spi: spi-fsl-dspi: Use DMA for S32G controller in target mode Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250509-james-nxp-spi-v1-8-32bfcd2fea11@linaro.org> References: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> In-Reply-To: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> To: Vladimir Oltean , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , larisa.grigore@nxp.com, arnd@linaro.org, andrei.stefanescu@nxp.com, dan.carpenter@linaro.org Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ciprian Marian Costea , James Clark X-Mailer: b4 0.14.0 From: Larisa Grigore Switch to DMA for target mode otherwise the controller is too slow to feed TX FIFO and UNDERFLOW occurs frequently. DMA can work only with 8 and 16 bits per word. 32bits per word is not supported, this is a hardware limitation, so we keep the controller mode in TCFQ mode. Signed-off-by: Larisa Grigore Signed-off-by: Ciprian Marian Costea Signed-off-by: James Clark --- drivers/spi/spi-fsl-dspi.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index b7363cfc649d..50cec3b94322 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -137,7 +137,8 @@ enum { LX2160A, MCF5441X, VF610, - S32G + S32G, + S32G_TARGET }; static const struct regmap_range dspi_yes_ranges[] = { @@ -182,6 +183,7 @@ static const struct regmap_access_table dspi_volatile_table = { enum { DSPI_REGMAP, + S32G_DSPI_REGMAP, DSPI_XSPI_REGMAP, S32G_DSPI_XSPI_REGMAP, DSPI_PUSHR @@ -197,6 +199,15 @@ static const struct regmap_config dspi_regmap_config[] = { .wr_table = &dspi_access_table, .rd_table = &dspi_access_table }, + [S32G_DSPI_REGMAP] = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0x8C, + .volatile_table = &dspi_volatile_table, + .wr_table = &s32g_dspi_access_table, + .rd_table = &s32g_dspi_access_table, + }, [DSPI_XSPI_REGMAP] = { .reg_bits = 32, .val_bits = 32, @@ -294,6 +305,12 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { .max_clock_factor = 1, .fifo_size = 5, .regmap = &dspi_regmap_config[S32G_DSPI_XSPI_REGMAP] + }, + [S32G_TARGET] = { + .trans_mode = DSPI_DMA_MODE, + .max_clock_factor = 1, + .fifo_size = 5, + .regmap = &dspi_regmap_config[S32G_DSPI_REGMAP] } }; @@ -350,6 +367,12 @@ struct fsl_dspi { void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata); }; +static bool is_s32g_dspi(struct fsl_dspi *data) +{ + return data->devtype_data == &devtype_data[S32G] || + data->devtype_data == &devtype_data[S32G_TARGET]; +} + static void dspi_native_host_to_dev(struct fsl_dspi *dspi, u32 *txdata) { switch (dspi->oper_word_size) { @@ -1398,6 +1421,9 @@ static int dspi_probe(struct platform_device *pdev) dspi->pushr_tx = 0; } + if (spi_controller_is_target(ctlr) && is_s32g_dspi(dspi)) + dspi->devtype_data = &devtype_data[S32G_TARGET]; + if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); else From patchwork Fri May 9 11:05:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Clark X-Patchwork-Id: 889036 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07A60291161 for ; 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Fri, 09 May 2025 04:07:07 -0700 (PDT) Received: from ho-tower-lan.lan ([77.81.75.81]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58ecadfsm2914797f8f.22.2025.05.09.04.07.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 May 2025 04:07:06 -0700 (PDT) From: James Clark Date: Fri, 09 May 2025 12:05:56 +0100 Subject: [PATCH 09/14] spi: spi-fsl-dspi: Reinitialize DSPI regs after resuming for S32G Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250509-james-nxp-spi-v1-9-32bfcd2fea11@linaro.org> References: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> In-Reply-To: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> To: Vladimir Oltean , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , larisa.grigore@nxp.com, arnd@linaro.org, andrei.stefanescu@nxp.com, dan.carpenter@linaro.org Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Clark X-Mailer: b4 0.14.0 From: Larisa Grigore After resuming, DSPI registers (MCR and SR) need to be reinitialized for S32G platforms. Signed-off-by: Larisa Grigore Signed-off-by: James Clark --- drivers/spi/spi-fsl-dspi.c | 73 +++++++++++++++++++++++++--------------------- 1 file changed, 40 insertions(+), 33 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 50cec3b94322..0613642d769d 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -1258,6 +1258,39 @@ static const struct of_device_id fsl_dspi_dt_ids[] = { }; MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); +static int dspi_init(struct fsl_dspi *dspi) +{ + unsigned int mcr; + + /* Set idle states for all chip select signals to high */ + mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->max_native_cs - 1, 0)); + + if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) + mcr |= SPI_MCR_XSPI; + if (!spi_controller_is_target(dspi->ctlr)) + mcr |= SPI_MCR_HOST; + + regmap_write(dspi->regmap, SPI_MCR, mcr); + regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); + + switch (dspi->devtype_data->trans_mode) { + case DSPI_XSPI_MODE: + regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE); + break; + case DSPI_DMA_MODE: + regmap_write(dspi->regmap, SPI_RSER, + SPI_RSER_TFFFE | SPI_RSER_TFFFD | + SPI_RSER_RFDFE | SPI_RSER_RFDFD); + break; + default: + dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", + dspi->devtype_data->trans_mode); + return -EINVAL; + } + + return 0; +} + #ifdef CONFIG_PM_SLEEP static int dspi_suspend(struct device *dev) { @@ -1284,6 +1317,13 @@ static int dspi_resume(struct device *dev) if (ret) return ret; spi_controller_resume(dspi->ctlr); + + ret = dspi_init(dspi); + if (ret) { + dev_err(dev, "failed to initialize dspi during resume\n"); + return ret; + } + if (dspi->irq) enable_irq(dspi->irq); @@ -1293,39 +1333,6 @@ static int dspi_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume); -static int dspi_init(struct fsl_dspi *dspi) -{ - unsigned int mcr; - - /* Set idle states for all chip select signals to high */ - mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->max_native_cs - 1, 0)); - - if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) - mcr |= SPI_MCR_XSPI; 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Fri, 09 May 2025 04:07:08 -0700 (PDT) Received: from ho-tower-lan.lan ([77.81.75.81]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58ecadfsm2914797f8f.22.2025.05.09.04.07.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 May 2025 04:07:08 -0700 (PDT) From: James Clark Date: Fri, 09 May 2025 12:05:57 +0100 Subject: [PATCH 10/14] spi: spi-fsl-dspi: Enable modified transfer protocol Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250509-james-nxp-spi-v1-10-32bfcd2fea11@linaro.org> References: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> In-Reply-To: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> To: Vladimir Oltean , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , larisa.grigore@nxp.com, arnd@linaro.org, andrei.stefanescu@nxp.com, dan.carpenter@linaro.org Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andra-Teodora Ilie , Bogdan-Gabriel Roman , James Clark X-Mailer: b4 0.14.0 From: Andra-Teodora Ilie Set MTFE bit in MCR register for frequencies higher than 25MHz. Signed-off-by: Andra-Teodora Ilie Signed-off-by: Bogdan-Gabriel Roman Signed-off-by: Larisa Grigore Signed-off-by: James Clark --- drivers/spi/spi-fsl-dspi.c | 44 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 0613642d769d..31521dac1580 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -24,6 +24,7 @@ #define SPI_MCR 0x00 #define SPI_MCR_HOST BIT(31) +#define SPI_MCR_MTFE BIT(26) #define SPI_MCR_PCSIS(x) ((x) << 16) #define SPI_MCR_CLR_TXF BIT(11) #define SPI_MCR_CLR_RXF BIT(10) @@ -37,6 +38,7 @@ #define SPI_CTAR(x) (0x0c + (((x) & GENMASK(2, 0)) * 4)) #define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27)) +#define SPI_CTAR_DBR BIT(31) #define SPI_CTAR_CPOL BIT(26) #define SPI_CTAR_CPHA BIT(25) #define SPI_CTAR_LSBFE BIT(24) @@ -110,6 +112,8 @@ #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000) +#define SPI_25MHZ 25000000 + struct chip_data { u32 ctar_val; }; @@ -345,6 +349,7 @@ struct fsl_dspi { const void *tx; void *rx; u16 tx_cmd; + bool mtf_enabled; const struct fsl_dspi_devtype_data *devtype_data; struct completion xfer_done; @@ -721,7 +726,7 @@ static void dspi_release_dma(struct fsl_dspi *dspi) } static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, - unsigned long clkrate) + unsigned long clkrate, bool mtf_enabled) { /* Valid baud rate pre-scaler values */ int pbr_tbl[4] = {2, 3, 5, 7}; @@ -738,7 +743,13 @@ static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, for (i = 0; i < ARRAY_SIZE(brs); i++) for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) { - scale = brs[i] * pbr_tbl[j]; + if (mtf_enabled) { + /* In MTF mode DBR=1 so frequency is doubled */ + scale = (brs[i] * pbr_tbl[j]) / 2; + } else { + scale = brs[i] * pbr_tbl[j]; + } + if (scale >= scale_needed) { if (scale < minscale) { minscale = scale; @@ -1120,6 +1131,20 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, return status; } +static int dspi_set_mtf(struct fsl_dspi *dspi) +{ + if (spi_controller_is_target(dspi->ctlr)) + return 0; + + if (dspi->mtf_enabled) + regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_MTFE, + SPI_MCR_MTFE); + else + regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_MTFE, 0); + + return 0; +} + static int dspi_setup(struct spi_device *spi) { struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller); @@ -1178,7 +1203,15 @@ static int dspi_setup(struct spi_device *spi) cs_sck_delay, sck_cs_delay); clkrate = clk_get_rate(dspi->clk); - hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate); + + if (is_s32g_dspi(dspi) && spi->max_speed_hz > SPI_25MHZ) + dspi->mtf_enabled = true; + else + dspi->mtf_enabled = false; + + dspi_set_mtf(dspi); + + hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate, dspi->mtf_enabled); /* Set PCS to SCK delay scale values */ ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate); @@ -1200,6 +1233,9 @@ static int dspi_setup(struct spi_device *spi) SPI_CTAR_PBR(pbr) | SPI_CTAR_BR(br); + if (dspi->mtf_enabled) + chip->ctar_val |= SPI_CTAR_DBR; + if (spi->mode & SPI_LSB_FIRST) chip->ctar_val |= SPI_CTAR_LSBFE; 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Fri, 09 May 2025 04:07:09 -0700 (PDT) Received: from ho-tower-lan.lan ([77.81.75.81]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58ecadfsm2914797f8f.22.2025.05.09.04.07.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 May 2025 04:07:09 -0700 (PDT) From: James Clark Date: Fri, 09 May 2025 12:05:58 +0100 Subject: [PATCH 11/14] spi: spi-fsl-dspi: Halt the module after a new message transfer Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250509-james-nxp-spi-v1-11-32bfcd2fea11@linaro.org> References: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> In-Reply-To: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> To: Vladimir Oltean , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , larisa.grigore@nxp.com, arnd@linaro.org, andrei.stefanescu@nxp.com, dan.carpenter@linaro.org Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bogdan-Gabriel Roman , James Clark X-Mailer: b4 0.14.0 From: Bogdan-Gabriel Roman The XSPI mode implementation in this driver still uses the EOQ flag to signal the last word in a transmission and deassert the PCS signal. However, at speeds lower than ~200kHZ, the PCS signal seems to remain asserted even when SR[EOQF] = 1 indicates the end of a transmission. This is a problem for target devices which require the deassertation of the PCS signal between transfers. Hence, this commit 'forces' the deassertation of the PCS by stopping the module through MCR[HALT] after completing a new transfer. According to the reference manual, the module stops or transitions from the Running state to the Stopped state after the current frame, when any one of the following conditions exist: - The value of SR[EOQF] = 1. - The chip is in Debug mode and the value of MCR[FRZ] = 1. - The value of MCR[HALT] = 1. This shouldn't be done if the last transfer in the message has cs_change set. Signed-off-by: Bogdan-Gabriel Roman Signed-off-by: Larisa Grigore Signed-off-by: James Clark --- drivers/spi/spi-fsl-dspi.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 31521dac1580..db921ee6305f 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -64,6 +64,7 @@ #define SPI_SR_TFIWF BIT(18) #define SPI_SR_RFDF BIT(17) #define SPI_SR_CMDFFF BIT(16) +#define SPI_SR_TXRXS BIT(30) #define SPI_SR_CLEAR (SPI_SR_TCFQF | \ SPI_SR_TFUF | SPI_SR_TFFF | \ SPI_SR_CMDTCF | SPI_SR_SPEF | \ @@ -1056,9 +1057,20 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, struct spi_transfer *transfer; bool cs = false; int status = 0; + u32 val = 0; + bool cs_change = false; message->actual_length = 0; + /* Put DSPI in running mode if halted. */ + regmap_read(dspi->regmap, SPI_MCR, &val); + if (val & SPI_MCR_HALT) { + regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, 0); + while (regmap_read(dspi->regmap, SPI_SR, &val) >= 0 && + !(val & SPI_SR_TXRXS)) + ; + } + list_for_each_entry(transfer, &message->transfers, transfer_list) { dspi->cur_transfer = transfer; dspi->cur_msg = message; @@ -1088,6 +1100,7 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, dspi->tx_cmd |= SPI_PUSHR_CMD_CONT; } + cs_change = transfer->cs_change; dspi->tx = transfer->tx_buf; dspi->rx = transfer->rx_buf; dspi->len = transfer->len; @@ -1125,6 +1138,15 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, dspi_deassert_cs(spi, &cs); } + if (status || !cs_change) { + /* Put DSPI in stop mode */ + regmap_update_bits(dspi->regmap, SPI_MCR, + SPI_MCR_HALT, SPI_MCR_HALT); + while (regmap_read(dspi->regmap, SPI_SR, &val) >= 0 && + val & SPI_SR_TXRXS) + ; + } + message->status = status; spi_finalize_current_message(ctlr); @@ -1306,6 +1328,8 @@ static int dspi_init(struct fsl_dspi *dspi) if (!spi_controller_is_target(dspi->ctlr)) mcr |= SPI_MCR_HOST; + mcr |= SPI_MCR_HALT; + regmap_write(dspi->regmap, SPI_MCR, mcr); regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); 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Fri, 09 May 2025 04:07:11 -0700 (PDT) Received: from ho-tower-lan.lan ([77.81.75.81]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58ecadfsm2914797f8f.22.2025.05.09.04.07.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 May 2025 04:07:11 -0700 (PDT) From: James Clark Date: Fri, 09 May 2025 12:05:59 +0100 Subject: [PATCH 12/14] dt-bindings: spi: dspi: Add S32G support Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250509-james-nxp-spi-v1-12-32bfcd2fea11@linaro.org> References: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> In-Reply-To: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> To: Vladimir Oltean , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , larisa.grigore@nxp.com, arnd@linaro.org, andrei.stefanescu@nxp.com, dan.carpenter@linaro.org Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ciprian Marian Costea , James Clark X-Mailer: b4 0.14.0 From: Ciprian Marian Costea Document S32G compatible strings. 's32g2' and 's32g3' use the same driver so 's32g2' must follow 's32g3'. The SPI controller node in dts can define both host and target pinctrl. The selection between them will be done based on pinctrl-names. The default pinctrl will be loaded first and will be used by the host. If the controller is configured as target (spi-slave property is added in the dts node), the driver will look for the "slave" pinctrl and apply it if found. Signed-off-by: Ciprian Marian Costea Signed-off-by: Larisa Grigore Signed-off-by: James Clark --- Documentation/devicetree/bindings/spi/fsl,dspi.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/fsl,dspi.yaml b/Documentation/devicetree/bindings/spi/fsl,dspi.yaml index 7ca8fceda717..b5fac0bb142a 100644 --- a/Documentation/devicetree/bindings/spi/fsl,dspi.yaml +++ b/Documentation/devicetree/bindings/spi/fsl,dspi.yaml @@ -23,6 +23,7 @@ properties: - fsl,ls2080a-dspi - fsl,ls2085a-dspi - fsl,lx2160a-dspi + - nxp,s32g2-dspi - items: - enum: - fsl,ls1012a-dspi @@ -37,6 +38,9 @@ properties: - items: - const: fsl,lx2160a-dspi - const: fsl,ls2085a-dspi + - items: + - const: nxp,s32g3-dspi + - const: nxp,s32g2-dspi reg: maxItems: 1 @@ -114,3 +118,17 @@ examples: spi-cs-hold-delay-ns = <50>; }; }; + # S32G3 in target mode + - | + spi0: spi@401d4000 { + compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; + reg = <0x401d4000 0x1000>; + interrupts = ; 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Fri, 09 May 2025 04:07:12 -0700 (PDT) Received: from ho-tower-lan.lan ([77.81.75.81]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58ecadfsm2914797f8f.22.2025.05.09.04.07.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 May 2025 04:07:12 -0700 (PDT) From: James Clark Date: Fri, 09 May 2025 12:06:00 +0100 Subject: [PATCH 13/14] spi: spi-fsl-dspi: Enable support for S32G platforms Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250509-james-nxp-spi-v1-13-32bfcd2fea11@linaro.org> References: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> In-Reply-To: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> To: Vladimir Oltean , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , larisa.grigore@nxp.com, arnd@linaro.org, andrei.stefanescu@nxp.com, dan.carpenter@linaro.org Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ciprian Marian Costea , Stoica Cosmin-Stefan , Dan Nica , Larisa Grigore , Stefan-Gabriel Mirea , James Clark X-Mailer: b4 0.14.0 From: Ciprian Marian Costea Add compatible for S32G platforms, allowing DSPI to be used. Add a depends for ARCH_NXP which can replace LAYERSCAPE and also includes the new ARCH_S32 for S32G. Similarly, ARCH_MXC can replace SOC_VF610 || SOC_LS1021A which should avoid updating this for every new sub-platform in the future. Signed-off-by: Ciprian Marian Costea Signed-off-by: Stoica Cosmin-Stefan Signed-off-by: Dan Nica Signed-off-by: Larisa Grigore Signed-off-by: Stefan-Gabriel Mirea Signed-off-by: James Clark --- drivers/spi/Kconfig | 4 ++-- drivers/spi/spi-fsl-dspi.c | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index ed38f6d41f47..ff26be07226b 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -647,10 +647,10 @@ config SPI_FSL_SPI config SPI_FSL_DSPI tristate "Freescale DSPI controller" select REGMAP_MMIO - depends on SOC_VF610 || SOC_LS1021A || ARCH_LAYERSCAPE || M5441x || COMPILE_TEST + depends on ARCH_MXC || ARCH_NXP || M54541x || COMPILE_TEST help This enables support for the Freescale DSPI controller in master - mode. VF610, LS1021A and ColdFire platforms uses the controller. + mode. S32, VF610, LS1021A and ColdFire platforms uses the controller. config SPI_FSL_ESPI tristate "Freescale eSPI controller" diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index db921ee6305f..0982f27a9b2a 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -1311,6 +1311,9 @@ static const struct of_device_id fsl_dspi_dt_ids[] = { }, { .compatible = "fsl,lx2160a-dspi", .data = &devtype_data[LX2160A], + }, { + .compatible = "nxp,s32g2-dspi", + .data = &devtype_data[S32G], }, { /* sentinel */ } }; From patchwork Fri May 9 11:06:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Clark X-Patchwork-Id: 889120 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 419E728FA91 for ; Fri, 9 May 2025 11:07:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 09 May 2025 04:07:14 -0700 (PDT) Received: from ho-tower-lan.lan ([77.81.75.81]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58ecadfsm2914797f8f.22.2025.05.09.04.07.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 May 2025 04:07:13 -0700 (PDT) From: James Clark Date: Fri, 09 May 2025 12:06:01 +0100 Subject: [PATCH 14/14] arm64: dts: Add DSPI entries for S32G platforms Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250509-james-nxp-spi-v1-14-32bfcd2fea11@linaro.org> References: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> In-Reply-To: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> To: Vladimir Oltean , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , larisa.grigore@nxp.com, arnd@linaro.org, andrei.stefanescu@nxp.com, dan.carpenter@linaro.org Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "Radu Pirea (NXP OSS)" , Larisa Grigore , James Clark X-Mailer: b4 0.14.0 From: Larisa Grigore S32G3 and S32G2 have the same 6 SPI devices, add the DT entries. Devices are all the same except spi0 has 8 chip selects instead of 5. Clock settings for the chip rely on ATF Firmware [1]. [1]: https://github.com/nxp-auto-linux/arm-trusted-firmware Co-developed-by: Radu Pirea (NXP OSS) Signed-off-by: Radu Pirea (NXP OSS) Signed-off-by: Larisa Grigore Signed-off-by: James Clark --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 78 ++++++++++++++++++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 78 ++++++++++++++++++++++ arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi | 87 +++++++++++++++++++++++++ arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi | 77 ++++++++++++++++++++++ 4 files changed, 320 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index ea1456d361a3..68848575bf81 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -376,6 +376,45 @@ uart1: serial@401cc000 { status = "disabled"; }; + spi0: spi@401d4000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x401d4000 0x1000>; + interrupts = ; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <8>; + bus-num = <0>; + dmas = <&edma0 0 7>, <&edma0 0 8>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi1: spi@401d8000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x401d8000 0x1000>; + interrupts = ; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <1>; + dmas = <&edma0 0 10>, <&edma0 0 11>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi2: spi@401dc000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x401dc000 0x1000>; + interrupts = ; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <2>; + dmas = <&edma0 0 13>, <&edma0 0 14>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + i2c0: i2c@401e4000 { compatible = "nxp,s32g2-i2c"; reg = <0x401e4000 0x1000>; @@ -460,6 +499,45 @@ uart2: serial@402bc000 { status = "disabled"; }; + spi3: spi@402c8000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x402c8000 0x1000>; + interrupts = ; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <3>; + dmas = <&edma0 1 7>, <&edma0 1 8>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi4: spi@402cc000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x402cc000 0x1000>; + interrupts = ; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <4>; + dmas = <&edma0 1 10>, <&edma0 1 11>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi5: spi@402d0000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x402d0000 0x1000>; + interrupts = ; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <5>; + dmas = <&edma0 1 13>, <&edma0 1 14>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + i2c3: i2c@402d8000 { compatible = "nxp,s32g2-i2c"; reg = <0x402d8000 0x1000>; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 991dbfbfa203..4f883b1a50ad 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -435,6 +435,45 @@ uart1: serial@401cc000 { status = "disabled"; }; + spi0: spi@401d4000 { + compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; + reg = <0x401d4000 0x1000>; + interrupts = ; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <8>; + bus-num = <0>; + dmas = <&edma0 0 7>, <&edma0 0 8>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi1: spi@401d8000 { + compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; + reg = <0x401d8000 0x1000>; + interrupts = ; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <1>; + dmas = <&edma0 0 10>, <&edma0 0 11>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi2: spi@401dc000 { + compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; + reg = <0x401dc000 0x1000>; + interrupts = ; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <2>; + dmas = <&edma0 0 13>, <&edma0 0 14>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + i2c0: i2c@401e4000 { compatible = "nxp,s32g3-i2c", "nxp,s32g2-i2c"; @@ -524,6 +563,45 @@ uart2: serial@402bc000 { status = "disabled"; }; + spi3: spi@402c8000 { + compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; + reg = <0x402c8000 0x1000>; + interrupts = ; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <3>; + dmas = <&edma0 1 7>, <&edma0 1 8>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi4: spi@402cc000 { + compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; + reg = <0x402cc000 0x1000>; + interrupts = ; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <4>; + dmas = <&edma0 1 10>, <&edma0 1 11>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi5: spi@402d0000 { + compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; + reg = <0x402d0000 0x1000>; + interrupts = ; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <5>; + dmas = <&edma0 1 13>, <&edma0 1 14>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + i2c3: i2c@402d8000 { compatible = "nxp,s32g3-i2c", "nxp,s32g2-i2c"; diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi index d26af0fb8be7..812b37b0098b 100644 --- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi @@ -173,6 +173,77 @@ i2c4-gpio-grp1 { pinmux = <0x2d40>, <0x2d30>; }; }; + + dspi1_pins: dspi1_pins { + dspi1_grp0 { + pinmux = <0x72>; + output-enable; + input-enable; + slew-rate = <150>; + bias-pull-up; + }; + + dspi1_grp1 { + pinmux = <0x62>; + output-enable; + slew-rate = <150>; + }; + + dspi1_grp2 { + pinmux = <0x83>; + output-enable; + input-enable; + slew-rate = <150>; + }; + + dspi1_grp3 { + pinmux = <0x5F0>; + input-enable; + slew-rate = <150>; + bias-pull-up; + }; + + dspi1_grp4 { + pinmux = <0x3D92>, + <0x3DA2>, + <0x3DB2>; + }; + }; + + dspi5_pins: dspi5_pins { + dspi5_grp0 { + pinmux = <0x93>; + output-enable; + input-enable; + slew-rate = <150>; + }; + + dspi5_grp1 { + pinmux = <0xA0>; + input-enable; + slew-rate = <150>; + bias-pull-up; + }; + + dspi5_grp2 { + pinmux = <0x3ED2>, + <0x3EE2>, + <0x3EF2>; + }; + + dspi5_grp3 { + pinmux = <0xB3>; + output-enable; + slew-rate = <150>; + }; + dspi5_grp4 { + pinmux = <0xC3>; + output-enable; + input-enable; + slew-rate = <150>; + bias-pull-up; + }; + }; }; &can0 { @@ -220,3 +291,19 @@ &i2c4 { pinctrl-1 = <&i2c4_gpio_pins>; status = "okay"; }; + +&spi1 { + pinctrl-0 = <&dspi1_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + spidev0: spidev@0 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <4000000>; + reg = <0>; + fsl,spi-cs-sck-delay = <100>; + fsl,spi-sck-cs-delay = <100>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi index ba53ec622f0b..798b58fa9536 100644 --- a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi @@ -127,6 +127,77 @@ i2c4-gpio-grp1 { pinmux = <0x2d40>, <0x2d30>; }; }; + + dspi1_pins: dspi1_pins { + dspi1_grp0 { + pinmux = <0x62>; + output-enable; + slew-rate = <150>; + }; + + dspi1_grp1 { + pinmux = <0x72>; + output-enable; + input-enable; + slew-rate = <150>; + bias-pull-up; + }; + + dspi1_grp2 { + pinmux = <0x83>; + output-enable; + input-enable; + slew-rate = <150>; + }; + + dspi1_grp3 { + pinmux = <0x5F0>; + input-enable; + slew-rate = <150>; + bias-pull-up; + }; + + dspi1_grp4 { + pinmux = <0x3D92>, + <0x3DA2>, + <0x3DB2>; + }; + }; + + dspi5_pins: dspi5_pins { + dspi5_grp0 { + pinmux = <0x93>; + output-enable; + input-enable; + slew-rate = <150>; + }; + + dspi5_grp1 { + pinmux = <0xA0>; + input-enable; + slew-rate = <150>; + bias-pull-up; + }; + + dspi5_grp2 { + pinmux = <0x3ED2>, + <0x3EE2>, + <0x3EF2>; + }; + + dspi5_grp3 { + pinmux = <0xB3>; + output-enable; + slew-rate = <150>; + }; + dspi5_grp4 { + pinmux = <0xC3>; + output-enable; + input-enable; + slew-rate = <150>; + bias-pull-up; + }; + }; }; &can0 { @@ -155,6 +226,12 @@ pcal6524: gpio-expander@22 { }; }; +&spi1 { + pinctrl-0 = <&dspi1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &i2c2 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&i2c2_pins>;