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Thu, 08 May 2025 08:15:33 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 5488FWRb006369; Thu, 8 May 2025 08:15:32 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 5488FWbQ006367 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 May 2025 08:15:32 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 4635958) id 4234340D09; Thu, 8 May 2025 16:15:31 +0800 (CST) From: Wenbin Yao To: catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, kishon@kernel.org, sfr@canb.auug.org.au, linux-phy@lists.infradead.org Cc: krishna.chundru@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_cang@quicinc.com, quic_qianyu@quicinc.com, quic_wenbyao@quicinc.com Subject: [PATCH v3 1/5] arm64: Kconfig: enable PCI Power Control Slot driver for QCOM Date: Thu, 8 May 2025 16:15:10 +0800 Message-Id: <20250508081514.3227956-2-quic_wenbyao@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250508081514.3227956-1-quic_wenbyao@quicinc.com> References: <20250508081514.3227956-1-quic_wenbyao@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 481nWpG-Z0Tf3w32Kn2NujcWXhWrDIJB X-Authority-Analysis: v=2.4 cv=E5XNpbdl c=1 sm=1 tr=0 ts=681c6827 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=8J9pHfFvgnT8GwhQ4KkA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA4MDA3MiBTYWx0ZWRfXyXndZstS/ke/ pFeu7nnsC1ZpIGX+PFI21xntAs99z1S3b8TxeRjv+U0p8XibS/4weIKThXs5JJ6wA3Z7PlyOPcG LHbXHhcMA1JQke/9ha52f7SKcHPlpXvQRiFMfVJPD4nIv11ybAZdPcROBDu7h9VRT6o+wahAbLB bQwNCENcWcgLsy158HqIYBIXFs72y8gugp6DcxP9X8CPKC/vLKnEmVQBTQ1hUuWg/L7DIwC/bRb SZQxrp/fDSHc/VpmK9GpL0FmfXeqNvjmnvFbSHyHfzoteNbzMcvTVlnV/JMx69ivAup8Cm0AkD3 RuOYDWmk8PlZfuQ07SomAJfHN9VQksfYfF7Joix8TQl4uVbDoYxivsfPkfzqTBjUapBGwfEC88s aREqr7d2XSxbrKLT5b7NUG/DbySC5ezfMeZrWvWvAZVIuDSock4PGj3OJ63DLd2wBWLSYieR X-Proofpoint-ORIG-GUID: 481nWpG-Z0Tf3w32Kn2NujcWXhWrDIJB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-08_02,2025-05-07_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 adultscore=0 mlxscore=0 malwarescore=0 bulkscore=0 phishscore=0 spamscore=0 priorityscore=1501 mlxlogscore=797 lowpriorityscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505080072 From: Qiang Yu Enable the pwrctrl driver, which is utilized to manage the power supplies of the devices connected to the PCI slots. This ensures that the voltage rails of the standard PCI slots on some platforms eg. X1E80100-QCP can be correctly turned on/off if they are described under PCIe port device tree node. Signed-off-by: Qiang Yu Signed-off-by: Wenbin Yao --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index a541bb029..0ffd65e36 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -270,6 +270,7 @@ config ARCH_QCOM select GPIOLIB select PINCTRL select HAVE_PWRCTRL if PCI + select PCI_PWRCTRL_SLOT if PCI help This enables support for the ARMv8 based Qualcomm chipsets. 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Thu, 08 May 2025 08:15:34 +0000 Received: from APTAIPPMTA01.qualcomm.com (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 5488FYdd015232; Thu, 8 May 2025 08:15:34 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 5488FXL6015229 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 May 2025 08:15:34 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 4635958) id DE7C140CFD; Thu, 8 May 2025 16:15:32 +0800 (CST) From: Wenbin Yao To: catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, kishon@kernel.org, sfr@canb.auug.org.au, linux-phy@lists.infradead.org Cc: krishna.chundru@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_cang@quicinc.com, quic_qianyu@quicinc.com, quic_wenbyao@quicinc.com, Konrad Dybcio Subject: [PATCH v3 2/5] arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3 Date: Thu, 8 May 2025 16:15:11 +0800 Message-Id: <20250508081514.3227956-3-quic_wenbyao@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250508081514.3227956-1-quic_wenbyao@quicinc.com> References: <20250508081514.3227956-1-quic_wenbyao@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=Ao/u3P9P c=1 sm=1 tr=0 ts=681c6829 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=iAUx9HIH3_1I80GXj-QA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA4MDA3MiBTYWx0ZWRfX/bW8IVtUAo3U iKGeRGiOwMZsunBcPfcFYcAz1/R0vSOY7KxfQ0MZ2QToQ7Tnu58BE0rbFg5Mcr2xvhD05P+vSGw MAlqkuLTZt4mkUs5puJPvRGUVS2FFFvpaWNi1gNpMqVTteYWbOMVSxxE/IxeIUcKlKA8xwZ223s t3ekRM+EOqPhDIbIP+Fo7H1OqUAu+l3WlOySskifs1ctRlY7+cRTam9RmUdWIbRHMeALlGLmfTR 9mxYSx8NhNdCidiKvXSFZEO5txS3qUnMIMmIIVWtWeN2P3DSZXK+g2TJHipRQ5gyoGQJ63QeGhT wBz5r3TXBQ/8MzwoG+jpna+thB9WfsfUqZwplNEHq3fycKU++dCMUfvrUJTuWsoJUh+LDKgtgg8 Jc0XWoYkgcvHW+x6hnWkq3VM4cAQCoeIsZy+pBix/jb7Rp4eujG/zdOIL96nFWLL1bNVHqfU X-Proofpoint-GUID: nizCpZqSH64bxL--A-Yf62QnIQvjwDu4 X-Proofpoint-ORIG-GUID: nizCpZqSH64bxL--A-Yf62QnIQvjwDu4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-08_02,2025-05-07_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 mlxlogscore=939 bulkscore=0 priorityscore=1501 spamscore=0 impostorscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505080072 From: Qiang Yu Add pcie3port node to represent the PCIe bridge of PCIe3 so that PCI slot voltage rails can be described under this node in the board's dts. Signed-off-by: Qiang Yu Signed-off-by: Wenbin Yao Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 46b79fce9..430f9d567 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3287,6 +3287,17 @@ opp-128000000 { opp-peak-kBps = <15753000 1>; }; }; + + pcie3port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3_phy: phy@1be0000 { From patchwork Thu May 8 08:15:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenbin Yao X-Patchwork-Id: 888869 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CA3A221D85; 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Describe the voltage rails of the x8 PCI slots for PCIe3 port. Signed-off-by: Qiang Yu Signed-off-by: Wenbin Yao Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 118 ++++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 470c4f826..ec2479f8f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -318,6 +318,48 @@ vreg_wcn_3p3: regulator-wcn-3p3 { regulator-boot-on; }; + vreg_pcie_12v: regulator-pcie-12v { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + + gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pcie_x8_12v>; + pinctrl-names = "default"; + }; + + vreg_pcie_3v3_aux: regulator-pcie-3v3-aux { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_3P3_AUX"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pm_sde7_aux_3p3_en>; + pinctrl-names = "default"; + }; + + vreg_pcie_3v3: regulator-pcie-3v3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pm_sde7_main_3p3_en>; + pinctrl-names = "default"; +}; + usb-1-ss0-sbu-mux { compatible = "onnn,fsusb42", "gpio-sbu-mux"; @@ -909,6 +951,59 @@ &mdss_dp3_phy { status = "okay"; }; +&pm8550ve_8_gpios { + pcie_x8_12v: pcie-12v-default-state { + pins = "gpio8"; + function = "normal"; + output-enable; + output-high; + bias-pull-down; + power-source = <0>; + }; +}; + +&pmc8380_3_gpios { + pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state { + pins = "gpio8"; + function = "normal"; + output-enable; + output-high; + bias-pull-down; + power-source = <0>; + }; + + pm_sde7_main_3p3_en: pcie-main-3p3-default-state { + pins = "gpio6"; + function = "normal"; + output-enable; + output-high; + bias-pull-down; + power-source = <0>; + }; +}; + +&pcie3 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_default>; + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&pcie3_phy { + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie3port { + vpcie12v-supply = <&vreg_pcie_12v>; + vpcie3v3-supply = <&vreg_pcie_3v3>; + vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>; +}; + &pcie4 { perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; @@ -1120,6 +1215,29 @@ nvme_reg_en: nvme-reg-en-state { bias-disable; }; + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio144"; + function = "pcie3_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins = "gpio147"; From patchwork Thu May 8 08:15:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenbin Yao X-Patchwork-Id: 888870 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F2CF22154B; Thu, 8 May 2025 08:15:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746692156; cv=none; b=PqJI4OMTrtSEVD80yB2MUemBKPW4dUPhZshxWEW9L4hPq7wMlUcKnJMeBTgqy0oUFqZBsQCjdUfVX9bKLZlo3cZZYgjRmbniphVnpP9g9FpsKrNkj3pdmd14/bPwPEgtG167IhJV12p+z8jl/9P6rRYLwrt7t2rZtGZRD9mPPIQ= ARC-Message-Signature: i=1; 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Thu, 8 May 2025 08:15:37 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 46dc7mq5ft-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 May 2025 08:15:37 +0000 Received: from APTAIPPMTA01.qualcomm.com (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 5488FbOH015282; Thu, 8 May 2025 08:15:37 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 5488FbsS015267 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 May 2025 08:15:37 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 4635958) id 108D240CFD; Thu, 8 May 2025 16:15:36 +0800 (CST) From: Wenbin Yao To: catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, kishon@kernel.org, sfr@canb.auug.org.au, linux-phy@lists.infradead.org Cc: krishna.chundru@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_cang@quicinc.com, quic_qianyu@quicinc.com, quic_wenbyao@quicinc.com Subject: [PATCH v3 4/5] arm64: dts: qcom: x1e80100-qcp: Add qref supply for PCIe PHYs Date: Thu, 8 May 2025 16:15:13 +0800 Message-Id: <20250508081514.3227956-5-quic_wenbyao@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250508081514.3227956-1-quic_wenbyao@quicinc.com> References: <20250508081514.3227956-1-quic_wenbyao@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA4MDA3MiBTYWx0ZWRfX8/PD56QYFILF l1hmA/c9w/23dLojVeSdOLbmZ2a0w90rGiesv3wDg10NJDoguuqDDtqWznWwu9dJ9w8fIIdb6Ol WDji7LSmo0ndtKvVzLnPSzebadvFYG4k/xpeHSoyvZ1bbcfXi0Lj5BMAaw+r4UiWQpOurJU3uAr KKC7elYppIAx5LfPCqU4nZpE7uSbKxRwbm9OZkAJdtyjfSIntQ1I8Qv5/OgluBMfr6J25RhJ8U4 rmQG6paZk9CV4/vvjClcvyJX1QJz3jg0+EsK1p7ZcH4yIOYKi0dt57VBzI7BWAZRP++sfqjtVqJ loAj7r2zCp+pYe2ECyfx9eAfzbIuwgahkyKmCiO0+7Rd/Rq8PFetj5fvtyRp9mNv/Mfgyk9bR+v +H+1SQ2e5TaqYmfBFSHJUoC4/k1WzyyPeoEnXrP0dt5sgLWThrUFZtZKqAJ7oQLv7wdmhXN2 X-Proofpoint-GUID: -8fcnbdSkNyIeY4rp2aDy6GtK-sEpCZ9 X-Proofpoint-ORIG-GUID: -8fcnbdSkNyIeY4rp2aDy6GtK-sEpCZ9 X-Authority-Analysis: v=2.4 cv=BvGdwZX5 c=1 sm=1 tr=0 ts=681c682c cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=OjqB7RjhM8taGROUhtwA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-08_02,2025-05-07_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 phishscore=0 impostorscore=0 mlxscore=0 spamscore=0 mlxlogscore=916 malwarescore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505080072 From: Qiang Yu All PCIe PHYs on X1E80100 require vdda-qref power supplies, but this is missing in the current PHY device tree node. The PCIe port can still function because the regulator L3J, which vdda-qref consumes, is voted by other components. Since the device tree should accurately describe the hardware, add the vdda-qref power supply explicitly in all PCIe PHY device nodes. Signed-off-by: Qiang Yu Signed-off-by: Wenbin Yao --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index ec2479f8f..a7f3ac142 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -994,6 +994,7 @@ &pcie3 { &pcie3_phy { vdda-phy-supply = <&vreg_l3c_0p8>; vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l3j_0p8>; status = "okay"; }; @@ -1017,6 +1018,7 @@ &pcie4 { &pcie4_phy { vdda-phy-supply = <&vreg_l3i_0p8>; vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l3j_0p8>; status = "okay"; }; @@ -1053,6 +1055,7 @@ &pcie6a { &pcie6a_phy { vdda-phy-supply = <&vreg_l1d_0p8>; vdda-pll-supply = <&vreg_l2j_1p2>; + vdda-qref-supply = <&vreg_l3j_0p8>; status = "okay"; }; From patchwork Thu May 8 08:15:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenbin Yao X-Patchwork-Id: 888629 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C76D221D596; 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Thu, 08 May 2025 08:15:43 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 5488Felj015326; Thu, 8 May 2025 08:15:40 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 46dc7mq5g5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 May 2025 08:15:40 +0000 Received: from APTAIPPMTA01.qualcomm.com (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 5488FYdg015232; Thu, 8 May 2025 08:15:40 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 5488FeR9015306 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 May 2025 08:15:40 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 4635958) id 568F240CFD; Thu, 8 May 2025 16:15:39 +0800 (CST) From: Wenbin Yao To: catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, kishon@kernel.org, sfr@canb.auug.org.au, linux-phy@lists.infradead.org Cc: krishna.chundru@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_cang@quicinc.com, quic_qianyu@quicinc.com, quic_wenbyao@quicinc.com, Johan Hovold , Abel Vesa Subject: [PATCH v3 5/5] phy: qcom: qmp-pcie: add x1e80100 qref supplies Date: Thu, 8 May 2025 16:15:14 +0800 Message-Id: <20250508081514.3227956-6-quic_wenbyao@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250508081514.3227956-1-quic_wenbyao@quicinc.com> References: <20250508081514.3227956-1-quic_wenbyao@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA4MDA3MiBTYWx0ZWRfX8Gt7V3Ewdg1u gjs7bgcDRKs1e805Lo1grnuUnyKh+7r5Z8uBWukbn2inB9npIpiPwE1mC8YRcotGUSyIt5RPT9L C8RHVexQn5PF4B91M6TlFdQDJzkOc9B+gRtUoaUeBnSovw2dchy/HvoKCc2KZUnb0BCQn7m7E5r mte99CYLSiLAWjgQwkDuIobL4SJsI+h9jtmn9FLVJPVwTcQgNBua5exCaryZCANXVrdQey1gcGM X6CszKI22c25JcVytM97cjG4CKV8zGCpFiA/T2KwA6VBD2ODI6/4cjNIX8EMQQbE2NcjKf7mBZG YMUNte2kWaxQwJI+x/qQF+/1EEi4PT2KsN9OQ5L9ks6nP3ZGYVbJH/ZN9hCvMGnt+6r80jRcDP+ t0gw5cx7I5JDZbJSgfaFWoJSSWzbgjnTAq9lLOAWRqft+wpfwjTlbx/acaUtYctImGwzSUm0 X-Proofpoint-GUID: mFh4YkiYOyOUUFmZkBKTAPY-kXeLMAoa X-Proofpoint-ORIG-GUID: mFh4YkiYOyOUUFmZkBKTAPY-kXeLMAoa X-Authority-Analysis: v=2.4 cv=J5Kq7BnS c=1 sm=1 tr=0 ts=681c682f cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=ZID-MTkIcqpTFlPhiEUA:9 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-08_02,2025-05-07_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 malwarescore=0 impostorscore=0 spamscore=0 clxscore=1011 mlxlogscore=999 mlxscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505080072 From: Qiang Yu All PCIe PHYs on the X1E80100 SOC require the vdda-qref, which feeds QREF clocks provided by the TCSR device. Hence, restore the vdda-qref request for the 6th PCIe instance by reverting commit 031b46b4729b ("phy: qcom: qmp-pcie: drop bogus x1e80100 qref supplies"). For the 4th PCIe instance (Gen3 x2), add a new driver data entry, namely x1e80100_qmp_gen3x2_pciephy_cfg, which is a copy of sm8550_qmp_gen3x2_pciephy_cfg but uses sm8550_qmp_phy_vreg_l instead. Fixes: 031b46b4729b ("phy: qcom: qmp-pcie: drop bogus x1e80100 qref supplies") Fixes: 606060ce8fd0 ("phy: qcom-qmp-pcie: Add support for X1E80100 g3x2 and g4x2 PCIE") Cc: Johan Hovold Cc: Abel Vesa Signed-off-by: Qiang Yu Signed-off-by: Wenbin Yao --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 37 ++++++++++++++++++++---- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index ab90aafb3..c3c725744 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -4142,6 +4142,33 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = { .phy_status = PHYSTATUS_4_20, }; +static const struct qmp_phy_cfg x1e80100_qmp_gen3x2_pciephy_cfg = { + .lanes = 2, + + .offsets = &qmp_pcie_offsets_v5, + + .tbls = { + .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl), + .tx = sm8550_qmp_gen3x2_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), + .rx = sm8550_qmp_gen3x2_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), + .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), + }, + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), + .regs = pciephy_v5_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, +}; + static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { .lanes = 2, @@ -4164,8 +4191,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs = pciephy_v6_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, @@ -4197,8 +4224,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs = pciephy_v6_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, @@ -5094,7 +5121,7 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { .data = &sm8650_qmp_gen4x2_pciephy_cfg, }, { .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy", - .data = &sm8550_qmp_gen3x2_pciephy_cfg, + .data = &x1e80100_qmp_gen3x2_pciephy_cfg, }, { .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy", .data = &x1e80100_qmp_gen4x2_pciephy_cfg,