From patchwork Thu May 8 18:12:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 888620 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03921229B16; Thu, 8 May 2025 18:13:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728013; cv=none; b=FwkJbMbaDSEnmAkfJrmgbiTE2PN7PHODNSN1Qaf885KF9uDYRsSnqNTbhtFPzpx9qyBtamH9MV7fZ8irqX1Cup8TdaGWb2XALPa7qH7ie5AxwmWXGV/y6E5dFNnJbAcnfB3qc9WpNShHQ8XfY5u3ZiPwrXDkmnX/FytrY2PJ590= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728013; c=relaxed/simple; bh=bDHdn95VekxzDJanXgTA48lEwL5W43wixFKSpHwJLcs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VWWli0jYP7NIR0ruL5+yX/NbIn1Ah3cp8wUo9i9ux6fwKAlhqw1HDJldRHWJB6fjfJuTxuZE1ccny1KqNYN7HIGeBzPZOGI7jazDhbR1+XYyV3HPSAnLOAxrfEA5Fsoy0+ayeAq/q+tLkdHMFP7lWqbgm2HYIo255CvD81cgE1I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CTwETgFn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CTwETgFn" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C0D96C4CEE7; Thu, 8 May 2025 18:13:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746728011; bh=bDHdn95VekxzDJanXgTA48lEwL5W43wixFKSpHwJLcs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=CTwETgFnrOB7vyySHhuj/pCsic+K+giVtdx1wxWum9fnvATvxMuKJpZc/PoIWsv+c n0lp0gQPMj11qz9ZY2jXaZ0PhhKPcxw9CTuUYA2sBudl15DaF/IYNchH+3Rphw3XiK 1VHylEBvUjwUmhbJTDvEab6lTd8g8JaU2KiUfrd7VGRHuKjdFie2rTgxjivfYpXNVo 8m9ovfyusoz80w6WaAwfxUNXb4b2eJjXMVD/TBf6wWlWcCxaMin2rBpW8OQ/H2IpIU uxQkLuMINgT1rCeL0ElAXAfyhAeneDO5/UGMTzLrA+qzrqfUrp4lJCRVE2lv2S2Xtz xgyXoLeU3gcVg== From: Konrad Dybcio Date: Thu, 08 May 2025 20:12:33 +0200 Subject: [PATCH RFT 01/14] soc: qcom: Add UBWC config provider Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250508-topic-ubwc_central-v1-1-035c4c5cbe50@oss.qualcomm.com> References: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> In-Reply-To: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746728002; l=10882; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=V9ixTYvvS78w1Iy5uh3EIkmQbXcpwcNzwrwRRDc3Tlk=; b=6BK4dBDtEYF8kw7dI4WaRvmGXiZkIibrZ5kUJoR19VgvDF/MaXXGMoiyrsscA35k9xY/rhWSf zrECU9TqgBTAQXNhvnvJzPBjNChbDHeEdn2bJV5RH6mawri6JM5STrl X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Add a file that will serve as a single source of truth for UBWC configuration data for various multimedia blocks. Signed-off-by: Konrad Dybcio --- drivers/soc/qcom/Kconfig | 8 ++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/ubwc_config.c | 255 +++++++++++++++++++++++++++++++++++++++++ include/linux/soc/qcom/ubwc.h | 31 +++++ 4 files changed, 295 insertions(+) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 58e63cf0036ba8554e4082da5184a620ca807a9e..2caadbbcf8307ff94f5afbdd1481e5e5e291749f 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -296,3 +296,11 @@ config QCOM_PBS PBS trigger event to the PBS RAM. endmenu + +config QCOM_UBWC_CONFIG + tristate + help + Most Qualcomm SoCs feature a number of Universal Bandwidth Compression + (UBWC) engines across various IP blocks, which need to be initialized + with coherent configuration data. This module functions as a single + source of truth for that information. diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index acbca2ab5cc2a9ab3dce1ff38efd048ba2fab31e..b7f1d2a5736748b8772c090fd24462fa91f321c6 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -39,3 +39,4 @@ obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o qcom_ice-objs += ice.o obj-$(CONFIG_QCOM_INLINE_CRYPTO_ENGINE) += qcom_ice.o obj-$(CONFIG_QCOM_PBS) += qcom-pbs.o +obj-$(CONFIG_QCOM_UBWC_CONFIG) += ubwc_config.o diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c new file mode 100644 index 0000000000000000000000000000000000000000..3f81fb2aab284dc9a5bcf53e5d638aaba44b6f2d --- /dev/null +++ b/drivers/soc/qcom/ubwc_config.c @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +static const struct qcom_ubwc_cfg_data msm8937_data = { + .ubwc_enc_version = UBWC_1_0, + .ubwc_dec_version = UBWC_1_0, + .highest_bank_bit = 1, + .mdss_reg_bus_bw = 76800, +}; + +static const struct qcom_ubwc_cfg_data msm8998_data = { + .ubwc_enc_version = UBWC_1_0, + .ubwc_dec_version = UBWC_1_0, + .highest_bank_bit = 2, + .mdss_reg_bus_bw = 76800, +}; + +static const struct qcom_ubwc_cfg_data qcm2290_data = { + /* no UBWC */ + .highest_bank_bit = 2, + .mdss_reg_bus_bw = 76800, +}; + +static const struct qcom_ubwc_cfg_data sa8775p_data = { + .ubwc_enc_version = UBWC_4_0, + .ubwc_dec_version = UBWC_4_0, + .ubwc_swizzle = 4, + .ubwc_bank_spread = true, + .highest_bank_bit = 0, + .macrotile_mode = true, + .mdss_reg_bus_bw = 74000, +}; + +static const struct qcom_ubwc_cfg_data sar2130p_data = { + .ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */ + .ubwc_dec_version = UBWC_4_3, + .ubwc_swizzle = 6, + .ubwc_bank_spread = true, + .highest_bank_bit = 0, + .macrotile_mode = true, + .mdss_reg_bus_bw = 74000, +}; + +static const struct qcom_ubwc_cfg_data sc7180_data = { + .ubwc_enc_version = UBWC_2_0, + .ubwc_dec_version = UBWC_2_0, + .ubwc_swizzle = 6, + .ubwc_bank_spread = true, + .highest_bank_bit = 1, + .mdss_reg_bus_bw = 76800, +}; + +static const struct qcom_ubwc_cfg_data sc7280_data = { + .ubwc_enc_version = UBWC_3_0, + .ubwc_dec_version = UBWC_4_0, + .ubwc_swizzle = 6, + .ubwc_bank_spread = true, + .highest_bank_bit = 1, + .macrotile_mode = true, + .mdss_reg_bus_bw = 74000, +}; + +static const struct qcom_ubwc_cfg_data sc8180x_data = { + .ubwc_enc_version = UBWC_3_0, + .ubwc_dec_version = UBWC_3_0, + .highest_bank_bit = 3, + .macrotile_mode = true, + .mdss_reg_bus_bw = 76800, +}; + +static const struct qcom_ubwc_cfg_data sc8280xp_data = { + .ubwc_enc_version = UBWC_4_0, + .ubwc_dec_version = UBWC_4_0, + .ubwc_swizzle = 6, + .ubwc_bank_spread = true, + .highest_bank_bit = 3, + .macrotile_mode = true, + .mdss_reg_bus_bw = 76800, +}; + +static const struct qcom_ubwc_cfg_data sdm670_data = { + .ubwc_enc_version = UBWC_2_0, + .ubwc_dec_version = UBWC_2_0, + .highest_bank_bit = 1, + .mdss_reg_bus_bw = 76800, +}; + +static const struct qcom_ubwc_cfg_data sdm845_data = { + .ubwc_enc_version = UBWC_2_0, + .ubwc_dec_version = UBWC_2_0, + .highest_bank_bit = 2, + .mdss_reg_bus_bw = 76800, +}; + +static const struct qcom_ubwc_cfg_data sm6115_data = { + .ubwc_enc_version = UBWC_1_0, + .ubwc_dec_version = UBWC_2_0, + .ubwc_swizzle = 7, + .ubwc_bank_spread = true, + .highest_bank_bit = 1, + .mdss_reg_bus_bw = 76800, +}; + +static const struct qcom_ubwc_cfg_data sm6125_data = { + .ubwc_enc_version = UBWC_1_0, + .ubwc_dec_version = UBWC_3_0, + .ubwc_swizzle = 1, + .highest_bank_bit = 1, +}; + +static const struct qcom_ubwc_cfg_data sm6150_data = { + .ubwc_enc_version = UBWC_2_0, + .ubwc_dec_version = UBWC_2_0, + .highest_bank_bit = 1, + .mdss_reg_bus_bw = 76800, +}; + +static const struct qcom_ubwc_cfg_data sm6350_data = { + .ubwc_enc_version = UBWC_2_0, + .ubwc_dec_version = UBWC_2_0, + .ubwc_swizzle = 6, + .ubwc_bank_spread = true, + .highest_bank_bit = 1, + .mdss_reg_bus_bw = 76800, +}; + +static const struct qcom_ubwc_cfg_data sm7150_data = { + .ubwc_enc_version = UBWC_2_0, + .ubwc_dec_version = UBWC_2_0, + .highest_bank_bit = 1, + .mdss_reg_bus_bw = 76800, +}; + +static const struct qcom_ubwc_cfg_data sm8150_data = { + .ubwc_enc_version = UBWC_3_0, + .ubwc_dec_version = UBWC_3_0, + .highest_bank_bit = 2, + .mdss_reg_bus_bw = 76800, +}; + +static const struct qcom_ubwc_cfg_data sm8250_data = { + .ubwc_enc_version = UBWC_4_0, + .ubwc_dec_version = UBWC_4_0, + .ubwc_swizzle = 6, + .ubwc_bank_spread = true, + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ + .highest_bank_bit = 3, + .macrotile_mode = true, + .mdss_reg_bus_bw = 76800, +}; + +static const struct qcom_ubwc_cfg_data sm8350_data = { + .ubwc_enc_version = UBWC_4_0, + .ubwc_dec_version = UBWC_4_0, + .ubwc_swizzle = 6, + .ubwc_bank_spread = true, + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ + .highest_bank_bit = 3, + .macrotile_mode = true, + .mdss_reg_bus_bw = 74000, +}; + +static const struct qcom_ubwc_cfg_data sm8550_data = { + .ubwc_enc_version = UBWC_4_0, + .ubwc_dec_version = UBWC_4_3, + .ubwc_swizzle = 6, + .ubwc_bank_spread = true, + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ + .highest_bank_bit = 3, + .macrotile_mode = true, + .mdss_reg_bus_bw = 57000, +}; + +static const struct qcom_ubwc_cfg_data x1e80100_data = { + .ubwc_enc_version = UBWC_4_0, + .ubwc_dec_version = UBWC_4_3, + .ubwc_swizzle = 6, + .ubwc_bank_spread = true, + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ + .highest_bank_bit = 3, + .macrotile_mode = true, + /* TODO: Add mdss_reg_bus_bw with real value */ +}; + +static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = { + { .compatible = "qcom,apq8096", .data = &msm8998_data }, + { .compatible = "qcom,msm8917", .data = &msm8937_data }, + { .compatible = "qcom,msm8937", .data = &msm8937_data }, + { .compatible = "qcom,msm8953", .data = &msm8937_data }, + { .compatible = "qcom,msm8956", .data = &msm8937_data }, + { .compatible = "qcom,msm8976", .data = &msm8937_data }, + { .compatible = "qcom,msm8996", .data = &msm8998_data }, + { .compatible = "qcom,msm8998", .data = &msm8998_data }, + { .compatible = "qcom,qcm2290", .data = &qcm2290_data, }, + { .compatible = "qcom,qcm6490", .data = &sc7280_data, }, + { .compatible = "qcom,sa8155p", .data = &sm8150_data, }, + { .compatible = "qcom,sa8540p", .data = &sc8280xp_data, }, + { .compatible = "qcom,sa8775p", .data = &sa8775p_data, }, + { .compatible = "qcom,sc7180", .data = &sc7180_data }, + { .compatible = "qcom,sc7280", .data = &sc7280_data, }, + { .compatible = "qcom,sc8180x", .data = &sc8180x_data, }, + { .compatible = "qcom,sc8280xp", .data = &sc8280xp_data, }, + { .compatible = "qcom,sdm630", .data = &msm8937_data }, + { .compatible = "qcom,sdm636", .data = &msm8937_data }, + { .compatible = "qcom,sdm660", .data = &msm8937_data }, + { .compatible = "qcom,sdm670", .data = &sdm670_data, }, + { .compatible = "qcom,sdm845", .data = &sdm845_data, }, + { .compatible = "qcom,sm4250", .data = &sm6115_data, }, + { .compatible = "qcom,sm6115", .data = &sm6115_data, }, + { .compatible = "qcom,sm6125", .data = &sm6125_data, }, + { .compatible = "qcom,sm6150", .data = &sm6150_data, }, + { .compatible = "qcom,sm6350", .data = &sm6350_data, }, + { .compatible = "qcom,sm6375", .data = &sm6350_data, }, + { .compatible = "qcom,sm7125", .data = &sc7180_data }, + { .compatible = "qcom,sm7150", .data = &sm7150_data, }, + { .compatible = "qcom,sm8150", .data = &sm8150_data, }, + { .compatible = "qcom,sm8250", .data = &sm8250_data, }, + { .compatible = "qcom,sm8350", .data = &sm8350_data, }, + { .compatible = "qcom,sm8450", .data = &sm8350_data, }, + { .compatible = "qcom,sm8550", .data = &sm8550_data, }, + { .compatible = "qcom,sm8650", .data = &sm8550_data, }, + { .compatible = "qcom,x1e80100", .data = &x1e80100_data, }, + { .compatible = "qcom,x1p42100", .data = &x1e80100_data, }, + { } +}; + +const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void) +{ + const struct of_device_id *match; + struct device_node *root; + + root = of_find_node_by_path("/"); + if (!root) + return ERR_PTR(-ENODEV); + + match = of_match_node(qcom_ubwc_configs, root); + of_node_put(root); + if (!match) { + pr_err("Couldn't find UBWC config data for this platform!\n"); + return ERR_PTR(-EINVAL); + } + + return match->data; +} diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h new file mode 100644 index 0000000000000000000000000000000000000000..450106e6aea06f9f752bb7312ec3074e375eee4d --- /dev/null +++ b/include/linux/soc/qcom/ubwc.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018, The Linux Foundation + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __QCOM_UBWC_H__ +#define __QCOM_UBWC_H__ + +#include + +struct qcom_ubwc_cfg_data { + u32 ubwc_enc_version; + /* Can be read from MDSS_BASE + 0x58 */ + u32 ubwc_dec_version; + u32 ubwc_swizzle; + int highest_bank_bit; + bool ubwc_bank_spread; + bool macrotile_mode; + u32 mdss_reg_bus_bw; +}; + +#define UBWC_1_0 0x10000000 +#define UBWC_2_0 0x20000000 +#define UBWC_3_0 0x30000000 +#define UBWC_4_0 0x40000000 +#define UBWC_4_3 0x40030000 + +const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void); + +#endif /* __QCOM_UBWC_H__ */ From patchwork Thu May 8 18:12:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 888859 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E5FA2874EE; Thu, 8 May 2025 18:13:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Thu, 8 May 2025 18:13:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746728016; bh=jEXyk4/CG4/uqqwjT04hGoBvLebRc7FJW1glFscjkII=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ss7pA5Z+UOJJ+WBR3F7JKUJlppXhDBGUwPcdhoA3cj9YSKzVbuRPkKamELkiyy8Oo SL8HlQZci4AlN9mnh5ctpkwBBctnyLyhoOZ3atEyHa51CmIfe4bcPcxorTlUMB/65n XNCTfHIOydw1cix//C2Eg7nZrECjtsOkRmz6QD5oW3nP33oIcLVipEUI4O4YHS2zfm nK7ZrrXRmznGhoEFVlvCrYYrhkmw01IWPU3SToMzTANJp5Bxl6gRe6/ehGk6fRwBmA EMNYN4MMlcJ3g28yXWBBgT2Wj2i3NX+xu//T2uCOvagcC4Yql6Y5jI6PnBRezZDRl4 chjaNy+rN+QtQ== From: Konrad Dybcio Date: Thu, 08 May 2025 20:12:34 +0200 Subject: [PATCH RFT 02/14] drm/msm: Use the central UBWC config database Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250508-topic-ubwc_central-v1-2-035c4c5cbe50@oss.qualcomm.com> References: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> In-Reply-To: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746728002; l=19651; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=sG42gm8yIn4lXx9vfCvzcqHISpqechon007a1c6Ps84=; b=eCu0P8svi/eSy7qYjmLwA4mkOzf+nbCXQdna/eUmcWM3mWheQW68QYieKLCcEVWMNj9XiyLf8 iDjJ57SqKxUAH9ur/IwhEnxVK4SmweRKepPmfB9nyPNqi3z6clQU32x X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio To reduce room for error, move to fetching the config from a central source, so that the data programmed into the hardware is consistent across all multimedia blocks that request it. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 7 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 +- drivers/gpu/drm/msm/msm_mdss.c | 302 ++++------------------------ drivers/gpu/drm/msm/msm_mdss.h | 28 --- 10 files changed, 49 insertions(+), 308 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 7f127e2ae44292f8f5c7ff6a9251c3d7ec8c9f58..6579ac907b83bc8042388e4efbaa250ebe771ac5 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -95,6 +95,7 @@ config DRM_MSM_DPU depends on DRM_MSM select DRM_MSM_MDSS select DRM_DISPLAY_DSC_HELPER + select QCOM_UBWC_CONFIG default y help Compile in support for the Display Processing Unit in diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 32c7c80845533d720683dbcde3978d98f4972cce..54ccb1e5a89c75452ac6d53d201999d1124be8cd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -10,11 +10,11 @@ #include "dpu_hw_sspp.h" #include "dpu_kms.h" -#include "msm_mdss.h" - #include #include +#include + #define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087 /* SSPP registers */ @@ -684,7 +684,7 @@ int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev, const struct dpu_sspp_cfg *cfg, void __iomem *addr, - const struct msm_mdss_data *mdss_data, + const struct qcom_ubwc_cfg_data *mdss_data, const struct dpu_mdss_version *mdss_rev) { struct dpu_hw_sspp *hw_pipe; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 56a0edf2a57c6dcef7cddf4a1bcd6f6df5ad60f6..7957a3ab6b68cbbd2fd9e1f48673b42d1c8a225a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -308,7 +308,7 @@ struct dpu_hw_sspp_ops { struct dpu_hw_sspp { struct dpu_hw_blk base; struct dpu_hw_blk_reg_map hw; - const struct msm_mdss_data *ubwc; + const struct qcom_ubwc_cfg_data *ubwc; /* Pipe */ enum dpu_sspp idx; @@ -323,7 +323,7 @@ struct dpu_kms; struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev, const struct dpu_sspp_cfg *cfg, void __iomem *addr, - const struct msm_mdss_data *mdss_data, + const struct qcom_ubwc_cfg_data *mdss_data, const struct dpu_mdss_version *mdss_rev); int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 1fd82b6747e9058ce11dc2620729921492d5ebdd..6667de3154e078b74f797ce1b92d4625c1503f9e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -20,9 +20,10 @@ #include #include +#include + #include "msm_drv.h" #include "msm_mmu.h" -#include "msm_mdss.h" #include "msm_gem.h" #include "disp/msm_disp_snapshot.h" @@ -1189,10 +1190,10 @@ static int dpu_kms_hw_init(struct msm_kms *kms) goto err_pm_put; } - dpu_kms->mdss = msm_mdss_get_mdss_data(dpu_kms->pdev->dev.parent); + dpu_kms->mdss = qcom_ubwc_config_get_data(); if (IS_ERR(dpu_kms->mdss)) { rc = PTR_ERR(dpu_kms->mdss); - DPU_ERROR("failed to get MDSS data: %d\n", rc); + DPU_ERROR("failed to get UBWC config data: %d\n", rc); goto err_pm_put; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index a57ec2ec106083e8f93578e4307e8b13ae549c08..993cf512f8c509ac4e28a60a1a31b262f4a54f98 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -60,7 +60,7 @@ struct dpu_kms { struct msm_kms base; struct drm_device *dev; const struct dpu_mdss_cfg *catalog; - const struct msm_mdss_data *mdss; + const struct qcom_ubwc_cfg_data *mdss; /* io/register spaces: */ void __iomem *mmio, *vbif[VBIF_MAX]; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 421138bc3cb779c45fcfd5319056f0d31c862452..ba5a46c5c1b501d22c6b28dd82ac761c26d08541 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -17,8 +17,9 @@ #include #include +#include + #include "msm_drv.h" -#include "msm_mdss.h" #include "dpu_kms.h" #include "dpu_hw_sspp.h" #include "dpu_hw_util.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 2e296f79cba1437470eeb30900a650f6f4e334b6..cae85812fe273ba12ef9215e1881f59986bbf969 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -40,7 +40,7 @@ static inline bool reserved_by_other(uint32_t *res_map, int idx, int dpu_rm_init(struct drm_device *dev, struct dpu_rm *rm, const struct dpu_mdss_cfg *cat, - const struct msm_mdss_data *mdss_data, + const struct qcom_ubwc_cfg_data *mdss_data, void __iomem *mmio) { int rc, i; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index aa62966056d489d9c94c61f24051a2f3e7b7ed89..ccd64404f12d3ca3956c8e6df7d1ffddd4f20642 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -69,7 +69,7 @@ struct msm_display_topology { int dpu_rm_init(struct drm_device *dev, struct dpu_rm *rm, const struct dpu_mdss_cfg *cat, - const struct msm_mdss_data *mdss_data, + const struct qcom_ubwc_cfg_data *mdss_data, void __iomem *mmio); int dpu_rm_reserve(struct dpu_rm *rm, diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 709979fcfab6062c0f316f7655823e888638bfea..a0c4b47470deca4b469868c7fdcc2f962723efcb 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -16,7 +16,8 @@ #include #include -#include "msm_mdss.h" +#include + #include "msm_kms.h" #include @@ -36,7 +37,7 @@ struct msm_mdss { unsigned long enabled_mask; struct irq_domain *domain; } irq_controller; - const struct msm_mdss_data *mdss_data; + const struct qcom_ubwc_cfg_data *mdss_data; struct icc_path *mdp_path[2]; u32 num_mdp_paths; struct icc_path *reg_bus_path; @@ -165,7 +166,7 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss) static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) { - const struct msm_mdss_data *data = msm_mdss->mdss_data; + const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); @@ -180,7 +181,7 @@ static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) { - const struct msm_mdss_data *data = msm_mdss->mdss_data; + const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) | MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); @@ -198,7 +199,7 @@ static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) { - const struct msm_mdss_data *data = msm_mdss->mdss_data; + const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); @@ -222,69 +223,6 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) } } -#define MDSS_HW_MAJ_MIN \ - (MDSS_HW_VERSION_MAJOR__MASK | MDSS_HW_VERSION_MINOR__MASK) - -#define MDSS_HW_MSM8996 0x1007 -#define MDSS_HW_MSM8937 0x100e -#define MDSS_HW_MSM8953 0x1010 -#define MDSS_HW_MSM8998 0x3000 -#define MDSS_HW_SDM660 0x3002 -#define MDSS_HW_SDM630 0x3003 - -/* - * MDP5 platforms use generic qcom,mdp5 compat string, so we have to generate this data - */ -static const struct msm_mdss_data *msm_mdss_generate_mdp5_mdss_data(struct msm_mdss *mdss) -{ - struct msm_mdss_data *data; - u32 hw_rev; - - data = devm_kzalloc(mdss->dev, sizeof(*data), GFP_KERNEL); - if (!data) - return NULL; - - hw_rev = readl_relaxed(mdss->mmio + REG_MDSS_HW_VERSION); - hw_rev = FIELD_GET(MDSS_HW_MAJ_MIN, hw_rev); - - if (hw_rev == MDSS_HW_MSM8996 || - hw_rev == MDSS_HW_MSM8937 || - hw_rev == MDSS_HW_MSM8953 || - hw_rev == MDSS_HW_MSM8998 || - hw_rev == MDSS_HW_SDM660 || - hw_rev == MDSS_HW_SDM630) { - data->ubwc_dec_version = UBWC_1_0; - data->ubwc_enc_version = UBWC_1_0; - } - - if (hw_rev == MDSS_HW_MSM8996 || - hw_rev == MDSS_HW_MSM8998) - data->highest_bank_bit = 2; - else - data->highest_bank_bit = 1; - - return data; -} - -const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev) -{ - struct msm_mdss *mdss; - - if (!dev) - return ERR_PTR(-EINVAL); - - mdss = dev_get_drvdata(dev); - - /* - * We could not do it at the probe time, since hw revision register was - * not readable. Fill data structure now for the MDP5 platforms. - */ - if (!mdss->mdss_data && mdss->is_mdp5) - mdss->mdss_data = msm_mdss_generate_mdp5_mdss_data(mdss); - - return mdss->mdss_data; -} - static int msm_mdss_enable(struct msm_mdss *msm_mdss) { int ret, i; @@ -297,9 +235,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) for (i = 0; i < msm_mdss->num_mdp_paths; i++) icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW)); - if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw) + if (msm_mdss->mdss_data && msm_mdss->mdss_data->mdss_reg_bus_bw) icc_set_bw(msm_mdss->reg_bus_path, 0, - msm_mdss->mdss_data->reg_bus_bw); + msm_mdss->mdss_data->mdss_reg_bus_bw); else icc_set_bw(msm_mdss->reg_bus_path, 0, DEFAULT_REG_BW); @@ -450,7 +388,9 @@ static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5 if (!msm_mdss) return ERR_PTR(-ENOMEM); - msm_mdss->mdss_data = of_device_get_match_data(&pdev->dev); + msm_mdss->mdss_data = qcom_ubwc_config_get_data(); + if (IS_ERR(msm_mdss->mdss_data)) + return ERR_CAST(msm_mdss->mdss_data); msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss"); if (IS_ERR(msm_mdss->mmio)) @@ -569,205 +509,31 @@ static void mdss_remove(struct platform_device *pdev) msm_mdss_destroy(mdss); } -static const struct msm_mdss_data msm8998_data = { - .ubwc_enc_version = UBWC_1_0, - .ubwc_dec_version = UBWC_1_0, - .highest_bank_bit = 2, - .reg_bus_bw = 76800, -}; - -static const struct msm_mdss_data qcm2290_data = { - /* no UBWC */ - .highest_bank_bit = 0x2, - .reg_bus_bw = 76800, -}; - -static const struct msm_mdss_data sa8775p_data = { - .ubwc_enc_version = UBWC_4_0, - .ubwc_dec_version = UBWC_4_0, - .ubwc_swizzle = 4, - .ubwc_bank_spread = true, - .highest_bank_bit = 0, - .macrotile_mode = true, - .reg_bus_bw = 74000, -}; - -static const struct msm_mdss_data sar2130p_data = { - .ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */ - .ubwc_dec_version = UBWC_4_3, - .ubwc_swizzle = 6, - .ubwc_bank_spread = true, - .highest_bank_bit = 0, - .macrotile_mode = 1, - .reg_bus_bw = 74000, -}; - -static const struct msm_mdss_data sc7180_data = { - .ubwc_enc_version = UBWC_2_0, - .ubwc_dec_version = UBWC_2_0, - .ubwc_swizzle = 6, - .ubwc_bank_spread = true, - .highest_bank_bit = 0x1, - .reg_bus_bw = 76800, -}; - -static const struct msm_mdss_data sc7280_data = { - .ubwc_enc_version = UBWC_3_0, - .ubwc_dec_version = UBWC_4_0, - .ubwc_swizzle = 6, - .ubwc_bank_spread = true, - .highest_bank_bit = 1, - .macrotile_mode = true, - .reg_bus_bw = 74000, -}; - -static const struct msm_mdss_data sc8180x_data = { - .ubwc_enc_version = UBWC_3_0, - .ubwc_dec_version = UBWC_3_0, - .highest_bank_bit = 3, - .macrotile_mode = true, - .reg_bus_bw = 76800, -}; - -static const struct msm_mdss_data sc8280xp_data = { - .ubwc_enc_version = UBWC_4_0, - .ubwc_dec_version = UBWC_4_0, - .ubwc_swizzle = 6, - .ubwc_bank_spread = true, - .highest_bank_bit = 3, - .macrotile_mode = true, - .reg_bus_bw = 76800, -}; - -static const struct msm_mdss_data sdm670_data = { - .ubwc_enc_version = UBWC_2_0, - .ubwc_dec_version = UBWC_2_0, - .highest_bank_bit = 1, - .reg_bus_bw = 76800, -}; - -static const struct msm_mdss_data sdm845_data = { - .ubwc_enc_version = UBWC_2_0, - .ubwc_dec_version = UBWC_2_0, - .highest_bank_bit = 2, - .reg_bus_bw = 76800, -}; - -static const struct msm_mdss_data sm6350_data = { - .ubwc_enc_version = UBWC_2_0, - .ubwc_dec_version = UBWC_2_0, - .ubwc_swizzle = 6, - .ubwc_bank_spread = true, - .highest_bank_bit = 1, - .reg_bus_bw = 76800, -}; - -static const struct msm_mdss_data sm7150_data = { - .ubwc_enc_version = UBWC_2_0, - .ubwc_dec_version = UBWC_2_0, - .highest_bank_bit = 1, - .reg_bus_bw = 76800, -}; - -static const struct msm_mdss_data sm8150_data = { - .ubwc_enc_version = UBWC_3_0, - .ubwc_dec_version = UBWC_3_0, - .highest_bank_bit = 2, - .reg_bus_bw = 76800, -}; - -static const struct msm_mdss_data sm6115_data = { - .ubwc_enc_version = UBWC_1_0, - .ubwc_dec_version = UBWC_2_0, - .ubwc_swizzle = 7, - .ubwc_bank_spread = true, - .highest_bank_bit = 0x1, - .reg_bus_bw = 76800, -}; - -static const struct msm_mdss_data sm6125_data = { - .ubwc_enc_version = UBWC_1_0, - .ubwc_dec_version = UBWC_3_0, - .ubwc_swizzle = 1, - .highest_bank_bit = 1, -}; - -static const struct msm_mdss_data sm6150_data = { - .ubwc_enc_version = UBWC_2_0, - .ubwc_dec_version = UBWC_2_0, - .highest_bank_bit = 1, - .reg_bus_bw = 76800, -}; - -static const struct msm_mdss_data sm8250_data = { - .ubwc_enc_version = UBWC_4_0, - .ubwc_dec_version = UBWC_4_0, - .ubwc_swizzle = 6, - .ubwc_bank_spread = true, - /* TODO: highest_bank_bit = 2 for LP_DDR4 */ - .highest_bank_bit = 3, - .macrotile_mode = true, - .reg_bus_bw = 76800, -}; - -static const struct msm_mdss_data sm8350_data = { - .ubwc_enc_version = UBWC_4_0, - .ubwc_dec_version = UBWC_4_0, - .ubwc_swizzle = 6, - .ubwc_bank_spread = true, - /* TODO: highest_bank_bit = 2 for LP_DDR4 */ - .highest_bank_bit = 3, - .macrotile_mode = true, - .reg_bus_bw = 74000, -}; - -static const struct msm_mdss_data sm8550_data = { - .ubwc_enc_version = UBWC_4_0, - .ubwc_dec_version = UBWC_4_3, - .ubwc_swizzle = 6, - .ubwc_bank_spread = true, - /* TODO: highest_bank_bit = 2 for LP_DDR4 */ - .highest_bank_bit = 3, - .macrotile_mode = true, - .reg_bus_bw = 57000, -}; - -static const struct msm_mdss_data x1e80100_data = { - .ubwc_enc_version = UBWC_4_0, - .ubwc_dec_version = UBWC_4_3, - .ubwc_swizzle = 6, - .ubwc_bank_spread = true, - /* TODO: highest_bank_bit = 2 for LP_DDR4 */ - .highest_bank_bit = 3, - .macrotile_mode = true, - /* TODO: Add reg_bus_bw with real value */ -}; - static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,mdss" }, - { .compatible = "qcom,msm8998-mdss", .data = &msm8998_data }, - { .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data }, - { .compatible = "qcom,sa8775p-mdss", .data = &sa8775p_data }, - { .compatible = "qcom,sar2130p-mdss", .data = &sar2130p_data }, - { .compatible = "qcom,sdm670-mdss", .data = &sdm670_data }, - { .compatible = "qcom,sdm845-mdss", .data = &sdm845_data }, - { .compatible = "qcom,sc7180-mdss", .data = &sc7180_data }, - { .compatible = "qcom,sc7280-mdss", .data = &sc7280_data }, - { .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data }, - { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data }, - { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data }, - { .compatible = "qcom,sm6125-mdss", .data = &sm6125_data }, - { .compatible = "qcom,sm6150-mdss", .data = &sm6150_data }, - { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data }, - { .compatible = "qcom,sm6375-mdss", .data = &sm6350_data }, - { .compatible = "qcom,sm7150-mdss", .data = &sm7150_data }, - { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data }, - { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data }, - { .compatible = "qcom,sm8350-mdss", .data = &sm8350_data }, - { .compatible = "qcom,sm8450-mdss", .data = &sm8350_data }, - { .compatible = "qcom,sm8550-mdss", .data = &sm8550_data }, - { .compatible = "qcom,sm8650-mdss", .data = &sm8550_data}, - { .compatible = "qcom,x1e80100-mdss", .data = &x1e80100_data}, + { .compatible = "qcom,msm8998-mdss" }, + { .compatible = "qcom,qcm2290-mdss" }, + { .compatible = "qcom,sa8775p-mdss" }, + { .compatible = "qcom,sar2130p-mdss" }, + { .compatible = "qcom,sdm670-mdss" }, + { .compatible = "qcom,sdm845-mdss" }, + { .compatible = "qcom,sc7180-mdss" }, + { .compatible = "qcom,sc7280-mdss" }, + { .compatible = "qcom,sc8180x-mdss" }, + { .compatible = "qcom,sc8280xp-mdss" }, + { .compatible = "qcom,sm6115-mdss" }, + { .compatible = "qcom,sm6125-mdss" }, + { .compatible = "qcom,sm6150-mdss" }, + { .compatible = "qcom,sm6350-mdss" }, + { .compatible = "qcom,sm6375-mdss" }, + { .compatible = "qcom,sm7150-mdss" }, + { .compatible = "qcom,sm8150-mdss" }, + { .compatible = "qcom,sm8250-mdss" }, + { .compatible = "qcom,sm8350-mdss" }, + { .compatible = "qcom,sm8450-mdss" }, + { .compatible = "qcom,sm8550-mdss" }, + { .compatible = "qcom,sm8650-mdss" }, + { .compatible = "qcom,x1e80100-mdss"}, {} }; MODULE_DEVICE_TABLE(of, mdss_dt_match); diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h deleted file mode 100644 index 14dc53704314558841ee1fe08d93309fd2233812..0000000000000000000000000000000000000000 --- a/drivers/gpu/drm/msm/msm_mdss.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2018, The Linux Foundation - */ - -#ifndef __MSM_MDSS_H__ -#define __MSM_MDSS_H__ - -struct msm_mdss_data { - u32 ubwc_enc_version; - /* can be read from register 0x58 */ - u32 ubwc_dec_version; - u32 ubwc_swizzle; - u32 highest_bank_bit; - bool ubwc_bank_spread; - bool macrotile_mode; - u32 reg_bus_bw; -}; - -#define UBWC_1_0 0x10000000 -#define UBWC_2_0 0x20000000 -#define UBWC_3_0 0x30000000 -#define UBWC_4_0 0x40000000 -#define UBWC_4_3 0x40030000 - -const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev); - -#endif /* __MSM_MDSS_H__ */ From patchwork Thu May 8 18:12:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 888619 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6899F2882B1; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MLNmiOMb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 892A4C4CEE7; Thu, 8 May 2025 18:13:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746728019; bh=gKs+6I7HFNL4vgoYUREY/5NovhmbeB9QBo6jMB6yzdY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MLNmiOMbK7gvEJ1JRWBqhM+vuG5q9xeOy2C9zuoA4TCEcLbKS6FCuTMdrxcz682EW 1WAha4yHFV3521TMQAZOTq5HNPS8+y+TeucZGauYOpZ3zOF0uNeiGqxCLsvmQNO/yQ QrXTQeZDMvtuTwHH3IYdqne/cRhY619E0zIP9Hrq425MrbXLjYi0XIhKkaOMWIhidg vTB4MojGWz6EK13yXXER7XWe1yjbphLQQByQlybiGwi6kUBl14seH41KbUYVj6hqDV ySeCBJPtvpRE1OlqUZ4T8RuXzEiQjqk6g1jEe2Vn5Mk0onv2TwG8jaokBDjiKMUFUb LXeLxsutU7bfw== From: Konrad Dybcio Date: Thu, 08 May 2025 20:12:35 +0200 Subject: [PATCH RFT 03/14] drm/msm/adreno: Offset the HBB value by 13 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250508-topic-ubwc_central-v1-3-035c4c5cbe50@oss.qualcomm.com> References: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> In-Reply-To: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746728002; l=5290; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=7Ey6T75TSm0Twsi0E4oRdCq8mhoNTIt1V/RJgSqVTnA=; b=TfGpK+u8EjVv8YFnRQI/mm5Y3HNNfkPgJxRTKHKNDWSDXV44+Sgd5n+s0zc8/3+Q+M/0BzF7A uIfmEsR9wszApiq1TLbkDlCLvYZIxW8zC2DNGpD8VLulqEzVvnyAsHC X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The value the UBWC hardware expects is 13 less than the actual value. To make it easier to migrate to a common UBWC configuration table, defer that logic to the data source (which is currently a number of if-else statements with assignments in case of this driver). Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 7 +++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 30 ++++++++++++------------------ 2 files changed, 15 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 650e5bac225f372e819130b891f1d020b464f17f..67331a7ee750c0d9eeeead9440e5d08b1a09c878 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -833,8 +833,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F); - BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); - hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13; + hbb = adreno_gpu->ubwc_config.highest_bank_bit; gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, hbb << 7); gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, hbb << 1); @@ -1792,9 +1791,9 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) /* Set the highest bank bit */ if (adreno_is_a540(adreno_gpu) || adreno_is_a530(adreno_gpu)) - adreno_gpu->ubwc_config.highest_bank_bit = 15; + adreno_gpu->ubwc_config.highest_bank_bit = 2; else - adreno_gpu->ubwc_config.highest_bank_bit = 14; + adreno_gpu->ubwc_config.highest_bank_bit = 1; /* a5xx only supports UBWC 1.0, these are not configurable */ adreno_gpu->ubwc_config.macrotile_mode = 0; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index bf3758f010f4079aa86f9c658b52a70acf10b488..b161b5cd991fc645dfcd69754b82be9691775ffe 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -592,32 +592,32 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) gpu->ubwc_config.min_acc_len = 0; gpu->ubwc_config.ubwc_swizzle = 0x6; gpu->ubwc_config.macrotile_mode = 0; - gpu->ubwc_config.highest_bank_bit = 15; + gpu->ubwc_config.highest_bank_bit = 2; if (adreno_is_a610(gpu)) { - gpu->ubwc_config.highest_bank_bit = 13; + gpu->ubwc_config.highest_bank_bit = 0; gpu->ubwc_config.min_acc_len = 1; gpu->ubwc_config.ubwc_swizzle = 0x7; } if (adreno_is_a618(gpu)) - gpu->ubwc_config.highest_bank_bit = 14; + gpu->ubwc_config.highest_bank_bit = 1; if (adreno_is_a619(gpu)) /* TODO: Should be 14 but causes corruption at e.g. 1920x1200 on DP */ - gpu->ubwc_config.highest_bank_bit = 13; + gpu->ubwc_config.highest_bank_bit = 0; if (adreno_is_a619_holi(gpu)) - gpu->ubwc_config.highest_bank_bit = 13; + gpu->ubwc_config.highest_bank_bit = 0; if (adreno_is_a621(gpu)) { - gpu->ubwc_config.highest_bank_bit = 13; + gpu->ubwc_config.highest_bank_bit = 0; gpu->ubwc_config.amsbc = 1; gpu->ubwc_config.uavflagprd_inv = 2; } if (adreno_is_a623(gpu)) { - gpu->ubwc_config.highest_bank_bit = 16; + gpu->ubwc_config.highest_bank_bit = 3; gpu->ubwc_config.amsbc = 1; gpu->ubwc_config.rgb565_predicator = 1; gpu->ubwc_config.uavflagprd_inv = 2; @@ -636,7 +636,7 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) adreno_is_a730(gpu) || adreno_is_a740_family(gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ - gpu->ubwc_config.highest_bank_bit = 16; + gpu->ubwc_config.highest_bank_bit = 3; gpu->ubwc_config.amsbc = 1; gpu->ubwc_config.rgb565_predicator = 1; gpu->ubwc_config.uavflagprd_inv = 2; @@ -644,7 +644,7 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) } if (adreno_is_a663(gpu)) { - gpu->ubwc_config.highest_bank_bit = 13; + gpu->ubwc_config.highest_bank_bit = 0; gpu->ubwc_config.amsbc = 1; gpu->ubwc_config.rgb565_predicator = 1; gpu->ubwc_config.uavflagprd_inv = 2; @@ -653,14 +653,14 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) } if (adreno_is_7c3(gpu)) { - gpu->ubwc_config.highest_bank_bit = 14; + gpu->ubwc_config.highest_bank_bit = 1; gpu->ubwc_config.amsbc = 1; gpu->ubwc_config.uavflagprd_inv = 2; gpu->ubwc_config.macrotile_mode = 1; } if (adreno_is_a702(gpu)) { - gpu->ubwc_config.highest_bank_bit = 14; + gpu->ubwc_config.highest_bank_bit = 1; gpu->ubwc_config.min_acc_len = 1; } } @@ -668,13 +668,7 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - /* - * We subtract 13 from the highest bank bit (13 is the minimum value - * allowed by hw) and write the lowest two bits of the remaining value - * as hbb_lo and the one above it as hbb_hi to the hardware. - */ - BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); - u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13; + u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit; u32 hbb_hi = hbb >> 2; u32 hbb_lo = hbb & 3; u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1; From patchwork Thu May 8 18:12:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 888858 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D69B12882DA; Thu, 8 May 2025 18:13:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 8 May 2025 18:13:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746728024; bh=L1yDHV1hA6bvULOD3ci6a6151CWiuV5UXbptlJcu4kg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lAbVtymavHqsYzezQ/0PbugXh+0TQmsyfNb0sxem0j3JX8G5b99uJ5VutdtnWzepN XTQ5/lMW5vJeBAt0L4y14256WJTkhHAwvGThvPFjPzxU0KR3SKZKwaxqKJtZURZptR iXgQqMSkOwKgat0H+6MxtXAbXrAlrfv0U/7wILPnQDM4JLvdubseWW4RAw1NzXOu4T p2SFEkGY2HcUjMcUvpuE0Sg+tYBgZYyMO4LEjiRQ8mm1E5Xw7lXw35TYB6SYeXxKn3 xLnQ42IFzO0JROB2KcAObcbTjd82tO4ICwE2Q16E7HbOuTTvmMlh/ZJggRrTCpKrGU TgG48Iv5PAloQ== From: Konrad Dybcio Date: Thu, 08 May 2025 20:12:36 +0200 Subject: [PATCH RFT 04/14] drm/msm/a6xx: Get a handle to the common UBWC config Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250508-topic-ubwc_central-v1-4-035c4c5cbe50@oss.qualcomm.com> References: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> In-Reply-To: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746728002; l=3470; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=p4HE/DWs11+jjamEyvelb/+uaNoHp2f4kQN5BS4HGmw=; b=aMqKFG1K1L+L3nDLtzCEAH8+8E5RFXdLoDea6EOjlq0HhkWbAHSk5MmddV9WP2mmphz2n4er8 cmxsyvERgTWAY/cm6cfJq68qCBMDoXdOcfJKVGJY4IQN1arHJV0x1m4 X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Start the great despaghettification by getting a pointer to the common UBWC configuration, which houses e.g. UBWC versions that we need to make decisions. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++++++++-- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +++ 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index b161b5cd991fc645dfcd69754b82be9691775ffe..89eb725f0950f3679d6214366cfbd22d5bcf4bc7 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -585,8 +585,13 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]); } -static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) +static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) { + /* Inherit the common config and make some necessary fixups */ + gpu->common_ubwc_cfg = qcom_ubwc_config_get_data(); + if (IS_ERR(gpu->common_ubwc_cfg)) + return -EINVAL; + gpu->ubwc_config.rgb565_predicator = 0; gpu->ubwc_config.uavflagprd_inv = 0; gpu->ubwc_config.min_acc_len = 0; @@ -663,6 +668,8 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) gpu->ubwc_config.highest_bank_bit = 1; gpu->ubwc_config.min_acc_len = 1; } + + return 0; } static void a6xx_set_ubwc_config(struct msm_gpu *gpu) @@ -2540,7 +2547,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, a6xx_fault_handler); - a6xx_calc_ubwc_config(adreno_gpu); + ret = a6xx_calc_ubwc_config(adreno_gpu); + if (ret) { + a6xx_destroy(&(a6xx_gpu->base.base)); + return ERR_PTR(ret); + } + /* Set up the preemption specific bits and pieces for each ringbuffer */ a6xx_preempt_init(gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 2348ffb35f7eb73a26da47881901d9111dca1ad9..b7f7eb8dcb272394dce8ed1e68310a394c1734a9 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1149,6 +1149,12 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, speedbin = 0xffff; adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); + adreno_gpu->common_ubwc_cfg = devm_kzalloc(dev, + sizeof(*adreno_gpu->common_ubwc_cfg), + GFP_KERNEL); + if (!adreno_gpu->common_ubwc_cfg) + return -ENOMEM; + gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); if (!gpu_name) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index a8f4bf416e64fadbd1c61c991db13d539581e324..06be95d3efaee94e4107a484ad3132e0a6a9ea46 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -12,6 +12,8 @@ #include #include +#include + #include "msm_gpu.h" #include "adreno_common.xml.h" @@ -243,6 +245,7 @@ struct adreno_gpu { */ u32 macrotile_mode; } ubwc_config; + const struct qcom_ubwc_cfg_data *common_ubwc_cfg; /* * Register offsets are different between some GPUs. From patchwork Thu May 8 18:12:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 888618 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D2B62882DA; Thu, 8 May 2025 18:13:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728028; cv=none; b=Qp4DEw5qqq5p0Ze4puxxzs+2Sedwm+vpTuSjteTfJ5ZpZXhehtB05RUBjJ/PrYUIwzCFeQ4v8OIfCOkXdhf6+OVZzhzQSsKCr9VZZAtYQz3udeKoR/pBf8XQBqFMnUWfPvDsY6pEXCYXPq4U/8xefjXuXvlVRHn2wMb7YuKcWLM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728028; c=relaxed/simple; bh=2n7Xb2GJXoTNjWVaIHHp40CW/ySKabjkTPPfcRdF8Bo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Dd5wTIEUTRxg6T8AxOkIFPeGapikbXTQBUXjL1Taw6F5qzIRsUpfbikM+LrxfaZF0PfgGYs8juDXRanFnF6uKeSdsGTO9ZG2Az6OLDLDW+I/WcvD83Kzg7jltNqdUspFFx6qtD/LVeNxrE6T6E9SqcIxoTxGwyNXF5EVuQ+HiZk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Wa1puvwD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Wa1puvwD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D3AB7C4CEEE; Thu, 8 May 2025 18:13:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746728028; bh=2n7Xb2GJXoTNjWVaIHHp40CW/ySKabjkTPPfcRdF8Bo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Wa1puvwDmCcCVzB2Q7vCb9WwMlWHqsSEuRptmbcyVSDOG64qBwKV/w/wRKnPahAog YobzLJGDsJ8lDpKsqu6z6/x0p2soWZ4xGrPfV+eSOgRMlOo1fd7PYeV+/c18HxXvew EhdABdbS+7O3FFyXrQAf0IJ3VGJ5Ta9mtXdbBHmw5wP7jGD2qBkR0JfWhwezSr10aH XJMdsrSbocJ+xKvL0n2lNKOK/ZWuNvysLGBj2Del3RON8WKjmS2UHGZQxDtZrJ36QT AFkb8O5rBVn3SvVoQBdl/+PQrNdv+eWwkWgokO+V69OkhZeIkNnYOOLIjDnEcsy/q/ W3VsXdiaag/xg== From: Konrad Dybcio Date: Thu, 08 May 2025 20:12:37 +0200 Subject: [PATCH RFT 05/14] drm/msm/a6xx: Resolve the meaning of AMSBC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250508-topic-ubwc_central-v1-5-035c4c5cbe50@oss.qualcomm.com> References: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> In-Reply-To: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746728002; l=3021; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=lOOhIGMEMtxwXLn8PJZj5/WHTRWR+s+rfoTJ83oqth0=; b=BvSt6fXsK771Xd7IXiSXaieaVN4W8J7zyUFJ7ELrDpEtPQXG/z8WZoKKlFyrGrtiG7vAZCyKP 0BlH8exCmp4CcuzaAVXNOfAy8gNQ0T5JBVQyhtgSzFQuLRah+Z3w1wT X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The bit must be set to 1 if the UBWC encoder version is >= 3.0, drop it as a separate field. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 89eb725f0950f3679d6214366cfbd22d5bcf4bc7..5fe0e8e72930320282a856e1ff77994865360854 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -617,21 +617,16 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (adreno_is_a621(gpu)) { gpu->ubwc_config.highest_bank_bit = 0; - gpu->ubwc_config.amsbc = 1; gpu->ubwc_config.uavflagprd_inv = 2; } if (adreno_is_a623(gpu)) { gpu->ubwc_config.highest_bank_bit = 3; - gpu->ubwc_config.amsbc = 1; gpu->ubwc_config.rgb565_predicator = 1; gpu->ubwc_config.uavflagprd_inv = 2; gpu->ubwc_config.macrotile_mode = 1; } - if (adreno_is_a640_family(gpu)) - gpu->ubwc_config.amsbc = 1; - if (adreno_is_a680(gpu)) gpu->ubwc_config.macrotile_mode = 1; @@ -642,7 +637,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) adreno_is_a740_family(gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ gpu->ubwc_config.highest_bank_bit = 3; - gpu->ubwc_config.amsbc = 1; gpu->ubwc_config.rgb565_predicator = 1; gpu->ubwc_config.uavflagprd_inv = 2; gpu->ubwc_config.macrotile_mode = 1; @@ -650,7 +644,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (adreno_is_a663(gpu)) { gpu->ubwc_config.highest_bank_bit = 0; - gpu->ubwc_config.amsbc = 1; gpu->ubwc_config.rgb565_predicator = 1; gpu->ubwc_config.uavflagprd_inv = 2; gpu->ubwc_config.macrotile_mode = 1; @@ -659,7 +652,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (adreno_is_7c3(gpu)) { gpu->ubwc_config.highest_bank_bit = 1; - gpu->ubwc_config.amsbc = 1; gpu->ubwc_config.uavflagprd_inv = 2; gpu->ubwc_config.macrotile_mode = 1; } @@ -675,7 +667,9 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg; u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit; + bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0; u32 hbb_hi = hbb >> 2; u32 hbb_lo = hbb & 3; u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1; @@ -684,7 +678,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, level2_swizzling_dis << 12 | adreno_gpu->ubwc_config.rgb565_predicator << 11 | - hbb_hi << 10 | adreno_gpu->ubwc_config.amsbc << 4 | + hbb_hi << 10 | amsbc << 4 | adreno_gpu->ubwc_config.min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); From patchwork Thu May 8 18:12:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 888857 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 806B1286D60; Thu, 8 May 2025 18:13:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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Thu, 8 May 2025 18:13:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746728033; bh=Lv2H2E4AyyMQYzCZzyIEsB3d9G7LQVe4hPuS8/c3LpI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=dFHAmHWLwAlUiyDGkmCAMkvLk1tF7BGeJ7NLrw8U4VJDzAbQ1vBhqk+JXi1CVFjJB yKJZax6ovjrq1Gwng9U5+5V3IuQdKR44FgnjJLk5owVKIhFSOBYQYIDcrB3pQxWfcU LtecXwy5W+pKdQViuTVkkXvCCPwTQGeffWKYnIV3t33vOYXTKXiDaf05fJrX4Bybn1 7j47TetX94z+9D0H++FFJks+BPvO7KWkJqoEOS0VVA1QPzkhNRoHmE/6o14J60BoPP 6pIE5/5Ad81ho1hnPdogbWRoEmaE82K5+QA1lTLtgza0D9QppaOUtUfXtw+S3hzS53 W4m9v3G8xnEQQ== From: Konrad Dybcio Date: Thu, 08 May 2025 20:12:38 +0200 Subject: [PATCH RFT 06/14] drm/msm/a6xx: Simplify uavflagprd_inv detection Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250508-topic-ubwc_central-v1-6-035c4c5cbe50@oss.qualcomm.com> References: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> In-Reply-To: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746728002; l=2928; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=3SEvTkNZ3L/kNlWcW+k5wOJurVA/HyPxiQtQjhnYwpA=; b=qqviDPJMFQPwKe71QA81ljC4ITfUnxo6ggEkhj/WyqTX3DrnWowALnn8UGZtFl538Y6lNDb0v duHQPtRPjGTA8donlyMaH6m3t+IZo6wHEl43cNGBU0YbIz9vpdfMaSp X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Instead of setting it on a gpu-per-gpu basis, converge it to the intended "is A650 family or A7xx". Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 5fe0e8e72930320282a856e1ff77994865360854..e1eab0906b6c460528da82a94a285ef181e0b479 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -593,7 +593,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) return -EINVAL; gpu->ubwc_config.rgb565_predicator = 0; - gpu->ubwc_config.uavflagprd_inv = 0; gpu->ubwc_config.min_acc_len = 0; gpu->ubwc_config.ubwc_swizzle = 0x6; gpu->ubwc_config.macrotile_mode = 0; @@ -615,15 +614,12 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (adreno_is_a619_holi(gpu)) gpu->ubwc_config.highest_bank_bit = 0; - if (adreno_is_a621(gpu)) { + if (adreno_is_a621(gpu)) gpu->ubwc_config.highest_bank_bit = 0; - gpu->ubwc_config.uavflagprd_inv = 2; - } if (adreno_is_a623(gpu)) { gpu->ubwc_config.highest_bank_bit = 3; gpu->ubwc_config.rgb565_predicator = 1; - gpu->ubwc_config.uavflagprd_inv = 2; gpu->ubwc_config.macrotile_mode = 1; } @@ -638,21 +634,18 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ gpu->ubwc_config.highest_bank_bit = 3; gpu->ubwc_config.rgb565_predicator = 1; - gpu->ubwc_config.uavflagprd_inv = 2; gpu->ubwc_config.macrotile_mode = 1; } if (adreno_is_a663(gpu)) { gpu->ubwc_config.highest_bank_bit = 0; gpu->ubwc_config.rgb565_predicator = 1; - gpu->ubwc_config.uavflagprd_inv = 2; gpu->ubwc_config.macrotile_mode = 1; gpu->ubwc_config.ubwc_swizzle = 0x4; } if (adreno_is_7c3(gpu)) { gpu->ubwc_config.highest_bank_bit = 1; - gpu->ubwc_config.uavflagprd_inv = 2; gpu->ubwc_config.macrotile_mode = 1; } @@ -667,6 +660,7 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu) ? 2 : 0; const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg; u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit; bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0; @@ -689,7 +683,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, level2_swizzling_dis << 12 | hbb_hi << 10 | - adreno_gpu->ubwc_config.uavflagprd_inv << 4 | + uavflagprd_inv << 4 | adreno_gpu->ubwc_config.min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); From patchwork Thu May 8 18:12:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 888617 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82CB2287505; Thu, 8 May 2025 18:13:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728038; cv=none; b=WYC3yDVJozcJ/vOA8epHoglBg70E2tpVG1Czk/dno3845ZztbBKFZ53+YUFUlaNdILPEPjT7DG0/ICnvj2KVVo9a46d578H18Nmk4cpEFxLnCj31/rFaNMi+iJc/xCuaBxAEQK5zcfbVMhjN1G1VCVchVJ19RIOnUJ5NPn6NMxk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728038; c=relaxed/simple; bh=mSJUEvv80r8+KtnSJMAeUi1qshbBWDIsutostsXF7fQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DFgkZMBQfLSXCTrd8yL8aaotyUwAgKkMhVCpf+vjHXH7m/FSIrH5QTxKx2V/TtWIdwGw37lRhdBwwO8G8y8tg59ccHJX58pnQLbckOK8f9Syjm6Y2NEqAiqDRRRPRX6R2QQ24JnhTaUNsXN5TftUHuCJ5XSXAHSCNbUg8EdbGXc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=i4ToPFz8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i4ToPFz8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9774CC4CEE7; Thu, 8 May 2025 18:13:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746728038; bh=mSJUEvv80r8+KtnSJMAeUi1qshbBWDIsutostsXF7fQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=i4ToPFz887Ydu+YQWzhBPo5Y3Ygr1jeZWdWxb/g7WfmhCnNNf6T4eeaz/nyNorphl 28PgfdkmDop4tzXAQqbPdB+24pKjzm8uk9LC9sAQihjm46DU01dVlzZ5f2+cP7wq69 WRbl9B/W9bHz8REP/eZk0TOxtuxPECh/AiX7eE7EhRxxcH8JByEqjQJ3Shz5o377K1 m94GZSxQrpUtQosx8B95xLIIHGl/kwzl6COetZJP0QpOx9PXpfZUQMNpeQh2tn407d TRcvClc/2MNq60YxR6bRbxm0JE1gpQt8Eq1LR43RMbwbi0BUJ1Q5T82gZrHzySM7Gf oReDeEexwu4lg== From: Konrad Dybcio Date: Thu, 08 May 2025 20:12:39 +0200 Subject: [PATCH RFT 07/14] drm/msm/a6xx: Resolve the meaning of UBWC_MODE Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250508-topic-ubwc_central-v1-7-035c4c5cbe50@oss.qualcomm.com> References: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> In-Reply-To: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746728002; l=1198; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=bdgZ+VQB/YhdQ2w9c/AGBkHp8bkhxZzalQyXbZHtSwk=; b=EvO5UGTWwUDaDxdjLGITE3vWhuZs7b8zM2G1C2DJEGe/pbry2U/RNnCvQxcM4a2qYtRqrSZOo lhl/5ozK4GvA3f5npJs12hyYk7iMqMdW72j3h6oZGuIReZNVoYSxNb3 X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio This bit is set iff the UBWC version is 1.0. That notably does not include QCM2290's "no UBWC". Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index e1eab0906b6c460528da82a94a285ef181e0b479..d47726ea8818a9660eadd52d97dde1489a884684 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -663,10 +663,10 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu) ? 2 : 0; const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg; u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit; + bool ubwc_mode = cfg->ubwc_enc_version == UBWC_1_0; bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0; u32 hbb_hi = hbb >> 2; u32 hbb_lo = hbb & 3; - u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1; u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2); gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, From patchwork Thu May 8 18:12:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 888856 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 652E8287512; Thu, 8 May 2025 18:14:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728042; cv=none; b=m4fofwTfj3jEbHH0/PUWZs7yx39RDOiHL+xbn/k+jOOHoY2wsSIS6JaADKQ7fyVNrEB0D0clOafH6zSkqI809ozsYExacBUHUUuIc3c7horwRDcZNrhjUm2hZGbL/VZgnNmD15Y+Q+qeqko0SGgtaI+BvjzqmrYDQpM84TjoKlU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728042; c=relaxed/simple; bh=7xJ6QXHwFEaw3JQWM81q0+vEc7fjCdPMm1L4MVRLeNw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=acoWPxGfzfG0YWMpklrlvG44/j/Lvy7W1dZXFlS+tPjdwjd+J8pQPsWy8SXrduCN8atgKt9ZDoX+eRlt2e8vT0FM0UvWOi3waaXlunNWQTJl9tx3y6G5ZHi44lL7Ll9sOIbiqN25zSXXG8TqqzDO9KHaDW8qISrBgDQEA+Bf0VY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=R5uluKDK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="R5uluKDK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7EB4CC4CEEB; Thu, 8 May 2025 18:13:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746728042; bh=7xJ6QXHwFEaw3JQWM81q0+vEc7fjCdPMm1L4MVRLeNw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=R5uluKDKO5hyPQAbp+97gSnBkxpgb6QYkBGGQnF9a1i9XczHEOBz8LO6acprcy5IE 5rHuKcpqb/HWlc0aBzpUoB+/iIs2ft3mInrNMrvTreqn4/z2x9GkV3iARILIBAEsbK NJmJfdcl3nSasFSe58FnVAQZhorXRztGEVR5geVVUsK8cxfaI8u0FNGp22hhCvHNV+ 4i50HomxufhxZKL937Sy2Hx+N2JNMpGJa0CpacGQLeFNnyrWcECR6ZKSw6S0FbI0V8 EFhHZxeO64CiHgtieYwIA3bOCLoem+5dN1AdJaSXGrbxiNeV42XsnF9cb633WTZg1G HLPjndTi9YXYA== From: Konrad Dybcio Date: Thu, 08 May 2025 20:12:40 +0200 Subject: [PATCH RFT 08/14] drm/msm/a6xx: Replace '2' with BIT(1) in level2_swizzling_dis calc Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250508-topic-ubwc_central-v1-8-035c4c5cbe50@oss.qualcomm.com> References: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> In-Reply-To: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746728002; l=1259; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=/T9oJ7HBRn8Ltit2GfS/Ltk+ksfwO5j8+C9eAHrFRZU=; b=/h9Q8DQ8NQFZaIU0ASNNvwq+lCugMwtcZO6cKkOovZxvS/maK61kuqau+Hu5vhh7R1JtJwHME +MsCuxH7tnFDyDykXdZ4k6xC1u7pKVxpmri44O0UdczyJ/wl824DaE+ X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio ubwc_swizzle is a bitmask. Check for a bit to make it more obvious. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index d47726ea8818a9660eadd52d97dde1489a884684..afe4fa8e9325988af37ff12adb61faae66d746ba 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -662,12 +662,12 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu) ? 2 : 0; const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg; + u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1)); u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit; bool ubwc_mode = cfg->ubwc_enc_version == UBWC_1_0; bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0; u32 hbb_hi = hbb >> 2; u32 hbb_lo = hbb & 3; - u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2); gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, level2_swizzling_dis << 12 | From patchwork Thu May 8 18:12:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 888616 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5501A286D75; Thu, 8 May 2025 18:14:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728047; cv=none; b=C/rGvyN4ANxT5NlNyLpF9m6Umvh9CPwWXAHU4OQ0g4BFhFQwBshkIkCpL2Dc6xkacFYmjygVlzon0qg2wmhR63NpPDwP0ZbD3g374gTRqvo28PnW55FVo7vdvcow7NkjgKCYULnuxzUv0J5skPkVYuwLcn06gxlH/Yst6tWJJMI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728047; c=relaxed/simple; bh=pNIxZjZ2B/51L9q0LkjHEJ+VOHIF4Sj29Z/AUMN2ll4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gJoULA1GdXUVhbkSDuMJDc9wjDW9qG8yNgRWHf8Hlt4Kw7G70S719vmnoqIUix2Hj2P+O474jnMSwgu6UVqvGoJkSubDi7R81zLVg0f6JTdUN5+M1YoifDu0BHBZxYiGIZTs0JX20PDKLNfbYWyEL+D6rMV8kEMXhBYO8pS58Og= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uv55DTsk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uv55DTsk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E679AC4CEEE; Thu, 8 May 2025 18:14:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746728047; bh=pNIxZjZ2B/51L9q0LkjHEJ+VOHIF4Sj29Z/AUMN2ll4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=uv55DTskdWSXkLNuDEp1V0My46NKrg32Ke5lxPC1fH4cwnFUtLq12MPsryhaQoqCb gkvGMPJ0QNw0vUUN6I0qR/87fJ8sAVPbFZM77Ley1Nhf/no9iITmc7o1O1Hw2ecxjR Fpuyf0ZXQkDarzpmJPRNQpWtnrFneWuAZ2kK16upKiNFdwkLmEhgDZOQUCigevtGAH nuYxccp9O3V+aU5DTQwd7I5sh3kLAmoeS1iS+8HEqO5M32zFVVcBGBmUzqeSQY99T0 LQEjNceI4lg1p+/KiVaFufnALVmG/8k6S2xi8RhDnmkU0S7AI+ZnkXUhe4MFbeuFSU OimTFqmBPi6aA== From: Konrad Dybcio Date: Thu, 08 May 2025 20:12:41 +0200 Subject: [PATCH RFT 09/14] drm/msm/a6xx: Resolve the meaning of rgb565_predicator Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250508-topic-ubwc_central-v1-9-035c4c5cbe50@oss.qualcomm.com> References: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> In-Reply-To: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746728002; l=2523; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=z6lGwAxT1SUsyRprEZFFJcrrC3aZdUlc0NVcPu988ts=; b=vmW2Q0ybkgGBJ2RY8AMRpaem1hMRWkeSRx7Zkm9uRGpOK+Eo6NwFmUQMqF1j9zDEAwG77ib7f 5dCOLPwt6LMComgCvBDMenWtN33jIuBvgNemkdxejiYoLZ0jD47SXfN X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio It's supposed to be on when the UBWC encoder version is >= 4.0. Drop the per-GPU assignments. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index afe4fa8e9325988af37ff12adb61faae66d746ba..60f89a2d851a5c383fc14cce4c483f630132a9a6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -592,7 +592,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (IS_ERR(gpu->common_ubwc_cfg)) return -EINVAL; - gpu->ubwc_config.rgb565_predicator = 0; gpu->ubwc_config.min_acc_len = 0; gpu->ubwc_config.ubwc_swizzle = 0x6; gpu->ubwc_config.macrotile_mode = 0; @@ -619,7 +618,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (adreno_is_a623(gpu)) { gpu->ubwc_config.highest_bank_bit = 3; - gpu->ubwc_config.rgb565_predicator = 1; gpu->ubwc_config.macrotile_mode = 1; } @@ -633,13 +631,11 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) adreno_is_a740_family(gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ gpu->ubwc_config.highest_bank_bit = 3; - gpu->ubwc_config.rgb565_predicator = 1; gpu->ubwc_config.macrotile_mode = 1; } if (adreno_is_a663(gpu)) { gpu->ubwc_config.highest_bank_bit = 0; - gpu->ubwc_config.rgb565_predicator = 1; gpu->ubwc_config.macrotile_mode = 1; gpu->ubwc_config.ubwc_swizzle = 0x4; } @@ -662,6 +658,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu) ? 2 : 0; const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg; + bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0; u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1)); u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit; bool ubwc_mode = cfg->ubwc_enc_version == UBWC_1_0; @@ -671,7 +668,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, level2_swizzling_dis << 12 | - adreno_gpu->ubwc_config.rgb565_predicator << 11 | + rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | adreno_gpu->ubwc_config.min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); From patchwork Thu May 8 18:12:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 888855 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E92E28937E; Thu, 8 May 2025 18:14:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728051; cv=none; b=XElq6o3K7T4AJkO1g2tDxCCcpXtJYjU+UbOYWpyKCmccHQ2bDF0/RlFGj/4cveslP/cjkSony+a3n07GWjftKIoakmSY/85z54kG1SZKWTVepty733vkAyUhE99dsrgUMbhzAGR70Tg2FfhyNYrNsSoH9ckSyVgdT2WycFjRmNc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728051; c=relaxed/simple; bh=P3CAccmQOpyaTriYllajUgj/8OsbOl7gbCPh5wyAPJM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DEB3CZbqk8Q4YJH8JXh21jBIbELCZPDgQQN/9qxSLwDG+HrdWAhOJzt9pYsps1XLVDgxZfjkhVwgKpeBcZ+Ih3mNYA4dIGcEoNqul7lkz3N5+keEQ6UQY13GvKOtpCq6eRmv+VDmatWN9rVP4bU8niXbEO05lZGLQAGx20SmWd8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=c81xgx+f; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="c81xgx+f" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B6BC7C4CEE7; Thu, 8 May 2025 18:14:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746728051; bh=P3CAccmQOpyaTriYllajUgj/8OsbOl7gbCPh5wyAPJM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=c81xgx+fiy6dgffAG6iBHvXCl4/CSxdEv/zztbSE+KxruEjqGk+v7YI2jBP/fMfYh EfLLpqyExuFypIznD0X3w89IlcSfa1YYGFJCGBrNH8pZiDI6QXpuXVs4UC0wdYkW3a 4QeSf2pVBgTY87SXhAFKIv/mCnjyHVZVLcvJ+8b78I4CnJn6Odqx95v7nWlGUEX/Sy ArOgTtQimusvb2ij9BLu5ZErhVagw5hiVrQP5V4tgJjjkIDpiSvUQc/HoD1VlzFeSV cldQ6CtExlRNhVivLkDcJaKABtjGSwtZvv95qroyU11EgrbY3k9rMu8hINFqd3ae17 KcQyXASdvZ+8A== From: Konrad Dybcio Date: Thu, 08 May 2025 20:12:42 +0200 Subject: [PATCH RFT 10/14] drm/msm/a6xx: Stop tracking macrotile_mode (again) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250508-topic-ubwc_central-v1-10-035c4c5cbe50@oss.qualcomm.com> References: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> In-Reply-To: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746728002; l=2664; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=fEi+/pRUWH3fcysAlmiv3GwevfiZcPYFy+z1RfmmQ+M=; b=7O9OisKq54zQDkxOW769oCsZ4KdFIAJ6o+e5RqglfIl8U7x05Dq/O6hs5KOCWJ728lr7YIASf MVTFttllawjAdBgfK6I4KGu0OaN8LkiUBvCdY6Ynzpiuh1GUMEu1b7P X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio SC8180X (A680) and SA8775P (A663) require a write to that register, while other SKUs are fine with the default value. Don't overwrite it needlessly, requiring the developer to read the value back from hardware just to put it in the driver again, introducing much more room for error. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 60f89a2d851a5c383fc14cce4c483f630132a9a6..bee7e9685aa3ea282fb20ef479e4d243d28418f7 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -594,7 +594,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) gpu->ubwc_config.min_acc_len = 0; gpu->ubwc_config.ubwc_swizzle = 0x6; - gpu->ubwc_config.macrotile_mode = 0; gpu->ubwc_config.highest_bank_bit = 2; if (adreno_is_a610(gpu)) { @@ -616,13 +615,8 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (adreno_is_a621(gpu)) gpu->ubwc_config.highest_bank_bit = 0; - if (adreno_is_a623(gpu)) { + if (adreno_is_a623(gpu)) gpu->ubwc_config.highest_bank_bit = 3; - gpu->ubwc_config.macrotile_mode = 1; - } - - if (adreno_is_a680(gpu)) - gpu->ubwc_config.macrotile_mode = 1; if (adreno_is_a650(gpu) || adreno_is_a660(gpu) || @@ -631,19 +625,15 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) adreno_is_a740_family(gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ gpu->ubwc_config.highest_bank_bit = 3; - gpu->ubwc_config.macrotile_mode = 1; } if (adreno_is_a663(gpu)) { gpu->ubwc_config.highest_bank_bit = 0; - gpu->ubwc_config.macrotile_mode = 1; gpu->ubwc_config.ubwc_swizzle = 0x4; } - if (adreno_is_7c3(gpu)) { + if (adreno_is_7c3(gpu)) gpu->ubwc_config.highest_bank_bit = 1; - gpu->ubwc_config.macrotile_mode = 1; - } if (adreno_is_a702(gpu)) { gpu->ubwc_config.highest_bank_bit = 1; @@ -691,8 +681,9 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21); - gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL, - adreno_gpu->ubwc_config.macrotile_mode); + /* The reset value only needs altering in some cases */ + if (adreno_is_a680(adreno_gpu) || adreno_is_a663(adreno_gpu)) + gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL, BIT(0)); } static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) From patchwork Thu May 8 18:12:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 888615 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C03B92882B5; Thu, 8 May 2025 18:14:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728058; cv=none; b=D/Z2AMUThe/BcUHrd9WUN3TLNBh9h67LqJWoQoGjtwFSzOdRcbGR6+FOyscANyZr8QnmYmBx8+zATdg1BI87XYWaAznbqATgvOIUai6+mHqSM3A8iPabLx8EQYekvq+ElAOhxjaKXIg0WyhjXGNGaS1DC4uWgf7BJUuPI4Dxkbw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728058; c=relaxed/simple; bh=8liazP8iiXn0BlZa9oKy5jgXneL3dwluFOB+c9XH1O0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RcapmOXYgD/jdMAt3dxyr/cyVcGS1w1eUu/M7HX4kUAWV5gN7AuDhPO7yn0lvYsTLrr3YDzW0i3G+6LeDVnMKQPveZOJIU1BIccKZntHGPM7tsEdPh8HpHOdIunXeOD2Z546dk536thzbJHtbSJQqxSFs5X0bvwrjt4dBMMpGho= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=T442B2qu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="T442B2qu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9CF22C4CEE7; Thu, 8 May 2025 18:14:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746728056; bh=8liazP8iiXn0BlZa9oKy5jgXneL3dwluFOB+c9XH1O0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=T442B2quCVUq4CtEWplge7TOiZlAwYluYMad1aRKOb7Jc2h0uklBS2dRkzgItLsc0 wBS9CTEiFQA3CdIaBdX76AaGR+s0V23TuAIx9w0FHSxJvGxk0GZnYoA4B0fyOMka8N Onr20p7hy2Op0zK9puSVYcNgwv+eJUMbkHVpUHH9ZfeYmndwjkqVR+VtSGYF8uUTGK SZ7VobkoRZjXUAPH5VMwgdNuNz+x+vlmih5kdO9tvHi4eRhfP1E96lU5ZYLfogBKa2 22YipNFzVTZDOTnUXVuvVmOIOB1lxdBfwuJMe7uhccKYN9TPhtlqZ7ytb0V5mgnWVK Ho0WFMc4rCcqw== From: Konrad Dybcio Date: Thu, 08 May 2025 20:12:43 +0200 Subject: [PATCH RFT 11/14] drm/msm/a6xx: Simplify min_acc_len calculation Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250508-topic-ubwc_central-v1-11-035c4c5cbe50@oss.qualcomm.com> References: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> In-Reply-To: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746728002; l=3052; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=Fc7S/eINdi/4ICaiJAsRjbgdY8UoVxF5ddDPMtUvVpo=; b=uQOcNQjU5nXx0fn/fcfoVExyfyF6IkSbNpyrHnOT8eRnOwaxmAT2dyWJnkX+fE09Qc8dNF0A/ Jz5ZC2PforqA3QNVs7J4kP3rWImDthxLtYxNushD7fWGCoFF0gO0haG X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio It's only necessary for some lower end parts. Also rename it to min_acc_len_64b to denote that if set, the minimum access length is 64 bits, 32b otherwise. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index bee7e9685aa3ea282fb20ef479e4d243d28418f7..d297890dfba60c6110fb8571e1f46729390302ed 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -592,13 +592,11 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (IS_ERR(gpu->common_ubwc_cfg)) return -EINVAL; - gpu->ubwc_config.min_acc_len = 0; gpu->ubwc_config.ubwc_swizzle = 0x6; gpu->ubwc_config.highest_bank_bit = 2; if (adreno_is_a610(gpu)) { gpu->ubwc_config.highest_bank_bit = 0; - gpu->ubwc_config.min_acc_len = 1; gpu->ubwc_config.ubwc_swizzle = 0x7; } @@ -635,10 +633,8 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (adreno_is_7c3(gpu)) gpu->ubwc_config.highest_bank_bit = 1; - if (adreno_is_a702(gpu)) { + if (adreno_is_a702(gpu)) gpu->ubwc_config.highest_bank_bit = 1; - gpu->ubwc_config.min_acc_len = 1; - } return 0; } @@ -647,6 +643,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu) ? 2 : 0; + bool min_acc_len_64b = adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu); const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg; bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0; u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1)); @@ -660,18 +657,18 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) level2_swizzling_dis << 12 | rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | - adreno_gpu->ubwc_config.min_acc_len << 3 | + min_acc_len_64b << 3 | hbb_lo << 1 | ubwc_mode); gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, level2_swizzling_dis << 6 | hbb_hi << 4 | - adreno_gpu->ubwc_config.min_acc_len << 3 | + min_acc_len_64b << 3 | hbb_lo << 1 | ubwc_mode); gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, level2_swizzling_dis << 12 | hbb_hi << 10 | uavflagprd_inv << 4 | - adreno_gpu->ubwc_config.min_acc_len << 3 | + min_acc_len_64b << 3 | hbb_lo << 1 | ubwc_mode); if (adreno_is_a7xx(adreno_gpu)) @@ -679,7 +676,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) FIELD_PREP(GENMASK(8, 5), hbb_lo)); gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, - adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21); + min_acc_len_64b << 23 | hbb_lo << 21); /* The reset value only needs altering in some cases */ if (adreno_is_a680(adreno_gpu) || adreno_is_a663(adreno_gpu)) From patchwork Thu May 8 18:12:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 888854 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66866289E33; Thu, 8 May 2025 18:14:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728060; cv=none; b=HwQ359StGc5iXzdjG+b5/NQWfesx1IikyS4RSPpjqM+95p+aHvAMZz92wTzt/Qoyohpyfag7cHMXm4z9MEEe4KCywEJR6fRb5ee1dL+xUDSg1AINb9BrH6d8M+ZWumT8FLCqxGz8mcpueiCYIooUfmq+VSj9hol/1Y1Lp2pSwE0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728060; c=relaxed/simple; bh=3wRg8SWnT3zzRmcOfCUrb+vJkaHBx2o3WHgC2Uh4E3Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LYub/kIAYG9iuRVM4XglMPAr+cIbY1G6eWNONLgxmVZAG6F2u2pqx51E4uDcpNXHliRcUQGiqc+wYz4+28YjKpGzy3eyB2NQ56JSXsS7S+UQUnd9vDk7aBz7F2QkGU3T4dySelcc6LORPNrvqIfWIHv4JG/9cDz69XlQNEAnUnQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=I7EJwodp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="I7EJwodp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C1C4CC4CEEB; Thu, 8 May 2025 18:14:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746728060; bh=3wRg8SWnT3zzRmcOfCUrb+vJkaHBx2o3WHgC2Uh4E3Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=I7EJwodpRna64dnKOIDzvAsxNykzrA8cwXIlVTZ4Ev7eVNvDiAbSAAk431D0h/E2/ A+7p8hjzoKmHCx85LzsUM0j+MWf72Zj84xmht37QFRIRuC8VJTOFGnFpoePPU947HY lnMglKI8qGrvsXe+xe41E5+shp3a0ObrM9SR/bD7yVg5fRS3AmWWzkmSdHBOUC5F4I Ls94nY57hWZs/tp/i/KrAfrWg8il/09082camtmO8ajr5aWVW7UCCcDoXoIbK5pxMT Lx1iF9ZWCS0jUdGIBzH+2lDsTQTETtAhexk3vFOEr+iq3JfUZtl88q8WqVIhccPNtY IS9GYQoQjHUhA== From: Konrad Dybcio Date: Thu, 08 May 2025 20:12:44 +0200 Subject: [PATCH RFT 12/14] drm/msm/adreno: Switch to the common UBWC config struct Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250508-topic-ubwc_central-v1-12-035c4c5cbe50@oss.qualcomm.com> References: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> In-Reply-To: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746728002; l=8657; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=mcNVgT7yDSwQcYtEu57k00J6uXoah00CaRsAdpcylz8=; b=qT0syBFswocBjZiKax6OrcOkrsQy75WrvAfntSInU0Lv0XXb+exzYFEaoKrNFtxuaFC35/Fgc fIRoH5z+JYSC/zATuTwv8k08jXAVOcVz6UgjqhQ4FidAYrJz3zDXGaK X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Now that Adreno specifics are out of the way, use the common config (but leave the HBB hardcoding in place until that is wired up on the other side). Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 10 ++++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 41 ++++++++++++++++++--------------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 ++++------ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 40 +------------------------------- 4 files changed, 34 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 67331a7ee750c0d9eeeead9440e5d08b1a09c878..1344d461c16dfa942b0b65d747eadca507116806 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -833,7 +833,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F); - hbb = adreno_gpu->ubwc_config.highest_bank_bit; + hbb = adreno_gpu->ubwc_config->highest_bank_bit; gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, hbb << 7); gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, hbb << 1); @@ -1791,13 +1791,13 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) /* Set the highest bank bit */ if (adreno_is_a540(adreno_gpu) || adreno_is_a530(adreno_gpu)) - adreno_gpu->ubwc_config.highest_bank_bit = 2; + adreno_gpu->ubwc_config->highest_bank_bit = 2; else - adreno_gpu->ubwc_config.highest_bank_bit = 1; + adreno_gpu->ubwc_config->highest_bank_bit = 1; /* a5xx only supports UBWC 1.0, these are not configurable */ - adreno_gpu->ubwc_config.macrotile_mode = 0; - adreno_gpu->ubwc_config.ubwc_swizzle = 0x7; + adreno_gpu->ubwc_config->macrotile_mode = 0; + adreno_gpu->ubwc_config->ubwc_swizzle = 0x7; adreno_gpu->uche_trap_base = 0x0001ffffffff0000ull; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index d297890dfba60c6110fb8571e1f46729390302ed..28ba0cddd7d222b0a287c7c3a111e123a73b1d39 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -587,34 +587,39 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) { + const struct qcom_ubwc_cfg_data *common_cfg; + struct qcom_ubwc_cfg_data *cfg = gpu->ubwc_config; + /* Inherit the common config and make some necessary fixups */ - gpu->common_ubwc_cfg = qcom_ubwc_config_get_data(); - if (IS_ERR(gpu->common_ubwc_cfg)) + common_cfg = qcom_ubwc_config_get_data(); + if (IS_ERR(common_cfg)) return -EINVAL; - gpu->ubwc_config.ubwc_swizzle = 0x6; - gpu->ubwc_config.highest_bank_bit = 2; + *cfg = *common_cfg; + + cfg->ubwc_swizzle = 0x6; + cfg->highest_bank_bit = 2; if (adreno_is_a610(gpu)) { - gpu->ubwc_config.highest_bank_bit = 0; - gpu->ubwc_config.ubwc_swizzle = 0x7; + cfg->highest_bank_bit = 0; + cfg->ubwc_swizzle = 0x7; } if (adreno_is_a618(gpu)) - gpu->ubwc_config.highest_bank_bit = 1; + cfg->highest_bank_bit = 1; if (adreno_is_a619(gpu)) /* TODO: Should be 14 but causes corruption at e.g. 1920x1200 on DP */ - gpu->ubwc_config.highest_bank_bit = 0; + cfg->highest_bank_bit = 0; if (adreno_is_a619_holi(gpu)) - gpu->ubwc_config.highest_bank_bit = 0; + cfg->highest_bank_bit = 0; if (adreno_is_a621(gpu)) - gpu->ubwc_config.highest_bank_bit = 0; + cfg->highest_bank_bit = 0; if (adreno_is_a623(gpu)) - gpu->ubwc_config.highest_bank_bit = 3; + cfg->highest_bank_bit = 3; if (adreno_is_a650(gpu) || adreno_is_a660(gpu) || @@ -622,19 +627,19 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) adreno_is_a730(gpu) || adreno_is_a740_family(gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ - gpu->ubwc_config.highest_bank_bit = 3; + cfg->highest_bank_bit = 3; } if (adreno_is_a663(gpu)) { - gpu->ubwc_config.highest_bank_bit = 0; - gpu->ubwc_config.ubwc_swizzle = 0x4; + cfg->highest_bank_bit = 0; + cfg->ubwc_swizzle = 0x4; } if (adreno_is_7c3(gpu)) - gpu->ubwc_config.highest_bank_bit = 1; + cfg->highest_bank_bit = 1; if (adreno_is_a702(gpu)) - gpu->ubwc_config.highest_bank_bit = 1; + cfg->highest_bank_bit = 1; return 0; } @@ -644,12 +649,12 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu) ? 2 : 0; bool min_acc_len_64b = adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu); - const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg; + const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->ubwc_config; bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0; u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1)); - u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit; bool ubwc_mode = cfg->ubwc_enc_version == UBWC_1_0; bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0; + u32 hbb = cfg->highest_bank_bit; u32 hbb_hi = hbb >> 2; u32 hbb_lo = hbb & 3; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index b7f7eb8dcb272394dce8ed1e68310a394c1734a9..77f1e29df47e1413e35c688f24503cb4d457e304 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -388,16 +388,16 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, *value = ctx->aspace->va_size; return 0; case MSM_PARAM_HIGHEST_BANK_BIT: - *value = adreno_gpu->ubwc_config.highest_bank_bit; + *value = adreno_gpu->ubwc_config->highest_bank_bit; return 0; case MSM_PARAM_RAYTRACING: *value = adreno_gpu->has_ray_tracing; return 0; case MSM_PARAM_UBWC_SWIZZLE: - *value = adreno_gpu->ubwc_config.ubwc_swizzle; + *value = adreno_gpu->ubwc_config->ubwc_swizzle; return 0; case MSM_PARAM_MACROTILE_MODE: - *value = adreno_gpu->ubwc_config.macrotile_mode; + *value = adreno_gpu->ubwc_config->macrotile_mode; return 0; case MSM_PARAM_UCHE_TRAP_BASE: *value = adreno_gpu->uche_trap_base; @@ -1149,10 +1149,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, speedbin = 0xffff; adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); - adreno_gpu->common_ubwc_cfg = devm_kzalloc(dev, - sizeof(*adreno_gpu->common_ubwc_cfg), - GFP_KERNEL); - if (!adreno_gpu->common_ubwc_cfg) + adreno_gpu->ubwc_config = devm_kzalloc(dev, sizeof(*adreno_gpu->ubwc_config), GFP_KERNEL); + if (!adreno_gpu->ubwc_config) return -ENOMEM; gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 06be95d3efaee94e4107a484ad3132e0a6a9ea46..5d27666c46e29da5177d6fc900effc209c2a5507 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -207,45 +207,7 @@ struct adreno_gpu { /* firmware: */ const struct firmware *fw[ADRENO_FW_MAX]; - struct { - /** - * @rgb565_predicator: Unknown, introduced with A650 family, - * related to UBWC mode/ver 4 - */ - u32 rgb565_predicator; - /** @uavflagprd_inv: Unknown, introduced with A650 family */ - u32 uavflagprd_inv; - /** @min_acc_len: Whether the minimum access length is 64 bits */ - u32 min_acc_len; - /** - * @ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling. - * - * UBWC 1.0 always enables all three levels. - * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3. - * UBWC 4.0 adds the optional ability to disable levels 2 & 3. - * - * This is a bitmask where BIT(0) enables level 1, BIT(1) - * controls level 2, and BIT(2) enables level 3. - */ - u32 ubwc_swizzle; - /** - * @highest_bank_bit: Highest Bank Bit - * - * The Highest Bank Bit value represents the bit of the highest - * DDR bank. This should ideally use DRAM type detection. - */ - u32 highest_bank_bit; - u32 amsbc; - /** - * @macrotile_mode: Macrotile Mode - * - * Whether to use 4-channel macrotiling mode or the newer - * 8-channel macrotiling mode introduced in UBWC 3.1. 0 is - * 4-channel and 1 is 8-channel. - */ - u32 macrotile_mode; - } ubwc_config; - const struct qcom_ubwc_cfg_data *common_ubwc_cfg; + struct qcom_ubwc_cfg_data *ubwc_config; /* * Register offsets are different between some GPUs. From patchwork Thu May 8 18:12:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 888614 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A8972882D3; Thu, 8 May 2025 18:14:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728064; cv=none; b=sc+UYZAbUpDLptpbTVZIS5GefgWwhVuFGMUx5l+atg887bjh+tnoMtBNIA9ad6tMfFFI1a31wNlCCXOGnN7vZdo3tUiv4IFtKUj573l5xdzgXEmFCth1KUpPVFNeeNFj0LDLPxhQ5lw8LzX1k2xrGeru2dma+B9dmcuj02ijCUw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728064; c=relaxed/simple; bh=WveUhGhrtwZKyhlbx/JZP0djDAE6iGTAASLA4GSoKq8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lHUVbi4zdMcaiMEirSUmsdsSVfIlKkRwii9S2zy/W+tHlkyxrJXmQQYJqMx+5wYH6xDpBIJ6UfwBn0vqb8BHlrUXnYYeOzWLdx+yWLlSTQLeXIPnVdwr89nWBSpJ/J0jYDN3QX9CklBuOPwQGQdAhLHOJBPS3iYmm8O1Rvxnt1E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=U/Ogt0UY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="U/Ogt0UY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id ADE8BC4CEE7; Thu, 8 May 2025 18:14:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746728064; bh=WveUhGhrtwZKyhlbx/JZP0djDAE6iGTAASLA4GSoKq8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=U/Ogt0UYTJqIzcVw/WVZUAeiVfqxGS1MATU0J/eVEq/TqTq5hyBL4HBf7Stl8jODR SY5Lja1jbjrEE62Yv6ehAPiTpVIMdLgK7BxTZcDPcvlOYPl2TA8AEMshHUgtXHSKXJ NobecadE3GURQ+HIHLX+uAxmiVAJZ628WJJOeWsIpdHvW/JyuyrTsMgSaQpjvJ8IeZ J8psJ694f4IpHPSResB0UrszkrAXPXgGbk4yRib4E86Iij4BXVbKEM6plceWTlqFrS ntOII7N05k3rFgWVFp+K0yG/fQxT1Ff36m5de1Zen2K6x8+bZiIt5ZusAFMf9YDQIW HwLEV466udvdw== From: Konrad Dybcio Date: Thu, 08 May 2025 20:12:45 +0200 Subject: [PATCH RFT 13/14] drm/msm/a6xx: Drop cfg->ubwc_swizzle override Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250508-topic-ubwc_central-v1-13-035c4c5cbe50@oss.qualcomm.com> References: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> In-Reply-To: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746728002; l=1329; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=QjPo7mRzkyky2v7OT2NwqggCjsaxe9ZY2P7ES9pQ+Ms=; b=hUkxZsMFQYp0KMXnZx6JjiiaS+YsYNUHP+LK5nHiwQ10VsfZl5sc4/2xpLMYRqb98tLUW/0iw x9bNPa2dtEeAVDS3qmpnMVsy9xlR1Eok2iJEH5WmBJ1+7x3LvqSJMUX X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio On A663 (SA8775P) the value matches exactly. On A610, the value matches on SM6115, but is different on SM6125. That turns out not to be a problem, as the bits that differ aren't even interpreted. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 28ba0cddd7d222b0a287c7c3a111e123a73b1d39..d96f8cec854a36a77896d39b88c320c29c787edd 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -597,13 +597,10 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) *cfg = *common_cfg; - cfg->ubwc_swizzle = 0x6; cfg->highest_bank_bit = 2; - if (adreno_is_a610(gpu)) { + if (adreno_is_a610(gpu)) cfg->highest_bank_bit = 0; - cfg->ubwc_swizzle = 0x7; - } if (adreno_is_a618(gpu)) cfg->highest_bank_bit = 1; @@ -630,10 +627,8 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) cfg->highest_bank_bit = 3; } - if (adreno_is_a663(gpu)) { + if (adreno_is_a663(gpu)) cfg->highest_bank_bit = 0; - cfg->ubwc_swizzle = 0x4; - } if (adreno_is_7c3(gpu)) cfg->highest_bank_bit = 1; From patchwork Thu May 8 18:12:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 888853 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B6B32874E4; Thu, 8 May 2025 18:14:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728068; cv=none; b=frHa/LBEFEy4eN5CednVc5Iy+9phj/iNVNzZxORwfVYxixD5ROpBqz6U8TXz+gDT1FX0ZpIvkRU2G0i7oTHOj8FeuGkj2fjLaA33ZACC0PENmu8xqjVIfik/fN6zPFDdWHMMuRCuJPczrTcT0Pc/8RAZSd31FwihhKJoPnHKKTA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728068; c=relaxed/simple; bh=u1ZebpgympfjFZvjfVb9tg/JxIpOvXahhTcaVs0MINU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iSB3tTwf41+Iw6gQYyFk73jWVlJlsb7iOX/V6VK0CNb9da3/LjPz1MjJ6LMuO35pV+WjnW2JBJfvQxsQMsgWPCu/NHGjT87UY7QTGnvGTZhg1ya4PN/BFT0qs71n5XzhCXFEEp0JMfJJarKe2UosCv7ISzvudSeE85wt4jNkoj8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VRZtPlvK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VRZtPlvK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 83948C4CEEE; Thu, 8 May 2025 18:14:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746728067; bh=u1ZebpgympfjFZvjfVb9tg/JxIpOvXahhTcaVs0MINU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=VRZtPlvKPdC6WIMNAsK6bCz/mLWr0CuqGSH88JIpumi+nWKqX3/S+nj4dlDXeP7hP dDanUZ2TPn05JY2CpkI1kTuEew5BDm6AvOvjPMmstpoccXYV7934tGlP/dht8Dw97D Nq6KBECE2xEW77qsByIdFpahBSh5Zs7x8nSPg2T3eopqjrkoQPDp8uwrMg19+uMNGG 8/ZrNZXynqbk1YdlfEYSv8lo2IxOPU/hbh+aUaHsd47JNmdPkYYRlSMcTWVgrYlAqg aMHxf5zJyhoSjABA3PlQnHs3s3e9/0iu62yaXQHojDxznE65OPBGkGTBQKDUgjWgL7 t/aiLjSTh98kg== From: Konrad Dybcio Date: Thu, 08 May 2025 20:12:46 +0200 Subject: [PATCH RFT 14/14] drm/msm/a5xx: Use UBWC data from the common UBWC config struct Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250508-topic-ubwc_central-v1-14-035c4c5cbe50@oss.qualcomm.com> References: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> In-Reply-To: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746728002; l=1816; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=XnxaU3f47vZgMuLum+OH9TEi5T6gf69H/vEopBXcG1g=; b=nF5fxgbJlDwUvAwuyKD0AA2ANMcmgfwbA0I7uxVbogq7qOO9HQid8CBOtWj0FHvBprsyu4Aro s42z6Yphv2RC2LxSoC2UkPNZajzJldeRVjmdYZ1iN2LTyn2nAn1haFJ X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Make use of the SSOT config database, this time including the HBB which doesn't seem to change between configurations. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 1344d461c16dfa942b0b65d747eadca507116806..691393e958cf164b69e7fe1a9df313f813473a35 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1753,6 +1753,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) struct msm_drm_private *priv = dev->dev_private; struct platform_device *pdev = priv->gpu_pdev; struct adreno_platform_config *config = pdev->dev.platform_data; + const struct qcom_ubwc_cfg_data *common_cfg; struct a5xx_gpu *a5xx_gpu = NULL; struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; @@ -1789,15 +1790,12 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) /* Set up the preemption specific bits and pieces for each ringbuffer */ a5xx_preempt_init(gpu); - /* Set the highest bank bit */ - if (adreno_is_a540(adreno_gpu) || adreno_is_a530(adreno_gpu)) - adreno_gpu->ubwc_config->highest_bank_bit = 2; - else - adreno_gpu->ubwc_config->highest_bank_bit = 1; + /* Inherit the common config and make some necessary fixups */ + common_cfg = qcom_ubwc_config_get_data(); + if (IS_ERR(common_cfg)) + return ERR_PTR(-EINVAL); - /* a5xx only supports UBWC 1.0, these are not configurable */ - adreno_gpu->ubwc_config->macrotile_mode = 0; - adreno_gpu->ubwc_config->ubwc_swizzle = 0x7; + *adreno_gpu->ubwc_config = *common_cfg; adreno_gpu->uche_trap_base = 0x0001ffffffff0000ull;