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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 01/17] tcg: Introduce target-specific page data for user-only Date: Thu, 4 Jun 2020 21:17:17 -0700 Message-Id: <20200605041733.415188-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This data can be allocated by page_alloc_target_data() and released by page_set_flags(start, end, prot | PAGE_RESET). This data will be used to hold tag memory for AArch64 MTE. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 20 ++++++++++++++------ accel/tcg/translate-all.c | 28 ++++++++++++++++++++++++++++ linux-user/mmap.c | 5 ++++- linux-user/syscall.c | 4 ++-- 4 files changed, 48 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 2bd023d692..e5f564fa1f 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -266,15 +266,21 @@ extern intptr_t qemu_host_page_mask; #define PAGE_EXEC 0x0004 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) #define PAGE_VALID 0x0008 -/* original state of the write flag (used when tracking self-modifying - code */ +/* + * Original state of the write flag (used when tracking self-modifying code) + */ #define PAGE_WRITE_ORG 0x0010 -/* Invalidate the TLB entry immediately, helpful for s390x - * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */ -#define PAGE_WRITE_INV 0x0040 +/* + * Invalidate the TLB entry immediately, helpful for s390x + * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() + */ +#define PAGE_WRITE_INV 0x0020 +/* For use with page_set_flags: page is being replaced; target_data cleared. */ +#define PAGE_RESET 0x0040 + #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ -#define PAGE_RESERVED 0x0020 +#define PAGE_RESERVED 0x0100 #endif /* Target-specific bits that will be used via page_get_flags(). */ #define PAGE_TARGET_1 0x0080 @@ -289,6 +295,8 @@ int walk_memory_regions(void *, walk_memory_regions_fn); int page_get_flags(target_ulong address); void page_set_flags(target_ulong start, target_ulong end, int flags); int page_check_range(target_ulong start, target_ulong len, int flags); +void *page_get_target_data(target_ulong address); +void *page_alloc_target_data(target_ulong address, size_t size); #endif CPUArchState *cpu_copy(CPUArchState *env); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 42ce1dfcff..a65bc1d4c2 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -111,6 +111,7 @@ typedef struct PageDesc { unsigned int code_write_count; #else unsigned long flags; + void *target_data; #endif #ifndef CONFIG_USER_ONLY QemuSpin lock; @@ -2525,6 +2526,7 @@ int page_get_flags(target_ulong address) void page_set_flags(target_ulong start, target_ulong end, int flags) { target_ulong addr, len; + bool reset_target_data; /* This function should never be called with addresses outside the guest address space. If this assert fires, it probably indicates @@ -2539,6 +2541,8 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) if (flags & PAGE_WRITE) { flags |= PAGE_WRITE_ORG; } + reset_target_data = !(flags & PAGE_VALID) || (flags & PAGE_RESET); + flags &= ~PAGE_RESET; for (addr = start, len = end - start; len != 0; @@ -2552,10 +2556,34 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) p->first_tb) { tb_invalidate_phys_page(addr, 0); } + if (reset_target_data && p->target_data) { + g_free(p->target_data); + p->target_data = NULL; + } p->flags = flags; } } +void *page_get_target_data(target_ulong address) +{ + PageDesc *p = page_find(address >> TARGET_PAGE_BITS); + return p ? p->target_data : NULL; +} + +void *page_alloc_target_data(target_ulong address, size_t size) +{ + PageDesc *p = page_find(address >> TARGET_PAGE_BITS); + void *ret = NULL; + + if (p) { + ret = p->target_data; + if (!ret && (p->flags & PAGE_VALID)) { + p->target_data = ret = g_malloc0(size); + } + } + return ret; +} + int page_check_range(target_ulong start, target_ulong len, int flags) { PageDesc *p; diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 40f03e3174..f9832609b0 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -599,6 +599,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int target_prot, } } the_end1: + page_flags |= PAGE_RESET; page_set_flags(start, start + len, page_flags); the_end: trace_target_mmap_complete(start); @@ -787,9 +788,11 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong old_size, new_addr = -1; } else { new_addr = h2g(host_addr); + /* FIXME: Move page flags and target_data for each page. */ prot = page_get_flags(old_addr); page_set_flags(old_addr, old_addr + old_size, 0); - page_set_flags(new_addr, new_addr + new_size, prot | PAGE_VALID); + page_set_flags(new_addr, new_addr + new_size, + prot | PAGE_VALID | PAGE_RESET); } tb_invalidate_phys_range(new_addr, new_addr + new_size); mmap_unlock(); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 7f6700c54e..d190fb1122 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -4315,8 +4315,8 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_env, raddr=h2g((unsigned long)host_raddr); page_set_flags(raddr, raddr + shm_info.shm_segsz, - PAGE_VALID | PAGE_READ | - ((shmflg & SHM_RDONLY)? 0 : PAGE_WRITE)); + PAGE_VALID | PAGE_RESET | PAGE_READ | + (shmflg & SHM_RDONLY ? 0 : PAGE_WRITE)); for (i = 0; i < N_SHM_REGIONS; i++) { if (!shm_regions[i].in_use) { From patchwork Fri Jun 5 04:17:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187476 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp2024665ilo; Thu, 4 Jun 2020 21:18:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzdoNW6V8NAIR+oPbs9HR3FzyWtFJI2N4KUk7l1813YbzDNxb7gpkUgmYk7WiQB41ttiTGa X-Received: by 2002:a25:c647:: with SMTP id k68mr13043191ybf.345.1591330722558; Thu, 04 Jun 2020 21:18:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591330722; cv=none; d=google.com; s=arc-20160816; b=X6HblEK6FW1OkUnm1VrKoS1lmSlliAnxMH/CDCNrQT0qS31PgPb1BMArZCb8W2usaJ TAiy3XR2nRjGuKQKb88IBDtJGFnzXq7Cm7RTIHwgEbSZUk5bnRm0UXAKTwOR9/WGwKhv fFXatnalsFi1tPQMfEH0KUz7e49w+CvJvhoqJX5ptFLhSR2im7tCSmwsShQva1ZP8L9K NCAzIU0TpXKO5FqfGy04zwaDJuJcHVoRoz8uQP9xMri/PzP9HJHhy4LYMKAdjDprP+k8 WF3bD/hYfo5asNGWfPZzDHmdhV1XTyYYtuN3IwiBmaKITK9C9LFkkWnEbnRC3XFAwCug JShQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=eLZZtVFaB75BQS+spGGXnwizsOQKSuMWVvyzFk16uJw=; b=kzkNmuDtfYcB03rdp06/KTEun3LKkBJMG+0tp0FIGgNn4ce9+SmSIN5eGmjT6A7Yjj mYso1cfoO7nywl2cq6JQxs439JVS+t+K/58stzD6PwxSOjW0T7dp9lax+beejvShZcl7 ja398Gm6bhhGU8QBXZM7B5TYQwAqMXsIzp2FNDOkl18ocop08owN7qwJx/6S9p32BBEg 01OPC7dufq6P4RFxbTu9VhFpz7WwDlutLFgPidV+srjGn5HVAzZBU7rDwBZFAVcSzE2J cZMN11BpUuZHP2hI6clRol2hL+geefRjrhqtSqU9Z3HuJzfQHvRH+NmJ6YE6ORGB3YOI D4Cw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="dkGcpEw/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 02/17] linux-user: Introduce PAGE_ANON Date: Thu, 4 Jun 2020 21:17:18 -0700 Message-Id: <20200605041733.415188-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Record whether the backing page is anonymous, or if it has file backing. This will allow us to get close to the Linux AArch64 ABI for MTE, which allows tag memory only on ram-backed VMAs. The real ABI allows tag memory on files, when those files are on ram-backed filesystems, such as tmpfs. We will not be able to implement that in QEMU linux-user. Thankfully, anonymous memory for malloc arenas is the primary consumer of this feature, so this restricted version should still be of use. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 2 ++ linux-user/mmap.c | 3 +++ 2 files changed, 5 insertions(+) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index e5f564fa1f..3cac7750e4 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -277,6 +277,8 @@ extern intptr_t qemu_host_page_mask; #define PAGE_WRITE_INV 0x0020 /* For use with page_set_flags: page is being replaced; target_data cleared. */ #define PAGE_RESET 0x0040 +/* For linux-user, indicates that the page is MAP_ANON. */ +#define PAGE_ANON 0x0080 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ diff --git a/linux-user/mmap.c b/linux-user/mmap.c index f9832609b0..fdd55986a1 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -599,6 +599,9 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int target_prot, } } the_end1: + if (flags & MAP_ANONYMOUS) { + page_flags |= PAGE_ANON; + } page_flags |= PAGE_RESET; page_set_flags(start, start + len, page_flags); the_end: From patchwork Fri Jun 5 04:17:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187474 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp2024343ilo; Thu, 4 Jun 2020 21:18:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz2gDqmV1ahcm1P2+joeXpnQ/RMyykSCWjidJ2JaN/BnGbi2qv6BguRJOPZvg1nff+J7NgK X-Received: by 2002:a25:4807:: with SMTP id v7mr13584887yba.121.1591330682758; Thu, 04 Jun 2020 21:18:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591330682; cv=none; d=google.com; s=arc-20160816; b=byYqZZEDGDN99oDJL3WN7vSNDgZfby3hkQjvejvViDiYGW3KoJDQp7/wJzu5kuw0wR gp1MLT+xt429UIjPaD4mlYwSqLfKhaSIQ5I8pHSIPqFNKUPrvQJ44/4qm1d+g1Xb+v2U Ucfg0Uii+9bfRo2A6GH8MzREGCJ6VvtF3WYbQrL9DyAKAfWPQFfNZyb5VcMJNGkL7FbF 8mv6RJLY5H8fKeWNB3Xv1CLRmF8P7WZqLo3ZdLFev6RN5BnlZMohXKmJ9qIKg7qTUUsw gAuw++gsmKYrajD2iddTWn8oWzJAg4oOjWTAywP8yJpdCW3AvWhtd2qvRch3xTCI+ePF Av0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZRhkmFyLy+CEyb6J1D7iziceaKpzHBPMdBM2JQyWlqQ=; b=YabkzLN0Es6DN5AVsowE97FRKkLNxjJ13QNzZMyjWLbcVCDAXWaYEg2pyBmTYrDkBQ j+K+gtcbdv2oQrR6nE/p7Ra0zG7Js9DiA/F83K62kWLEg/C/PdO/nIEug/nHHp4hnwck cLyLp6I+XX1FPl0UpjjqI8QMpF2ALWsXjVLvI0TD5Kv1Ypc+RjBljUNhS7piWTlgh7Yw snnnMH+FDgpLZYam2hB6PxkekEqpEzHO3QlMHZgJvV3tYWLyWr+BvviPrw1r5haxSW7o H8mFeFHR/mhshe/MJ78KeTITljICJ6DTvsSGz/R59tMSxhW7ThiTDeZbgiAX8+jIYGps C5kA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Vik2TrY3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 03/17] linux-user: Check for overflow in access_ok Date: Thu, 4 Jun 2020 21:17:19 -0700 Message-Id: <20200605041733.415188-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Verify that addr + size - 1 does not wrap around. Signed-off-by: Richard Henderson --- linux-user/qemu.h | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/linux-user/qemu.h b/linux-user/qemu.h index d36b18b678..2bf35e66ac 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -467,12 +467,19 @@ extern unsigned long guest_stack_size; #define VERIFY_READ 0 #define VERIFY_WRITE 1 /* implies read access */ -static inline int access_ok(int type, abi_ulong addr, abi_ulong size) +static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { - return guest_addr_valid(addr) && - (size == 0 || guest_addr_valid(addr + size - 1)) && - page_check_range((target_ulong)addr, size, - (type == VERIFY_READ) ? PAGE_READ : (PAGE_READ | PAGE_WRITE)) == 0; + if (!guest_addr_valid(addr)) { + return false; + } + if (size != 0 && + (addr + size - 1 < addr || + !guest_addr_valid(addr + size - 1))) { + return false; + } + return page_check_range((target_ulong)addr, size, + (type == VERIFY_READ) ? PAGE_READ : + (PAGE_READ | PAGE_WRITE)) == 0; } /* NOTE __get_user and __put_user use host pointers and don't check access. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 04/17] linux-user: Tidy VERIFY_READ/VERIFY_WRITE Date: Thu, 4 Jun 2020 21:17:20 -0700 Message-Id: <20200605041733.415188-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These constants are only ever used with access_ok, and friends. Rather than translating them to PAGE_* bits, let them equal the PAGE_* bits to begin. Signed-off-by: Richard Henderson --- linux-user/qemu.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 2bf35e66ac..a8dde8c609 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -464,8 +464,8 @@ extern unsigned long guest_stack_size; /* user access */ -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 /* implies read access */ +#define VERIFY_READ PAGE_READ +#define VERIFY_WRITE (PAGE_READ | PAGE_WRITE) static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { @@ -477,9 +477,7 @@ static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) !guest_addr_valid(addr + size - 1))) { return false; } - return page_check_range((target_ulong)addr, size, - (type == VERIFY_READ) ? PAGE_READ : - (PAGE_READ | PAGE_WRITE)) == 0; + return page_check_range((target_ulong)addr, size, type) == 0; } /* NOTE __get_user and __put_user use host pointers and don't check access. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 05/17] bsd-user: Tidy VERIFY_READ/VERIFY_WRITE Date: Thu, 4 Jun 2020 21:17:21 -0700 Message-Id: <20200605041733.415188-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These constants are only ever used with access_ok, and friends. Rather than translating them to PAGE_* bits, let them equal the PAGE_* bits to begin. Signed-off-by: Richard Henderson --- bsd-user/qemu.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index f8bb1e5459..4076adabd0 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -218,13 +218,12 @@ extern unsigned long x86_stack_size; /* user access */ -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 /* implies read access */ +#define VERIFY_READ PAGE_READ +#define VERIFY_WRITE (PAGE_READ | PAGE_WRITE) -static inline int access_ok(int type, abi_ulong addr, abi_ulong size) +static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { - return page_check_range((target_ulong)addr, size, - (type == VERIFY_READ) ? PAGE_READ : (PAGE_READ | PAGE_WRITE)) == 0; + return page_check_range((target_ulong)addr, size, type) == 0; } /* NOTE __get_user and __put_user use host pointers and don't check access. */ From patchwork Fri Jun 5 04:17:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187481 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp2026035ilo; Thu, 4 Jun 2020 21:21:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwKnN8mZoH4/Le1s1yk/EyxozfMtmNkQ09rnfz9zz+2RvJGdwxvM0XFYA12+05cu9PXbqO0 X-Received: by 2002:a25:9746:: with SMTP id h6mr13220278ybo.409.1591330898704; Thu, 04 Jun 2020 21:21:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591330898; cv=none; d=google.com; s=arc-20160816; b=CXjhCkB82B9jY4LOsaHgvto+Oo5cEEWmCclZ+AbP+R/E1DfT2VTqimX+NWAanU/Kq8 t+ZTa9VJrGohe8yPSHvwKiv8wL76XGWNHJUdGCEY4EEDu3SYk44KN2CFb+Mp86CEOZEA asdo6RtNGGkPyNcD+XIh7q6Zb5maeGsvsIskS3yDP33C6PNKnlqHh6291PUy75+OIyr6 NLpMghAPQK8OpiwUb6Ob792m7aPAaPBNKNBM49zyNanEz69HLt5cGEl2FrrAXEN3KQ8s 2NPISH/r0LT4uU+zKjwTtSOh02buUArcrxgPdv2modXPUbgvtZgN6tfYUDgNIJpJqp4B 3lGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mHdkZW2BtXgCCzUvavDtufJgojf9AzZZHlwJyJIkodU=; b=i1IPbcWBMkkQpWc11kPrZOyWg8k0KOQ69+B/6HWbGn5yBpqgb51g/NfTYnNebPLB58 jWAfPNtWqDkutUqmhUZBAczg7TAVF8Au9QRC3uflZ5k4peamhPj2AWot0TuUvHhb4PDH wSKPa4m8g5vCb/cFO6VW4i7V0KQy1jSirAdLiu85/9WnUwNbFfm6H1+mxEuxoHheTmkY yryWaTe5NxR/1T0nGD/VQjK8JL9WxJ93TpLskxqbiIKcCGYTArFVtMjUZ+kebFoXupl0 DhZGso1mP2CWdboCtcXeibY9bHVVB7gvNKEccLXx+A+WLPO97bqkItYSwbKMtDjTI1tw ow4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=A0tjNfKG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 06/17] linux-user: Do not use guest_addr_valid for h2g_valid Date: Thu, 4 Jun 2020 21:17:22 -0700 Message-Id: <20200605041733.415188-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the only use of guest_addr_valid that does not begin with a guest address, but a host address being transformed to a guest address. We will shortly adjust guest_addr_valid to handle guest memory tags, and the host address should not be subjected to that. Move h2g_valid adjacent to the other h2g macros. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index c14a48f65e..3930362e20 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -77,15 +77,16 @@ typedef uint64_t abi_ptr; #else #define guest_addr_valid(x) ((x) <= GUEST_ADDR_MAX) #endif -#define h2g_valid(x) guest_addr_valid((unsigned long)(x) - guest_base) static inline int guest_range_valid(unsigned long start, unsigned long len) { return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1; } +#define h2g_valid(x) ((uintptr_t)(x) - guest_base <= GUEST_ADDR_MAX) + #define h2g_nocheck(x) ({ \ - unsigned long __ret = (unsigned long)(x) - guest_base; \ + uintptr_t __ret = (uintptr_t)(x) - guest_base; \ (abi_ptr)__ret; \ }) From patchwork Fri Jun 5 04:17:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187477 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp2025115ilo; Thu, 4 Jun 2020 21:19:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyOH4fFOAxej3zaOCXr3gwiuTEYH4pJmg61nxHem7H72m8ZqhsrK232+FmxOiSE5h6UnY7x X-Received: by 2002:a25:1e41:: with SMTP id e62mr13055609ybe.326.1591330787395; Thu, 04 Jun 2020 21:19:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591330787; cv=none; d=google.com; s=arc-20160816; b=P/QCvw+Eqi00m282Ra1boyh3OWOyY4boz11Ro+H5gAzWwOW0fiCYezN/qQ5cfbNQzD d3LVbm5fe8vZcU8HvloI5s6Uy3JrKSke4fbA7jQahKcZ2QA0zayrlUT53KTCEqxfJhhJ dMod99bFhG/o7r98LxSEOZ7yq3dSkwjdhBbY5fGoOyxl/4XKOFnRLMw6NocQkxvpCsX/ VNso3XlqpLvrm60yPXIBRBwGzQjG5cH4+hr0hrY0XtTqsBcAAEJYOi6DhBuGMMFiJaqj pS68ruxuA5zuIfkEF6O25LE6rwslepaGZu4nk8DUQCPJRNAhlMhoZodxyMYEOiSG7gG1 FB8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IX3UPP0As7IJLtjhajwCoyh2nTlTRQqiCGAXcYWkMx4=; b=aoJ9QSp/OdjiuT5UMxjFShlVxqDfPALiIcNcYuXQ+L/ZEAWpbyzdSf/JACJE62fS94 9enxXifqHOP4nrO48ejzxBtOaKMkcnsvcDve6g77jTtd/xoJqGdrg0czx18ICwhUW2fm 27HlXXMD575GE+baZ8QhyEL4owvU5vGljmoDQ4gLiaN0KIUyVnYYhtgjA1XKAlYKJrU8 r1ezv7UsNFakMLEgLd20P03tM1EqgCGlLHlNEmAwNb42FNGYUyAbhkHStv/Hbjm6WAqc 3So0FKNcwe8qsALq+4/+pBBuZhYPK4wQnu/vjiM/m2YSUzp6MFm2pS9DVZsB/9NWzuV3 1caw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=c5IIcB5F; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 07/17] linux-user: Fix guest_addr_valid vs reserved_va Date: Thu, 4 Jun 2020 21:17:23 -0700 Message-Id: <20200605041733.415188-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We must always use GUEST_ADDR_MAX, because even 32-bit hosts can use -R to restrict the memory address of the guest. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 3930362e20..066cf33f70 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -72,11 +72,10 @@ typedef uint64_t abi_ptr; /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ #define g2h(x) ((void *)((unsigned long)(abi_ptr)(x) + guest_base)) -#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS -#define guest_addr_valid(x) (1) -#else -#define guest_addr_valid(x) ((x) <= GUEST_ADDR_MAX) -#endif +static inline bool guest_addr_valid(abi_ptr x) +{ + return x <= GUEST_ADDR_MAX; +} static inline int guest_range_valid(unsigned long start, unsigned long len) { From patchwork Fri Jun 5 04:17:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187483 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp2026278ilo; Thu, 4 Jun 2020 21:22:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzEFqLOpxnfVOlvDakpZsl3X0H95807VSOyTK9WpRalwQFhpzowHb2HZcna2f135lFPL/pC X-Received: by 2002:a25:f413:: with SMTP id q19mr13682166ybd.178.1591330928302; Thu, 04 Jun 2020 21:22:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591330928; cv=none; d=google.com; s=arc-20160816; b=o6pnikrdK09mVK8/nTVk/DmITvwDilxEj+tO3CHtfjl5doVSv8nspBtIshhfI9zB4E gpwKw3P1OpVVtMZmABWx75RHSr9uYlWl8G9EvYQO5UkjRYoVXSEBCaOi4vd0XYET6gau ntFLgJsQmu0oTrkAJDJQbd7kzdZtQLEnTT7oOhga65+h/pkaS2g4mpUx/5DZnj7maCcR WDaOsEb1iWJuy9grQOxZG+jE4sLagxjSALmmfiKo/uEq9/NxRKIGg20DEfl6blTFuLlx 2D6stKBHrsLG0OzQMjwIB/A5RsJTT/DUJ79ct7jwfMhX16XEug2ruHqx7H8fC7T6pdXr epIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nCxIirgN5OzmYmJJvTz1Ncldrcyg3LSoeyCRUE7/tl0=; b=x/HZ1AH0dsckuwvOrWHg3wHkJbQ5Mz2nOfgozPLT2xNW/KaFvT+Tg8WHwUKUaNjbDh IAqfoWd+Yr25iJBqSC5DFBGYj8wNSJl7kMbpcRJNMg+VmTvgv20dc9gi438AFAepEPhW KjoXC2xuLu3cBH0MV+JL6Wwtxyp6ByOKo+MLhT29AsvlEEX84Mx5/a08ah+fBFjYqFYr N2Zy1RSXEzMBHsV4tpOY5L4efw20CXVDaITfqd4Xz4ueiU1kTk47UCgtL/OYGvlFMSAL Uoa8NRQcQToo0+NDKcLxTsBN2juN4isV9s/lD4hU3cgEIwxAc8q4a9raOhrEJ5Esg7Vx Uubw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YxMROiUm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l15si7918583ybt.337.2020.06.04.21.22.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Jun 2020 21:22:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YxMROiUm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56756 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jh3rr-0004gL-QF for patch@linaro.org; Fri, 05 Jun 2020 00:22:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39514) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jh3nf-0004Uk-Cb for qemu-devel@nongnu.org; Fri, 05 Jun 2020 00:17:47 -0400 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:40216) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jh3ne-0000kh-Il for qemu-devel@nongnu.org; Fri, 05 Jun 2020 00:17:47 -0400 Received: by mail-pj1-x1043.google.com with SMTP id s88so2179647pjb.5 for ; Thu, 04 Jun 2020 21:17:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nCxIirgN5OzmYmJJvTz1Ncldrcyg3LSoeyCRUE7/tl0=; b=YxMROiUmSMWoMRilm0Ow7tHnIWiDyjBi33Ml7dfIqbCZtEUDsT+NFO9ubOAnOb0WE3 uBB5vDn6D6ta07XlPURgTyJW7kDEklNuHOr6eYuE7jg7kAbZYBRxGtvuJxRKEC6wRsa1 2Ue0vfJsJXvw1ctA1QOLZDpPztNkwBao6fUlaRzBNJSjj/ruCMXvPZLH6itcx6pu5qko ner6WCZamoZZrIUlVR+FkGMfZXdK3wKzYc2P+/xh888lQsRVawCZ/RrnHsmRHZI/ZtN8 t8WqwqM9ne333TErHpYu+n3naILGXfYnGugrK5UAjjzSEwzcgT0rXCGhSP5UBGbn141p 0OKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nCxIirgN5OzmYmJJvTz1Ncldrcyg3LSoeyCRUE7/tl0=; b=lJneh+VPJtTeT2m8QMgLW2RzzqeUpRP5AWGtVqSAm0UOaYfNjBXI5nltuFPkCb5O1q +OXB4u/ZsVV3U3ep2qzUONHR9z8pxcN3FEkxQ3Y/Es8hbcsvRVB4qx1H9/67cmyCVupU VmE17bsnb8QaotpHxv03Kv4+4GV7EvtMHPNEWeEbMvK7x9JS4bsxXhwqTCMu5JU2SbiN 4tfXq0dNDhyMkcztBO14Zk6eYAnwWtPWmjXYKaWHq8KQJjGvgewx6eqdaqlKfXZofLYj 17l+oIZDCxXlOlVzqhXQHCfjI5z8Q55m+liP9GftV+39Bro/Hcy21udHprtuRNsI4x75 6Piw== X-Gm-Message-State: AOAM530U/8s7Z0VIKeJ2s2ZlQujMQREAa4mW0EOwntLhMCW0Rb/MnTtd u4fhjmf3vb3u9f1e1fFugh5JaG4Ed+o= X-Received: by 2002:a17:90a:6047:: with SMTP id h7mr738751pjm.145.1591330664883; Thu, 04 Jun 2020 21:17:44 -0700 (PDT) Received: from localhost.localdomain (174-21-143-238.tukw.qwest.net. [174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 08/17] exec: Add support for TARGET_TAGGED_ADDRESSES Date: Thu, 4 Jun 2020 21:17:24 -0700 Message-Id: <20200605041733.415188-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The AArch64 Linux ABI has always enabled TBI, but has historically required that pointer tags be removed before a syscall. This has changed in the lead-up to ARMv8.5-MTE, in a way that affects the ABI generically and not specifically to MTE. This patch allows the target to indicate that (1) there are tags and (2) whether or not they should be taken into account at the syscall level. Adjust g2h, guest_addr_valid, and guest_range_valid to ignore pointer tags, similar to how TIF_TAGGED_ADDR alters __range_ok in the arm64 kernel source. The prctl syscall is not not yet updated, so this change by itself has no visible effect. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 22 ++++++++++++++++++---- target/arm/cpu-param.h | 3 +++ bsd-user/main.c | 5 +++++ linux-user/main.c | 5 +++++ 4 files changed, 31 insertions(+), 4 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 066cf33f70..d84847dc70 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -69,17 +69,31 @@ typedef uint64_t abi_ptr; #define TARGET_ABI_FMT_ptr "%"PRIx64 #endif +#ifdef TARGET_TAGGED_ADDRESSES +extern abi_ptr untagged_addr_mask; +static inline abi_ptr untagged_addr(abi_ptr x) +{ + return x & untagged_addr_mask; +} +#else +static inline abi_ptr untagged_addr(abi_ptr x) { return x; } +#endif + /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ -#define g2h(x) ((void *)((unsigned long)(abi_ptr)(x) + guest_base)) +static inline void *g2h(abi_ptr x) +{ + return (void *)(uintptr_t)(untagged_addr(x) + guest_base); +} static inline bool guest_addr_valid(abi_ptr x) { - return x <= GUEST_ADDR_MAX; + return untagged_addr(x) <= GUEST_ADDR_MAX; } -static inline int guest_range_valid(unsigned long start, unsigned long len) +static inline bool guest_range_valid(abi_ptr start, abi_ulong len) { - return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1; + return len - 1 <= GUEST_ADDR_MAX && + untagged_addr(start) <= GUEST_ADDR_MAX - len + 1; } #define h2g_valid(x) ((uintptr_t)(x) - guest_base <= GUEST_ADDR_MAX) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 6321385b46..f922aa0650 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -20,6 +20,9 @@ #ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 12 +# ifdef TARGET_AARCH64 +# define TARGET_TAGGED_ADDRESSES +# endif #else /* * ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 diff --git a/bsd-user/main.c b/bsd-user/main.c index 0bfe46cff9..87c99fc6c2 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -45,6 +45,11 @@ unsigned long guest_base; bool have_guest_base; unsigned long reserved_va; +#ifdef TARGET_TAGGED_ADDRESSES +/* Default to no tagged addresses, i.e. all pointer bits valid. */ +abi_ptr untagged_addr_mask = -1; +#endif + static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX; const char *qemu_uname_release; extern char **environ; diff --git a/linux-user/main.c b/linux-user/main.c index 3597e99bb1..8fcca3f5f1 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -103,6 +103,11 @@ static int last_log_mask; unsigned long reserved_va; +#ifdef TARGET_TAGGED_ADDRESSES +/* Default to no tagged addresses, i.e. all pointer bits valid. */ +abi_ptr untagged_addr_mask = -1; +#endif + static void usage(int exitcode); static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX; From patchwork Fri Jun 5 04:17:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187482 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp2026132ilo; Thu, 4 Jun 2020 21:21:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwVlCbzldcIWKs198NniGsJSKnpo2w238Ckoex6yLLgyvAH1KNW/t4nmc8rQvLfNCHM5Pp+ X-Received: by 2002:a25:9b07:: with SMTP id y7mr13656710ybn.156.1591330911566; Thu, 04 Jun 2020 21:21:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591330911; cv=none; d=google.com; s=arc-20160816; b=yHUZ6NFwhxfos+GjIRhzLxS7jjVGP0Duj02DNXu8B8xMTyS/KAxTl/zmkhfAuYTShX fRHthv9/Mct4mWiHejQTqkKPA1CudcWG99vxEGZLhC4TBTXWzdesSwZgc24Amci11FWJ /Ehxo4VDvm2rs2nDaYohpx9dD5IWJNAQEd3TTNqpRco+alCpZMW38ssWdFzZJTWuMIOs 0SfdH3XljTJrjgSdumk1tkndC2nKr6XTdRaUHHmpSI2suYLeV+oTzY8e1nsDzsXwQMNX L925RLv5elDxejLMrsxkYLmzYxIpqURgMftOcDxbiPfkAjwMKp5/YmkaHwfwMG/v0kUA i7OQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=icu8Xm8+iq0LFQnztaWvz0M6KFnN5WeXG+dX4xSgCB0=; b=wvEinkXY55+NzchheJrv2ySt8bFrCulMkGe46nnLlOo+6kgsAWEMg3WJe1gF9qge7l Aq3u05G8bu6j9ykOSFhI+JazSRJf/o6ZGYCSun25WnOUjYlr6s7Y18pR00eUoTec5qub 2Bgck2LqO+IHtbnBbfIaYQzrUq50/zUDzBrLFfmgv5/2Pch2pdGI/piihmGd2ruqpFkI UzdR+ocjbTJ5t1iCHzXzqTI/bxT44hmo7vzIwEaPOnaP7/aL0KCz13UxkqeR2kvNRvz2 95DDI/zz++E3sa9S0RlXWixSlaHO5uIl+aKO3RIG3kAZAA1TxOkf0CkMxdwJ7gUJBgJO xAwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ENhlwBTP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 09/17] linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE Date: Thu, 4 Jun 2020 21:17:25 -0700 Message-Id: <20200605041733.415188-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the prctl bit that controls whether syscalls accept tagged addresses. See Documentation/arm64/tagged-address-abi.rst in the linux kernel. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_syscall.h | 4 ++++ linux-user/syscall.c | 23 +++++++++++++++++++++++ 2 files changed, 27 insertions(+) -- 2.25.1 diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h index 995e475c73..5fb0bf4a5d 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -29,4 +29,8 @@ struct target_pt_regs { # define TARGET_PR_PAC_APDBKEY (1 << 3) # define TARGET_PR_PAC_APGAKEY (1 << 4) +#define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 +#define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 +# define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) + #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index d190fb1122..e4da53c5b3 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10460,6 +10460,29 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, } } return -TARGET_EINVAL; + case TARGET_PR_SET_TAGGED_ADDR_CTRL: + { + abi_ulong valid_mask = TARGET_PR_TAGGED_ADDR_ENABLE; + + if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + untagged_addr_mask = (arg2 & TARGET_PR_TAGGED_ADDR_ENABLE + ? MAKE_64BIT_MASK(0, 56) : -1); + return 0; + } + case TARGET_PR_GET_TAGGED_ADDR_CTRL: + { + abi_long ret = 0; + + if (arg2 || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + if (~untagged_addr_mask != 0) { + ret |= TARGET_PR_TAGGED_ADDR_ENABLE; + } + return ret; + } #endif /* AARCH64 */ case PR_GET_SECCOMP: case PR_SET_SECCOMP: From patchwork Fri Jun 5 04:17:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187486 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp2027012ilo; Thu, 4 Jun 2020 21:23:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyhauJB0dVuI9COsNtwim0HUlrXu+yxBkvS/U9cG39VKCOtKksvxhmAEoN22lNdLYrfj+Je X-Received: by 2002:a25:4807:: with SMTP id v7mr13605758yba.121.1591331024878; Thu, 04 Jun 2020 21:23:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591331024; cv=none; d=google.com; s=arc-20160816; b=eBUwkpAFBax1uDmXAtKpRMygse+4rbHlCns2LrADfN8Au2IURWAii3BAOk83ixEDN+ B1JBFGNn8j0VmwZpTnTyjyzoEkXfTDrdzMvBao8k0hyH+XaOm3lDTL38PFZijLolw8cy zZBSc7LQ6B7N2Vx3v6nXgojmcChSAzMVjeMDTU3iR9L+jYqJCsffTnYY6Q094LDlShNE ayPBdYvDCOpXgJq6yvNM2LMLLwNevjO7veG9u+bJIvpHPIEA2VfRrpIjM2N/1+HpEOpC ncUUbl8YCsuDSH5t5Ngl743X44JXL5ecRRO8rRd4j5EMpoO3yVXdnQIEAqkIxUpiU7/2 yj9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yLR2Th1A4FLiNvF9RrUXZ7U/jaonjCXwdyobyMFPwns=; b=tojinLj+Vpi/zSqlDmevyhbOr0kdOMSWr1V9CvbJSMyKlv5rgwwzRHkqlXhQtDN+We 4v3m7kt+KXEe/CFJEGwz4gSV6pDOFK3Urcx6F6HCBMw4EtKVpKbTa4Lcq1r7KBtn25ey zLgqfK8UiqGCr0BnCdDsHw6pzt7uAdRnu5GftTeNalMMPNs4QcSCdJrJhJ+28b7PttMQ bz8HJZh/zB741yOCJoYXzoxF8TT4L09IK1gsttimW3mqoVj9iQo4dQuhHwXUyxhOicF3 WPXpvhU+vH93j8kQxVeQuApfmtzCx0a77UOyhDrhJKAbzCJZjpW6tMkjN4VJ3pbRq4w+ 2S3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GOj5nQRM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 10/17] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG Date: Thu, 4 Jun 2020 21:17:26 -0700 Message-Id: <20200605041733.415188-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These prctl fields are required for the function of MTE. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_syscall.h | 9 ++++++ linux-user/syscall.c | 46 +++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) -- 2.25.1 diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h index 5fb0bf4a5d..779ca0c805 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -32,5 +32,14 @@ struct target_pt_regs { #define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 #define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 # define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) +/* MTE tag check fault modes */ +# define TARGET_PR_MTE_TCF_SHIFT 1 +# define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT) +/* MTE tag inclusion mask */ +# define TARGET_PR_MTE_TAG_SHIFT 3 +# define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIFT) #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index e4da53c5b3..9cf3ce872d 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10463,10 +10463,47 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, case TARGET_PR_SET_TAGGED_ADDR_CTRL: { abi_ulong valid_mask = TARGET_PR_TAGGED_ADDR_ENABLE; + CPUARMState *env = cpu_env; + ARMCPU *cpu = env_archcpu(env); + + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |= TARGET_PR_MTE_TCF_MASK; + valid_mask |= TARGET_PR_MTE_TAG_MASK; + } if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { return -TARGET_EINVAL; } + + if (cpu_isar_feature(aa64_mte, cpu)) { + switch (arg2 & TARGET_PR_MTE_TCF_MASK) { + case TARGET_PR_MTE_TCF_NONE: + case TARGET_PR_MTE_TCF_SYNC: + case TARGET_PR_MTE_TCF_ASYNC: + break; + default: + return -EINVAL; + } + + /* + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. + * Note that the syscall values are consistent with hw. + */ + env->cp15.sctlr_el[1] = + deposit64(env->cp15.sctlr_el[1], 38, 2, + arg2 >> TARGET_PR_MTE_TCF_SHIFT); + + /* + * Write PR_MTE_TAG to GCR_EL1[Exclude]. + * Note that the syscall uses an include mask, + * and hardware uses an exclude mask -- invert. + */ + env->cp15.gcr_el1 = + deposit64(env->cp15.gcr_el1, 0, 16, + ~arg2 >> TARGET_PR_MTE_TAG_SHIFT); + arm_rebuild_hflags(env); + } + untagged_addr_mask = (arg2 & TARGET_PR_TAGGED_ADDR_ENABLE ? MAKE_64BIT_MASK(0, 56) : -1); return 0; @@ -10474,6 +10511,8 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, case TARGET_PR_GET_TAGGED_ADDR_CTRL: { abi_long ret = 0; + CPUARMState *env = cpu_env; + ARMCPU *cpu = env_archcpu(env); if (arg2 || arg3 || arg4 || arg5) { return -TARGET_EINVAL; @@ -10481,6 +10520,13 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, if (~untagged_addr_mask != 0) { ret |= TARGET_PR_TAGGED_ADDR_ENABLE; } + if (cpu_isar_feature(aa64_mte, cpu)) { + /* See above. */ + ret |= (extract64(env->cp15.sctlr_el[1], 38, 2) + << TARGET_PR_MTE_TCF_SHIFT); + ret = deposit64(ret, TARGET_PR_MTE_TAG_SHIFT, 16, + ~env->cp15.gcr_el1); + } return ret; } #endif /* AARCH64 */ From patchwork Fri Jun 5 04:17:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187487 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp2027476ilo; Thu, 4 Jun 2020 21:24:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwv+NCz0fFCibi96hnY7OdND3f+gVGv19bnglTnxgvZCGSMoEAw9N6+2n2XFl3aT5UDPZG9 X-Received: by 2002:a25:dc0e:: with SMTP id y14mr12946783ybe.198.1591331090738; Thu, 04 Jun 2020 21:24:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591331090; cv=none; d=google.com; s=arc-20160816; b=r99WPV+z/K8Q7SKasS+FJ+XvfGE+bAwWdb4I0rYewXb5Gqq95BZW1wbX9NJBj9c1lc 94ke/h5njaHZrh2u54fxgGoyQ4Ohd8WAYReqEitgd3q0YlO8UypE2ED2fq/uq8eAXfRX 61UqbpD99elC6BfvGcF/26NvIwRYRcWvf8x/Al+SG5Uv6qjW3kjJq4BPgtgG+3knm1Gg ymPziH9l2kMRhnkxkN/8yOwogSTxAuSxxUegoKVPOHgO7o6KOyrXyDeW+JU6SNOB4+KP W0RivS4Lfb+u7kUQikQTluK8eGqgMK5kc+WOY4Wegz4rJ93/nk5Hs8Ii0ETtWQw3Ur1w jAxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=p6D0SimXYVXC4E7m3TGAGtyiw9jb/y2AGrQNgRl17pM=; b=tdDNB4wPW0u9MmSOLuS2LwiBqhAr32VAKvZonutYAk/Ihto0HYEqbODrwqS+deTFKQ yqE68Du0bXSX9eZy47/ejVGNJGN/Ydaj6H8IHimHr5yI0I24fNvM30e8Gt5/DAkAPlQm t4Sn/8UFhfskEbRLRvCFjA512Lcok051cRaxczaxdnWMHSvkIJlUjxWVFQ3uKyvbSgnR JC/R2OHPiT2iMtbh96FDuxRvuG6m9Oq5QZyshVd7eYTcTApKOy9aQXbudKGEA/huEJUG 4Pd+SUVNm+XHfZlc+BgDZYLnCoM/4oez32UoxKqY+evrjktw7VyDB2ZNicgfXiuSIZ5h 1YGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WmdMO5TG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 11/17] linux-user/aarch64: Implement PROT_MTE Date: Thu, 4 Jun 2020 21:17:27 -0700 Message-Id: <20200605041733.415188-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remember the PROT_MTE bit as PAGE_TARGET_2. Otherwise this does not yet have effect. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 1 + linux-user/syscall_defs.h | 1 + linux-user/mmap.c | 20 ++++++++++++-------- 3 files changed, 14 insertions(+), 8 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 3cac7750e4..7ff10a8b08 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -286,6 +286,7 @@ extern intptr_t qemu_host_page_mask; #endif /* Target-specific bits that will be used via page_get_flags(). */ #define PAGE_TARGET_1 0x0080 +#define PAGE_TARGET_2 0x0100 #if defined(CONFIG_USER_ONLY) void page_dump(FILE *f); diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index 36bdafb3f1..f2bfa3b17f 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -1196,6 +1196,7 @@ struct target_winsize { #ifdef TARGET_AARCH64 #define TARGET_PROT_BTI 0x10 +#define TARGET_PROT_MTE 0x20 #endif /* Common */ diff --git a/linux-user/mmap.c b/linux-user/mmap.c index fdd55986a1..b5618c40bd 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -84,18 +84,22 @@ static int validate_prot_to_pageflags(int *host_prot, int prot) | (prot & PROT_EXEC ? PROT_READ : 0); #ifdef TARGET_AARCH64 - /* - * The PROT_BTI bit is only accepted if the cpu supports the feature. - * Since this is the unusual case, don't bother checking unless - * the bit has been requested. If set and valid, record the bit - * within QEMU's page_flags as PAGE_TARGET_1. - */ - if (prot & TARGET_PROT_BTI) { + { ARMCPU *cpu = ARM_CPU(thread_cpu); - if (cpu_isar_feature(aa64_bti, cpu)) { + /* + * The PROT_BTI bit is only accepted if the cpu supports the feature. + * If set and valid, record the bit within QEMU's page_flags + * as PAGE_TARGET_1. + */ + if ((prot & TARGET_PROT_BTI) && cpu_isar_feature(aa64_bti, cpu)) { valid |= TARGET_PROT_BTI; page_flags |= PAGE_TARGET_1; } + /* Similarly for the PROT_MTE bit; set PAGE_TARGET_2. */ + if ((prot & TARGET_PROT_MTE) && cpu_isar_feature(aa64_mte, cpu)) { + valid |= TARGET_PROT_MTE; + page_flags |= PAGE_TARGET_2; + } } #endif From patchwork Fri Jun 5 04:17:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187480 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp2025438ilo; Thu, 4 Jun 2020 21:20:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwj+ykl98wr1cY5uCzPVvC2Dau181VgQ2g7eqbef8gUE1GK4us+e/sSQKJlCvUGKii0WOQ0 X-Received: by 2002:a25:cac7:: with SMTP id a190mr12505241ybg.223.1591330832915; Thu, 04 Jun 2020 21:20:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591330832; cv=none; d=google.com; s=arc-20160816; b=U3ACc7iGGr7TueI3daxEYn2j3iHge6/Kwdh/X6+DyGKAvCiBhZ55pDlO0MpQbX3mpJ a1vgd/p+W+dWTbjNgX0iTSdos+vXqu88o0E826sTknpyWAqnT/GzwPQgzQsCgaKvf0Xp pWYbaGZFTN3/ftsBSZ33j2l6CI/6pZm5e/VwArJyCPg6xbQohYUmbZCMOzi6uPrOHVlV Cnt/Ne6bUi97YVlECg70e3EqvIF21GURJFBTq1C9+LVNo8GvFytPQtJB9r+EQ/z96u78 W73KEGdJ7syqJS6h8Jl+QjxM9eN9K+y+k5fBrceXTPR1vh+15591MI7VbOQTWOLjMUYT xKXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OzYHxasinbK12hHGjXt3IY3GTdvR0p0In8jS7714bjc=; b=jYjsibueziqEmmHOfif8xaC2dxG4sZqL42a5G0nSRHz0dT7bbOj0kumf7ETQfZ69aY 6N49KuPZhgC3P5YzOFZ5zxXwn7TBCJ/sWKKoeBN2Uj+GFIy5/aZ1LYMng1uBfwol1K2f dntkPLfP1m4X1WxAIj+98jH2rZlakFffjKtdHjXaITtKuyZXUApwGK8rgdJ0kJt6qa2Y YNLlB6LjPE5K9IrvevbVAwTcv6X0qJCbigbjA5hjE2OqHPA/l619uy2TMcwvBiCIdxP0 cWYGVtoShGYVCFJhKT0jACxX53jrdTGi0iWa8WCJm3POisLXiNdAeQ0QzW9VOuvvnENZ WFdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GVjk9AlO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 12/17] linux-user/aarch64: Pass syndrome to EXC_*_ABORT Date: Thu, 4 Jun 2020 21:17:28 -0700 Message-Id: <20200605041733.415188-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" A proper syndrome is required to fill in the proper si_code. Use page_get_flags to determine permission vs translation for user-only. Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 23 ++++++++++++++++++++--- target/arm/tlb_helper.c | 27 +++++++++++++++++++++------ 2 files changed, 41 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 3cca637bb9..ce56e15be2 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -75,7 +75,7 @@ void cpu_loop(CPUARMState *env) { CPUState *cs = env_cpu(env); - int trapnr; + int trapnr, ec, fsc; abi_long ret; target_siginfo_t info; @@ -116,9 +116,26 @@ void cpu_loop(CPUARMState *env) case EXCP_DATA_ABORT: info.si_signo = TARGET_SIGSEGV; info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; info._sifields._sigfault._addr = env->exception.vaddress; + + /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */ + ec = extract32(env->exception.syndrome, 26, 6); + assert(ec == 0x24 || ec == 0x20); + + /* Both EC have the same format for FSC, or close enough. */ + fsc = extract32(env->exception.syndrome, 0, 6); + switch (fsc) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + info.si_code = TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + info.si_code = TARGET_SEGV_ACCERR; + break; + default: + g_assert_not_reached(); + } + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_UNALIGNED: diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index d4e6d37f4f..35d84ac24f 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -10,8 +10,6 @@ #include "internals.h" #include "exec/exec-all.h" -#if !defined(CONFIG_USER_ONLY) - static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, bool same_el, bool ea, @@ -51,6 +49,8 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, return syn; } +#if !defined(CONFIG_USER_ONLY) + static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, ARMMMUFaultInfo *fi) @@ -138,13 +138,28 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, ARMCPU *cpu = ARM_CPU(cs); #ifdef CONFIG_USER_ONLY + int flags, fsc, exc; + unsigned syn; + cpu->env.exception.vaddress = address; - if (access_type == MMU_INST_FETCH) { - cs->exception_index = EXCP_PREFETCH_ABORT; + + flags = page_get_flags(useronly_clean_ptr(address)); + if (flags & PAGE_VALID) { + fsc = 0xf; /* permission fault, level 3 */ } else { - cs->exception_index = EXCP_DATA_ABORT; + fsc = 0x7; /* translation fault, level 3 */ } - cpu_loop_exit_restore(cs, retaddr); + + cpu_restore_state(cs, retaddr, true); + if (access_type == MMU_INST_FETCH) { + exc = EXCP_PREFETCH_ABORT; + syn = syn_insn_abort(0, 0, 0, fsc); + } else { + exc = EXCP_DATA_ABORT; + syn = merge_syn_data_abort(cpu->env.exception.syndrome, 1, 0, 0, 0, + access_type == MMU_DATA_STORE, fsc); + } + raise_exception(&cpu->env, exc, syn, 1); #else hwaddr phys_addr; target_ulong page_size; From patchwork Fri Jun 5 04:17:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187484 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp2026385ilo; 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 13/17] linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault Date: Thu, 4 Jun 2020 21:17:29 -0700 Message-Id: <20200605041733.415188-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- linux-user/aarch64/target_signal.h | 2 ++ linux-user/aarch64/cpu_loop.c | 3 +++ 2 files changed, 5 insertions(+) -- 2.25.1 diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target_signal.h index ddd73169f0..777fb667fe 100644 --- a/linux-user/aarch64/target_signal.h +++ b/linux-user/aarch64/target_signal.h @@ -21,5 +21,7 @@ typedef struct target_sigaltstack { #include "../generic/signal.h" +#define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */ + #define TARGET_ARCH_HAS_SETUP_FRAME #endif /* AARCH64_TARGET_SIGNAL_H */ diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index ce56e15be2..41a68a57bc 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -132,6 +132,9 @@ void cpu_loop(CPUARMState *env) case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ info.si_code = TARGET_SEGV_ACCERR; break; + case 0x11: /* Synchronous Tag Check Fault */ + info.si_code = TARGET_SEGV_MTESERR; + break; default: g_assert_not_reached(); } From patchwork Fri Jun 5 04:17:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187485 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp2026952ilo; Thu, 4 Jun 2020 21:23:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz4zd0cpY7XeEL2le017YUEQLyJarYfIJZRM0Ew2vHjPbPyeIs5o6vMbnu0eqr5Z5IwE4/9 X-Received: by 2002:a25:c647:: with SMTP id k68mr13060169ybf.345.1591331016432; Thu, 04 Jun 2020 21:23:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591331016; cv=none; d=google.com; s=arc-20160816; b=MQQdc1xwgtcgA3esI/JyBnlGnjn07VPkRm8VHYUg17E6uPCF63YY/IleedRWkCsCap xxt70YNWCK572YWmf2vzEZDbzPmqkW2kNQK88Kb1Yc2sxveniHJeDyemnAL0rHMajy7g CY7FZt1pFNVqEZIrQzU9lgFWXKF57HDhO1WgDelfmUuRgkPaSQksgbZP7fm/rcQ+4BwK 8BNWUcTFbbU6E2yyP5HFfSoepJmsoEwUU/QLoqMixX8M7i5hcIKkF+OjiD8J/s21faKm 3hzC6pT9luaJZ10EiuJpWAxxTJv9f69+I8C3amEMV2ld3ovDru8hDIv4FuzbKvlqLs5q o3OQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=025+D4aoylrwlotsdqqyp7BRSM6nAeDFcADkgg9A3QU=; b=WKa8u1sEIeDugaKYpSLiTRpzCdFeabnzIO566gom8xRoskEPfdGuS/KGyCc+XkGMp9 mpW59sRliLKMh2rNHb0tW4l4SGUgTV7rCHVzwo3S4rGG6pZ1f86iau5JEimnjHKaQ5/K rYQWwab1FvQMwWvGXrEqgl3rSpvyAcUIpMW+qqxv9/pzOa7vgis7K0wKf6Ra43Iz/SNV 4yOF2sYsC4bzQhE2mwxQ4hFCL0DCjEcTwbiBi/VBSgxk+TV6MpT7UYWwwtI+I6k6YjxE bfLNgMFNiPEobLETQeNNpXbziUoChFntMtaRhQGRgD1CScYq1tAEQ5hluTE8i4v08jON 4xCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yrmPfvKu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 14/17] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error Date: Thu, 4 Jun 2020 21:17:30 -0700 Message-Id: <20200605041733.415188-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- linux-user/aarch64/target_signal.h | 1 + linux-user/aarch64/cpu_loop.c | 34 +++++++++++++++++++++--------- target/arm/mte_helper.c | 10 +++++++++ 3 files changed, 35 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target_signal.h index 777fb667fe..18013e1b23 100644 --- a/linux-user/aarch64/target_signal.h +++ b/linux-user/aarch64/target_signal.h @@ -21,6 +21,7 @@ typedef struct target_sigaltstack { #include "../generic/signal.h" +#define TARGET_SEGV_MTEAERR 8 /* Asynchronous ARM MTE error */ #define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */ #define TARGET_ARCH_HAS_SETUP_FRAME diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 41a68a57bc..1b2f2b4239 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -71,6 +71,21 @@ put_user_u16(__x, (gaddr)); \ }) +static bool check_mte_async_fault(CPUARMState *env, target_siginfo_t *info) +{ + if (likely(env->cp15.tfsr_el[0] == 0)) { + return false; + } + + env->cp15.tfsr_el[0] = 0; + info->si_signo = TARGET_SIGSEGV; + info->si_errno = 0; + info->_sifields._sigfault._addr = 0; + info->si_code = TARGET_SEGV_MTEAERR; + queue_signal(env, info->si_signo, QEMU_SI_FAULT, info); + return true; +} + /* AArch64 main loop */ void cpu_loop(CPUARMState *env) { @@ -87,15 +102,13 @@ void cpu_loop(CPUARMState *env) switch (trapnr) { case EXCP_SWI: - ret = do_syscall(env, - env->xregs[8], - env->xregs[0], - env->xregs[1], - env->xregs[2], - env->xregs[3], - env->xregs[4], - env->xregs[5], - 0, 0); + if (check_mte_async_fault(env, &info)) { + ret = -TARGET_ERESTARTSYS; + } else { + ret = do_syscall(env, env->xregs[8], env->xregs[0], + env->xregs[1], env->xregs[2], env->xregs[3], + env->xregs[4], env->xregs[5], 0, 0); + } if (ret == -TARGET_ERESTARTSYS) { env->pc -= 4; } else if (ret != -TARGET_QEMU_ESIGRETURN) { @@ -103,7 +116,8 @@ void cpu_loop(CPUARMState *env) } break; case EXCP_INTERRUPT: - /* just indicate that signals should be handled asap */ + /* Just indicate that signals should be handled asap. */ + check_mte_async_fault(env, &info); break; case EXCP_UDEF: info.si_signo = TARGET_SIGILL; diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index b15fa665df..835b6d1ded 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -542,6 +542,16 @@ static void mte_check_fail(CPUARMState *env, int mmu_idx, select = 0; } env->cp15.tfsr_el[el] |= 1 << select; +#ifdef CONFIG_USER_ONLY + /* + * Stand in for a timer irq, setting _TIF_MTE_ASYNC_FAULT, + * which then sends a SIGSEGV when the thread is next scheduled. + * This cpu will return to the main loop at the end of the TB, + * which is rather sooner than "normal". But the alternative + * is waiting until the next syscall. + */ + qemu_cpu_kick(env_cpu(env)); +#endif break; default: From patchwork Fri Jun 5 04:17:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187488 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp2027915ilo; Thu, 4 Jun 2020 21:25:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx25ot1aMPv/ubzgJXAUqEkRnL4ip04jJ2QQPyNb1pjEsUPpyG1mM/OAcqbpMudJWBKVsQf X-Received: by 2002:a25:d8cd:: with SMTP id p196mr14017877ybg.55.1591331143363; Thu, 04 Jun 2020 21:25:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591331143; cv=none; d=google.com; s=arc-20160816; b=DneTrrR4Gz062Zo+rjS6sZg3PCx7jYcGRP3GwT7QeamyYBHlaGmPMOVifK1zdJNF0Y AFVsZJ8LbsgksLl6yRm3uil9nDrdSvKjvoJ8YCRiv5/QWnTcpUh7X3fbhNOVNbGs+G9K Bhf3pAL+kwJ33LFR8DI2IQvdsGQvQFPwsFeh+X6jSqLG65FMixQlUWgk6s+pIG4r/qW7 0YDDk9LfzoGztbkUq/9NIsfiD/YGrkTZIEggH9N0QG2n2jWgHmBn1x08gtVkHgfsRaMk MWpoRyQJk19RZHp7AWeMuT3faVRpgHFMOmrKIWE5ziJzmUDBdBVjOe182IN+VjMj33Yk Peaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CDahIOixg8N2JHR7Ek8lGA826Cs5BmS4mXRyzAL5jqQ=; b=Y1pcFIGN89TQ2+2A+2y7GfBCjGQrojNbsU+kIVhp6jntNhBQS9LFerPsa42CGNwoms 9lraGmMQLGQsZWJy32rJ2HX1QvOD1+0TSaHZAgn+KHQYXo46fO89uS9TgIhKwTykLZT9 8pvK4qaqm2exLtBQIX2M7QlA2IM5JaKsRW6mUywYSbga3nbGczGhNAYMyRvEakNe9Gdm M7mLnC19o7pm0hYomNyNokjmUKueTFA0hBLo8BmN8m827SdFuRDA87Vf6NrE0GCJOBH0 BckrbJGExX8bK3mgtiOwg5dVYVZVE+V66qrUtPvA+rx9nU0PPerqGLR1HGu+8PUjeqLc fARg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Qzvmb+yr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 15/17] target/arm: Add allocation tag storage for user mode Date: Thu, 4 Jun 2020 21:17:31 -0700 Message-Id: <20200605041733.415188-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the now-saved PAGE_ANON and PAGE_TARGET_2 bits, and the per-page saved data. Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 835b6d1ded..0911cebd36 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -76,8 +76,33 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, int tag_size, uintptr_t ra) { #ifdef CONFIG_USER_ONLY - /* Tag storage not implemented. */ - return NULL; + uint64_t clean_ptr = useronly_clean_ptr(ptr); + int flags = page_get_flags(clean_ptr); + uint8_t *tags; + uintptr_t index; + + if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE : PAGE_READ))) { + /* SIGSEGV */ + arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access, + ptr_mmu_idx, false, ra); + g_assert_not_reached(); + } + + /* Require both MAP_ANON and PROT_MTE for the page. */ + if (!(flags & PAGE_ANON) || !(flags & PAGE_TARGET_2)) { + return NULL; + } + + tags = page_get_target_data(clean_ptr); + if (tags == NULL) { + size_t alloc_size = TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); + tags = page_alloc_target_data(clean_ptr, alloc_size); + assert(tags != NULL); + } + + index = extract32(ptr, LOG2_TAG_GRANULE + 1, + TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); + return tags + index; #else uintptr_t index; CPUIOTLBEntry *iotlbentry; From patchwork Fri Jun 5 04:17:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187489 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp2027948ilo; Thu, 4 Jun 2020 21:25:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzl2JcpGg1axOE3aMPSc3MtnZ8b8jp6r6v8ViZ9JyPwayd/uqk9tSrYpU0Krg/nEZUAiVSK X-Received: by 2002:a25:810e:: with SMTP id o14mr12987956ybk.453.1591331149436; Thu, 04 Jun 2020 21:25:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591331149; cv=none; d=google.com; s=arc-20160816; b=lZS58lvKDIkcKCY+9Y6J41E9HhNkOlAgHdq0Vlz1PT8sgS+Ag3qEiXhoANF/bx2utX /abiA7vJD8EDApcWO/dNn8cfhJPBHWwNvIUHLRPJvMHjlQ3h0+HdZ14s+A6/NaZzHMOt 4WodhDgIFUOIVPAX+waKbyrU3JM9+kA/GdAN2N8vW1e/QpH1zTDhZnfXsvfPmtiUGbQF zAsy/Edjevr4R+ZIlYBjrPf/1gUCywdBDePEGDuhgU55arMZm8EXFa+vDQdEcKZc9C1P rTJRRdziXk0fs1YIe7J/+24nucEnJWNm0rjzkkq5yq0nVlFUioi4gK6hZRY7WG1t9dV4 /2Fw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7wl+QdYCs/b+nFYwpri9epwwg1rNtdW9XylmaArLSo0=; b=J0PhT96QvKWV60jYqdj6wltqtUSo2dW6dv+2/CvE7cZmKVsZz3+3THKIYvRIi/3hCP AwNr2NKsHZZwi/M3cRnScmOTZWaK8TR0TI+zvnUc9bCXvZTrq1Fi8uySyqZ742sG+gDc iIFaee5DSD28JrUHFfN5hnr8/ncasjfdVR5uj5J1kYkKgy7Dsd0hv77dhdUvXpMzHvX2 W1M0hlUKlCd9mabYMZnQzNZtf3L2f8m2UkPcGAhnK4pBoue3q56cyqtsmZdAf1YKrmh/ NKEJ83jCNC9jDq3Byy275SpF52VKbZZWT3uB5aHP7JV2ofR2A23XimPkJ0lUfg3GO1SA s5Cg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cQxyorMA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 16/17] target/arm: Enable MTE for user-only Date: Thu, 4 Jun 2020 21:17:32 -0700 Message-Id: <20200605041733.415188-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.25.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 37b7cc2c9c..6395918524 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -39,6 +39,7 @@ #include "kvm_arm.h" #include "disas/capstone.h" #include "fpu/softfloat.h" +#include "qemu/guest-random.h" static void arm_cpu_set_pc(CPUState *cs, vaddr value) { @@ -191,6 +192,22 @@ static void arm_cpu_reset(DeviceState *dev) /* Enable all PAC keys. */ env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB); + /* Enable MTE */ + if (cpu_isar_feature(aa64_mte, cpu)) { + /* Enable tag access, but leave TCF0 as No Effect (0). */ + env->cp15.sctlr_el[1] |= SCTLR_ATA0; + /* + * Exclude all tags, so that tag 0 is always used. + * This corresponds to Linux current->thread.gcr_incl = 0. + */ + env->cp15.gcr_el1 = 0xffff; + /* If RGSR == 0, NextRandomTagBit will always produce 0. */ + do { + qemu_guest_getrandom_nofail(&env->cp15.rgsr_el1, + sizeof(env->cp15.rgsr_el1)); + env->cp15.rgsr_el1 &= 0xffff0fu; + } while (env->cp15.rgsr_el1 == 0); + } /* and to the FP/Neon instructions */ env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); /* and to the SVE instructions */ From patchwork Fri Jun 5 04:17:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187490 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp2028879ilo; Thu, 4 Jun 2020 21:27:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwuOT4NuqwiRQXsbYQ4rmNtYh4SdTtUK97jEuBGpFSLDsfVsUiAEoaQQcG0xuicovifkXKD X-Received: by 2002:a5b:3c2:: with SMTP id t2mr11727784ybp.209.1591331268611; Thu, 04 Jun 2020 21:27:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591331268; cv=none; d=google.com; s=arc-20160816; b=xz3qvZ3AfkQ8tZr3goqECWclEk7f8zztgotXz1wk5gLOz7SYlcJA6gViBJwHyLwgwC bEq7R8PFETzUb2Gn8iR0kE7oQEZ4aX1hIG2eWMPZF2fw0FPXvH3lI/grMXcZi/hOT7v6 atOKWhuSR5zsGaUZqWwhjnxWVyC4E7DDMa9HOoGZQ3lAUJqlK/gZG6544RK6Jm0FDz9q 8qU4Ck4CLNixRAXj3DMRsQYsOWBcNsQYGzlVABZ84+awHNEc1Jpd83Rtp4KlUfMmP1Zu HHvlMoS65/Qr7JVxw2pjmZ2WHDv0p7v/YOAwKewzPTYaAxCDZmpOEMDUhshbyXDDJCug NURg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Kb6rkAj53RRMvC2rZIPmdOIeGY5NNQOnyCUHmHsi04g=; b=quEx/oN72/XpM/72qzQ0FRMNkmxxMrxs5dqujFSnKzKcLbcLZ51eWjCjSYLyM71hS+ tR6vee7M9gKE4Zdn7UKuvnhcZbGeHCP9bnKke0UlnheUhMdPHErr4m+/uT1MpzJg2Xbn oJfwSWT30pT4Zus+Z3Jsx+NufvSKVBxuRbUOvMAnSIgs44F4jCVlXZfm9UwS3823Z64n DHvPXHiZWX2sZDucDsT+SOK5sdcC7gBXDBUCBePa6VakObuVdksizHY33QrpIxtYctiU JkRIu+rSO6FdAmBCGNPr5L7NtvLJyxkl74Adu2Vvo1ez6gaExRiTUmLTvXJZjoaKDaW1 b1Bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yvH8g8df; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 17/17] tests/tcg/aarch64: Add mte smoke tests Date: Thu, 4 Jun 2020 21:17:33 -0700 Message-Id: <20200605041733.415188-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte.h | 54 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/mte-1.c | 25 ++++++++++++++ tests/tcg/aarch64/mte-2.c | 42 ++++++++++++++++++++++++ tests/tcg/aarch64/mte-3.c | 47 +++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 4 +++ 5 files changed, 172 insertions(+) create mode 100644 tests/tcg/aarch64/mte.h create mode 100644 tests/tcg/aarch64/mte-1.c create mode 100644 tests/tcg/aarch64/mte-2.c create mode 100644 tests/tcg/aarch64/mte-3.c -- 2.25.1 diff --git a/tests/tcg/aarch64/mte.h b/tests/tcg/aarch64/mte.h new file mode 100644 index 0000000000..7bcc416e6a --- /dev/null +++ b/tests/tcg/aarch64/mte.h @@ -0,0 +1,54 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef PR_SET_TAGGED_ADDR_CTRL +# define PR_SET_TAGGED_ADDR_CTRL 55 +#endif +#ifndef PR_TAGGED_ADDR_ENABLE +# define PR_TAGGED_ADDR_ENABLE (1UL << 0) +#endif +#ifndef PR_MTE_TCF_SHIFT +# define PR_MTE_TCF_SHIFT 1 +# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TAG_SHIFT 3 +#endif + +#ifndef PROT_MTE +# define PROT_MTE 0x20 +#endif + +#ifndef SEGV_MTEAERR +# define SEGV_MTEAERR 8 +# define SEGV_MTESERR 9 +#endif + +static void enable_mte(int tcf) +{ + int r = prctl(PR_SET_TAGGED_ADDR_CTRL, + PR_TAGGED_ADDR_ENABLE | tcf | (0xfffe << PR_MTE_TAG_SHIFT), + 0, 0, 0); + if (r < 0) { + perror("PR_SET_TAGGED_ADDR_CTRL"); + exit(2); + } +} + +static void *alloc_mte_page(void) +{ + void *p = mmap(NULL, getpagesize(), + PROT_READ | PROT_WRITE | PROT_MTE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (p == MAP_FAILED) { + perror("mmap PROT_MTE"); + exit(2); + } + return p; +} diff --git a/tests/tcg/aarch64/mte-1.c b/tests/tcg/aarch64/mte-1.c new file mode 100644 index 0000000000..e62c842e85 --- /dev/null +++ b/tests/tcg/aarch64/mte-1.c @@ -0,0 +1,25 @@ +/* + * Memory tagging, basic pass cases. + */ + +#include "mte.h" + +int main(int ac, char **av) +{ + int *p0, *p1, *p2; + long c; + + enable_mte(PR_MTE_TCF_NONE); + p0 = alloc_mte_page(); + + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(1)); + assert(p1 != p0); + asm("subp %0,%1,%2" : "=r"(c) : "r"(p0), "r"(p1)); + assert(c == 0); + + asm("stg %0, [%0]" : : "r"(p1)); + asm("ldg %0, [%1]" : "=r"(p2) : "r"(p0), "0"(p0)); + assert(p1 == p2); + + return 0; +} diff --git a/tests/tcg/aarch64/mte-2.c b/tests/tcg/aarch64/mte-2.c new file mode 100644 index 0000000000..68b5708462 --- /dev/null +++ b/tests/tcg/aarch64/mte-2.c @@ -0,0 +1,42 @@ +/* + * Memory tagging, basic fail cases. + */ + +#include "mte.h" + +void pass(int sig, siginfo_t *info, void *uc) +{ + assert(info->si_code == SEGV_MTESERR); + exit(0); +} + +int main(int ac, char **av) +{ + struct sigaction sa; + int *p0, *p1, *p2; + long excl = 1; + + enable_mte(PR_MTE_TCF_SYNC); + p0 = alloc_mte_page(); + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl != 1); + asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl)); + assert(p1 != p2); + + /* Store the tag from the first pointer. */ + asm("stg %0, [%0]" : : "r"(p1)); + + *p1 = 0; + + memset(&sa, 0, sizeof(sa)); + sa.sa_sigaction = pass; + sa.sa_flags = SA_SIGINFO; + sigaction(SIGSEGV, &sa, NULL); + + *p2 = 0; + + abort(); +} diff --git a/tests/tcg/aarch64/mte-3.c b/tests/tcg/aarch64/mte-3.c new file mode 100644 index 0000000000..6f034cdb01 --- /dev/null +++ b/tests/tcg/aarch64/mte-3.c @@ -0,0 +1,47 @@ +/* + * Memory tagging, basic fail cases. + */ + +#include "mte.h" + +void pass(int sig, siginfo_t *info, void *uc) +{ + assert(info->si_code == SEGV_MTEAERR); + exit(0); +} + +int main(int ac, char **av) +{ + struct sigaction sa; + int *p0, *p1, *p2; + long excl = 1; + + enable_mte(PR_MTE_TCF_ASYNC); + p0 = alloc_mte_page(); + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl != 1); + asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl)); + assert(p1 != p2); + + /* Store the tag from the first pointer. */ + asm("stg %0, [%0]" : : "r"(p1)); + + *p1 = 0; + + memset(&sa, 0, sizeof(sa)); + sa.sa_sigaction = pass; + sa.sa_flags = SA_SIGINFO; + sigaction(SIGSEGV, &sa, NULL); + + /* + * Signal for async error will happen eventually. + * For a real kernel this should be after the next IRQ (e.g. timer). + * For qemu linux-user, we kick the cpu and exit at the next TB. + * In either case, loop until this happens (or killed by timeout). + */ + *p2 = 0; + while (1); +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index cf84787eb6..2269c264df 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -31,6 +31,10 @@ bti-%: CFLAGS += -mbranch-protection=standard bti-%: LDFLAGS += -nostdlib endif +# MTE Tests +AARCH64_TESTS += mte-1 mte-2 mte-3 +mte-%: CFLAGS += -march=armv8.5-a+memtag + # Semihosting smoke test for linux-user AARCH64_TESTS += semihosting run-semihosting: semihosting