From patchwork Sat May 3 10:39:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Travkin X-Patchwork-Id: 887022 Received: from box.trvn.ru (box.trvn.ru [45.141.101.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B235D1E3DD0; Sat, 3 May 2025 10:40:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.141.101.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746268809; cv=none; b=i5zmVtZlQW2ZZZi4ecKD8H1ZXhafo3LD5xDzTBfA/vjOYlf7lV9z8GxMZHr+9gA11+XSB/ziJGMTJOIIEtD5UNzXJKY4w99Tpz64xXXymDpAeukC6RE8XOh/cfLjqDh/C48lkCIbtAUii+Jl8+tWXqAuhsU8EEGMIWrgmSErwdU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746268809; c=relaxed/simple; bh=TK4hEyPMkYbCZlehLpnWJgAjP62FEEwufy8Wx+ZMA44=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EDunohZagKZHePuc7/wv/HRUMBLaKZ75vrBvELYNvKUiqKwoxFamzxY2pT/IMWyw4YLUUchu0jfOB2pG96ur4OJXYCqBhJ5xg3TYdjx+NOPImBw3NEsdj3OstAGl9HSgGthkg1xWwWeMUyVro+C8an004yA1/m1DRLKl65FO/xQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=trvn.ru; spf=pass smtp.mailfrom=trvn.ru; dkim=pass (2048-bit key) header.d=trvn.ru header.i=@trvn.ru header.b=xeDnJEWG; arc=none smtp.client-ip=45.141.101.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=trvn.ru Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=trvn.ru Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=trvn.ru header.i=@trvn.ru header.b="xeDnJEWG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=trvn.ru; s=mail; t=1746268800; bh=TK4hEyPMkYbCZlehLpnWJgAjP62FEEwufy8Wx+ZMA44=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=xeDnJEWGRM7op+Y5umJxsiKvhaIFnWKJgLQtPatAH+Wy2U3UiapWPRx8bAh1qwesq 4ssacjUH8EwuGumkHhCgsqz6fFgpylXs8o23hcaO1KK1XmAbYEdlpcZkax4zKeRKBy l2oP8+mYjAwyITu16uGKJrdDqyM/Q6KxvCoYmvuM+txT8fl6CJz5ZxRvs+aEpgAPoe fmi4aINDCw57pdm76b4rOoVDllCFmfML5qQ1RzAp82LDibGgCAExFEYA5LfJcYB8I6 clUbmtPBni4ADWdPyTjy6jh6jI6g/3f5pMay+e9nIjnVL7FOhmjeTmzZjE2NJp8wBc Mq2z7/GpZJErw== Received: from authenticated-user (box.trvn.ru [45.141.101.25]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by box.trvn.ru (Postfix) with ESMTPSA id 4AAC4C971; Sat, 3 May 2025 15:39:59 +0500 (+05) From: Nikita Travkin Date: Sat, 03 May 2025 15:39:29 +0500 Subject: [PATCH v2 2/5] arm64: dts: qcom: sc8280xp: Add PCIe IOMMU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250503-sc-el2-overlays-v2-2-24e9b4572e15@trvn.ru> References: <20250503-sc-el2-overlays-v2-0-24e9b4572e15@trvn.ru> In-Reply-To: <20250503-sc-el2-overlays-v2-0-24e9b4572e15@trvn.ru> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marc Zyngier , Jens Glathe , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nikita Travkin X-Developer-Signature: v=1; a=openpgp-sha256; l=1403; i=nikita@trvn.ru; h=from:subject:message-id; bh=TK4hEyPMkYbCZlehLpnWJgAjP62FEEwufy8Wx+ZMA44=; b=owEBbQKS/ZANAwAIAUMc7O4oGb91AcsmYgBoFfJ70x4aJqDuOy0WTSriVZp3HsbqFjo2uPGA6 +y2KPYYsU2JAjMEAAEIAB0WIQTAhK9UUj+qg34uxUdDHOzuKBm/dQUCaBXyewAKCRBDHOzuKBm/ daS4D/4quQUYnXxcHbgL6FSMPfDq67U+rkeTqs+S5Gwga/Ad1FbMZXIJmXrCLbspEUR/Wu8yJ2e Z+A9IvCHh9B9KlLc0ooQEKpM3P5R6nlqkNHvhQnC5o4kqWLQSBaiV6RFGEfQh5640Je8JWrV4Ij lQ5bhm8UkBlYxcIQKTmxFeGGAQhv25Q3m0MDc4sdng2/whxll5xVlX98NbEl5mCG2A4rojc69h1 +1l1+6YBblWmcVgd8pBR8YJ/SIixhd2nuRrKjjdChWt62Fc7xB1jcE9OfkHhcqhosCzmixs7Ucl tnB/VACXQn66L8UmpwEtZHwP8AjdLQwUHvaAfVfkHikY2TNZ2cOruluht7mzvBg4PNJFXo3Xbjm X6ZgCR5DsSccor/V0dZqW2CYoF0nAKzdOgZaqVQ/I+TWTspshP+Ilg6koQbtn12fBMdbt+yhP2r mqJGecdNbBdOfFDeOuYa5LgboiAn9GL8av3rmvT2Ie+UFYhOGMsnOtdxvA6N4KgB1OlYz8hrHNo sYTCNL8WfosGDdU9rgVb4bebtkZwYQOu7vI2Db3ub17nRyi2A7+XcTQO9qqiJkVLE2BQJIXtFaO uRq/n9pw4c/BtA5O0/X/vMg1490IKgoc7GdUk1141dzWtg9KYol4G0LJ++AVW93cQFd3ggMyTWU G/j9R/pAI65TdSg== X-Developer-Key: i=nikita@trvn.ru; a=openpgp; fpr=C084AF54523FAA837E2EC547431CECEE2819BF75 sc8280xp has an SMMUv3 connected to PCIe which is normally controlled by QHEE and is thus transparent to the OS. However if we boot Linux in EL2, without QHEE, we need to manage this IOMMU ourselves. To make that easier, and since the hardware actually exists, just not "usually" managed by Linux, describe it in the dts as "reserved". Signed-off-by: Nikita Travkin --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 35ef31d4ecf26125407bb64dd2de6e777a3400a3..27d21e1a2d50c6fc12f324ab2b4dfa4b99791b81 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4927,6 +4927,20 @@ rx-pins { }; }; + pcie_smmu: iommu@14f80000 { + compatible = "arm,smmu-v3"; + reg = <0 0x14f80000 0 0x80000>; + #iommu-cells = <1>; + interrupts = , + , + ; + interrupt-names = "eventq", + "gerror", + "cmdq-sync"; + dma-coherent; + status = "reserved"; /* Controlled by QHEE. */ + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; From patchwork Sat May 3 10:39:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Travkin X-Patchwork-Id: 887021 Received: from box.trvn.ru (box.trvn.ru [45.141.101.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B339D1EEA5F; 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Sat, 3 May 2025 15:40:00 +0500 (+05) From: Nikita Travkin Date: Sat, 03 May 2025 15:39:30 +0500 Subject: [PATCH v2 3/5] arm64: dts: qcom: sc8280xp: Add EL2 overlay for WoA devices Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250503-sc-el2-overlays-v2-3-24e9b4572e15@trvn.ru> References: <20250503-sc-el2-overlays-v2-0-24e9b4572e15@trvn.ru> In-Reply-To: <20250503-sc-el2-overlays-v2-0-24e9b4572e15@trvn.ru> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marc Zyngier , Jens Glathe , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nikita Travkin X-Developer-Signature: v=1; a=openpgp-sha256; l=3816; i=nikita@trvn.ru; h=from:subject:message-id; bh=yZ5AUrLf7fwFTnXazjJiDVbDwXh8gK863PfsGEF+COE=; b=owEBbQKS/ZANAwAIAUMc7O4oGb91AcsmYgBoFfJ7W3JhVsSMdFH3UYKcvKN2kRJvh3XzL9RkZ WHrKS4fMnGJAjMEAAEIAB0WIQTAhK9UUj+qg34uxUdDHOzuKBm/dQUCaBXyewAKCRBDHOzuKBm/ dXoFEACwm+C1nTTALVRMuoVoDZOgQ3lsjOnA/jfN4TQjr9fcwjOx+2WHqSUe/YbYpKJClWjsuqA J2s7dqK6eUKoD0L7KziywERMIrhSYJcbAMvcXZZzCVvEktKXNqO71lYiz1iwFHnU/65jjmFsDf1 acncroD/kb6OZ8B77ICCEqH2e/3Sy+pOQAhUDP7psNWPw6UzBn1pmQIvZM7gIYVAMMJ50unl1Ia 1bdvUxm/GzLKFCUymL57fB9Mkuzy9SyMJIlU2ZBwZfgB98TdPVxnyrYVa6jGfdMFv29SHVZEu1w PB2sf4So472FuHnPlIoWVteVlPhxWdebL2oIbhsMQkufuEBeFPmYLPTdhxpyFA3w8/AHowE5iMw ePAxLhBaQCgyvnmLrD6QcvtH6fq9aqEOvsqHeAg0OzejkILGWaYxUhyJ0Wrr21+6Pel2zwWBJEl kqFg1R/kjJuECpiBO2qjx7IvdccGW1XECqL+k0ub5NGGZzzuMHMn2PgfE6me7SdIXUi2AhiDyhk jZk+ZjvM7zoEoqrbvpIcz4oXmH+mLOq8gGIAADYZflscY1Lto8viMxTEH5P/ilD/FuGbAPUKWJn i19Eyjd95n0Sr9gmLkSq/YkPsM7EVFlp0hXSRbEE5rOPn/C59qoLJNwe+aOulD597Jdc8aOEJ5c K7jN+/9Q1KZK5zQ== X-Developer-Key: i=nikita@trvn.ru; a=openpgp; fpr=C084AF54523FAA837E2EC547431CECEE2819BF75 WoA devices using sc8280xp use android firmware to boot, which notably includes QHEE hypervisor. This means that, so far, Linux-based OS could only boot in EL1 on those devices. However Windows can replace QHEE upon boot with it's own hypervisor, and with the use of tools such as "slbounce", it's possible to do the same for Linux-based OS, in which case some modifications to the DT are necessary to facilitate the absence of QHEE services. Add a EL2-specific DT overlay and apply it to sc8280xp WoA devices to create -el2.dtb for each of them alongside "normal" dtb. Signed-off-by: Nikita Travkin --- arch/arm64/boot/dts/qcom/Makefile | 15 ++++++---- arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso | 44 ++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 06da6f6791d69f56bafc3dad3e721c9ff2a1a68a..12d9ed1129b4e83146e561910aca9fc3718b0820 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -205,11 +205,16 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8180x-lenovo-flex-5g.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8180x-primus.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-huawei-gaokun3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-microsoft-arcata.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-microsoft-blackrock.dtb +sc8280xp-crd-el2-dtbs := sc8280xp-crd.dtb sc8280xp-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb sc8280xp-crd-el2.dtb +sc8280xp-huawei-gaokun3-el2-dtbs := sc8280xp-huawei-gaokun3.dtb sc8280xp-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-huawei-gaokun3.dtb sc8280xp-huawei-gaokun3-el2.dtb +sc8280xp-lenovo-thinkpad-x13s-el2-dtbs := sc8280xp-lenovo-thinkpad-x13s.dtb sc8280xp-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb sc8280xp-lenovo-thinkpad-x13s-el2.dtb +sc8280xp-microsoft-arcata-el2-dtbs := sc8280xp-microsoft-arcata.dtb sc8280xp-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-microsoft-arcata.dtb sc8280xp-microsoft-arcata-el2.dtb +sc8280xp-microsoft-blackrock-el2-dtbs := sc8280xp-microsoft-blackrock.dtb sc8280xp-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-microsoft-blackrock.dtb sc8280xp-microsoft-blackrock-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm450-lenovo-tbx605f.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm450-motorola-ali.dtb diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso b/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso new file mode 100644 index 0000000000000000000000000000000000000000..25d1fa4bc2055e67db0508aa09c8a8bd7fa01687 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * sc8280xp specific modifications required to boot in EL2. + */ + +/dts-v1/; +/plugin/; + +/* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */ +&gpu { + zap-shader { + status = "disabled"; + }; +}; + +/* + * When running under QHEE, this IOMMU is controlled by the firmware, + * however when we take ownership of it in EL2, we need to configure + * it properly to use PCIe. + */ +&pcie2a { + iommu-map = <0 &pcie_smmu 0x20000 0x10000>; +}; + +&pcie2b { + iommu-map = <0 &pcie_smmu 0x30000 0x10000>; +}; + +&pcie3a { + iommu-map = <0 &pcie_smmu 0x40000 0x10000>; +}; + +&pcie3b { + iommu-map = <0 &pcie_smmu 0x50000 0x10000>; +}; + +&pcie4 { + iommu-map = <0 &pcie_smmu 0x60000 0x10000>; +}; + +&pcie_smmu { + status = "okay"; +}; From patchwork Sat May 3 10:39:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Travkin X-Patchwork-Id: 887023 Received: from box.trvn.ru (box.trvn.ru [45.141.101.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63E8B1DDA00; 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Sat, 3 May 2025 15:40:02 +0500 (+05) From: Nikita Travkin Date: Sat, 03 May 2025 15:39:31 +0500 Subject: [PATCH v2 4/5] arm64: dts: qcom: x1e80100: Add PCIe IOMMU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250503-sc-el2-overlays-v2-4-24e9b4572e15@trvn.ru> References: <20250503-sc-el2-overlays-v2-0-24e9b4572e15@trvn.ru> In-Reply-To: <20250503-sc-el2-overlays-v2-0-24e9b4572e15@trvn.ru> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marc Zyngier , Jens Glathe , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nikita Travkin X-Developer-Signature: v=1; a=openpgp-sha256; l=1435; i=nikita@trvn.ru; h=from:subject:message-id; bh=VM78bnqXE6eBOsA+BcpvbWTxuAL5iTO9ndxW92ZfweM=; b=owEBbQKS/ZANAwAIAUMc7O4oGb91AcsmYgBoFfJ7aOsXspvdR4afafYLHfc7zVuVmThcjx+y+ YgWuneG8wmJAjMEAAEIAB0WIQTAhK9UUj+qg34uxUdDHOzuKBm/dQUCaBXyewAKCRBDHOzuKBm/ dRFpD/9A97XMAN+kp2VjUzOrl3pQ1Fb8f7wH57nYgMHqsnCcQvyaI7ZoPIjzSrQwXfvA8VrLPLz uLkSho69HjBlPPF0SPJ8e4TPaEQOWtlaq2tHPOWcHKRcE7CklL5ZcVmSS+eDlRTtr9blhkiScMZ vAop/Rfa3eOM2yq++dG0bbd+gRF2mNpQkbSNlJFXv1dW4xhsGogvpJHLDiw/8rnv1c4f4nzx4AX zBZE6Sk9H5QI/HZcFkcAa4klhAy6xZlHxYKTEWBXIMVcux8vGMuSjDU3bSUzJHJbVLLKlATXpS4 rWOlYgmOKzM96Nnhz8xbysoHRuXdYSnw6jbvOZSiQnS0lwRTYzprHcdcaoFcXNaKd+OfteMvL70 h8jDHu18DI9qIt5FbGBK19nnbuIvNPnLqkykQ65YPyzqfivH/d2fZuamLMg/cv0VelSu0+iGSy1 buTwtGa3RueP/ArQ3KPWudqwklNbu0voCO6gmcEq9HpKVQ6rR5VkYSdTzcck5FkgR7BM4e7AnHF nFIwxDkBe8JasUeeFTUZ+NxpJM0cha64OKrRCm0WyzeZNcnwxZLqmXTVTX1KS7rkeR42waPUD/U klMFyfJG/VcgpZs86KCaSWmtYpvPe2WkEVKycHW3XBrqsrXdo9KoleHOwcRKao9nSXhl+LIxFPp dPiDuVdbpy9FRJQ== X-Developer-Key: i=nikita@trvn.ru; a=openpgp; fpr=C084AF54523FAA837E2EC547431CECEE2819BF75 x1e80100 has an SMMUv3 connected to PCIe which is normally controlled by Gunyah and is thus transparent to the OS. However if we boot Linux in EL2, without Gunyah, we need to manage this IOMMU ourselves. To make that easier, and since the hardware actually exists, just not "usually" managed by Linux, describe it in the dts as "reserved". Signed-off-by: Nikita Travkin --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 46b79fce92c90d969e3de48bc88e27915d1592bb..7a3e75294be545a719f3543a8b874900f7c78f99 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -7940,6 +7940,20 @@ apps_smmu: iommu@15000000 { dma-coherent; }; + pcie_smmu: iommu@15400000 { + compatible = "arm,smmu-v3"; + reg = <0 0x15400000 0 0x80000>; + #iommu-cells = <1>; + interrupts = , + , + ; + interrupt-names = "eventq", + "gerror", + "cmdq-sync"; + dma-coherent; + status = "reserved"; /* Controlled by Gunyah. */ + }; + intc: interrupt-controller@17000000 { compatible = "arm,gic-v3"; reg = <0 0x17000000 0 0x10000>, /* GICD */