From patchwork Sat May 3 16:24:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 887016 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D73881F1508; Sat, 3 May 2025 16:25:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746289515; cv=none; b=TJs6j9/4mkAWeWqvqcWkVAPPRFXyiiuvSxEQ8kq0P2liFhuAD3H5nECh1aUxG7U2LxId5MfedBEMNpJNQfd/zHLo3Nau60jUlP9P3YFaw0C41OW4IajqHf8XifKK519O8Q0DtjeYhCmwFcPmL8NuoSM61zhbsTGDZVl9JImnEfI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746289515; c=relaxed/simple; bh=lGxx0xcmSC6aYPTUvYvkXGNcIwmdZpACrGVuxDGh9y0=; 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Sat, 3 May 2025 16:24:46 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 46dc7kb1ff-1; Sat, 03 May 2025 16:24:46 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 543GOgxU029746; Sat, 3 May 2025 16:24:46 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 543GOkhV029809; Sat, 03 May 2025 16:24:46 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id 7E30E5015A2; Sat, 3 May 2025 21:54:45 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, bvanassche@acm.org, andersson@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat , Dmitry Baryshkov Subject: [PATCH V4 03/11] phy: qcom-qmp-ufs: Refactor phy_power_on and phy_calibrate callbacks Date: Sat, 3 May 2025 21:54:32 +0530 Message-ID: <20250503162440.2954-4-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250503162440.2954-1-quic_nitirawa@quicinc.com> References: <20250503162440.2954-1-quic_nitirawa@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: nS6O4KPA0-a1AnoaV6Gp9lYF48utZNgp X-Proofpoint-GUID: nS6O4KPA0-a1AnoaV6Gp9lYF48utZNgp X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAzMDE1MCBTYWx0ZWRfX6hJ/SjC2k2C4 bpGIWSv47e14AOTWlYiXnbhXnwYSAY/jMhltFgIXYsOJlE+1HZ5rxV9JcwZyU9rLV2mZI2lrvD2 YpCC0jRLgz7QyMBHRSOqew5x4Xvqf2XReejqM+59cEKOwOei3OG9Xq8mcLLAdtYZvzStzh5d2cu p1VSxwgp88tai8yiuqTEuJb3Ln7uN8acXLCoYiSkMyRyEukZKrrDh5EmbN1nIaZYyPuUHkGBpcX hPfBI7yugDuVkhmp7OKp5jOLTTgasq9UTf13gQEo5dbIv8sYPg0Px8MZ2J6daqM+fhqxv58vKDe /QYYU+c++WexE4VE/rmUDugbi9Q2jpPyHUbnJ0B0tRpg/m+m3BrFcP6OaqwrDPK2/xMHSIYkHKc nKaro74aS2F62I9scPtvaZnEfe90ADO6Sgi8cqdMLb6LTdRkoACat/l0v4vMVO/Qij7iPjA+ X-Authority-Analysis: v=2.4 cv=AfqxH2XG c=1 sm=1 tr=0 ts=68164352 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=ZEhkBkkNTqPGxlI-GDwA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-03_07,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 phishscore=0 impostorscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505030150 Commit 052553af6a31 ("ufs/phy: qcom: Refactor to use phy_init call") puts enabling regulators & clks, calibrating UFS PHY, starting serdes and polling PCS ready status into phy_power_on. In Current code regulators enable, clks enable, calibrating UFS PHY, start_serdes and polling PCS_ready_status are part of phy_power_on. UFS PHY registers are retained after power collapse, meaning calibrating UFS PHY, start_serdes and polling PCS_ready_status can be done only when hba is powered_on, and not needed every time when phy_power_on is called during resume. Hence keep the code which enables PHY's regulators & clks in phy_power_on and move the rest steps into phy_calibrate function. Refactor the code to retain PHY regulators & clks in phy_power_on and move out rest of the code to new phy_calibrate function. Also move reset_control_assert to qmp_ufs_phy_calibrate to align with Hardware programming guide. Reviewed-by: Dmitry Baryshkov Co-developed-by: Can Guo Signed-off-by: Can Guo Signed-off-by: Nitin Rawat --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 26 ++++++------------------- 1 file changed, 6 insertions(+), 20 deletions(-) -- 2.48.1 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index bb836bc0f736..636dc3dc3ea8 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1796,7 +1796,7 @@ static int qmp_ufs_com_exit(struct qmp_ufs *qmp) return 0; } -static int qmp_ufs_init(struct phy *phy) +static int qmp_ufs_power_on(struct phy *phy) { struct qmp_ufs *qmp = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qmp->cfg; @@ -1824,10 +1824,6 @@ static int qmp_ufs_init(struct phy *phy) return ret; } } - - ret = reset_control_assert(qmp->ufs_reset); - if (ret) - return ret; } ret = qmp_ufs_com_init(qmp); @@ -1846,6 +1842,10 @@ static int qmp_ufs_phy_calibrate(struct phy *phy) unsigned int val; int ret; + ret = reset_control_assert(qmp->ufs_reset); + if (ret) + return ret; + qmp_ufs_init_registers(qmp, cfg); ret = reset_control_deassert(qmp->ufs_reset); @@ -1898,21 +1898,6 @@ static int qmp_ufs_exit(struct phy *phy) return 0; } -static int qmp_ufs_power_on(struct phy *phy) -{ - int ret; - - ret = qmp_ufs_init(phy); - if (ret) - return ret; - - ret = qmp_ufs_phy_calibrate(phy); - if (ret) - qmp_ufs_exit(phy); - - return ret; -} - static int qmp_ufs_disable(struct phy *phy) { int ret; @@ -1942,6 +1927,7 @@ static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode) static const struct phy_ops qcom_qmp_ufs_phy_ops = { .power_on = qmp_ufs_power_on, .power_off = qmp_ufs_disable, + .calibrate = qmp_ufs_phy_calibrate, .set_mode = qmp_ufs_set_mode, .owner = THIS_MODULE, }; From patchwork Sat May 3 16:24:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 887017 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1246A8F58; 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Additionally, the code within qmp_ufs_com_init() does not correspond well with its name. Therefore, to enhance the readability and eliminate unnecessary function call inline qmp_ufs_com_init() into qmp_ufs_power_on(). There is no change to the functionality. Reviewed-by: Dmitry Baryshkov Signed-off-by: Nitin Rawat --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 44 ++++++++++--------------- 1 file changed, 18 insertions(+), 26 deletions(-) -- 2.48.1 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 43d2d714f28b..94095393148c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1757,31 +1757,6 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); } -static int qmp_ufs_com_init(struct qmp_ufs *qmp) -{ - const struct qmp_phy_cfg *cfg = qmp->cfg; - void __iomem *pcs = qmp->pcs; - int ret; - - ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); - if (ret) { - dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); - return ret; - } - - ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); - if (ret) - goto err_disable_regulators; - - qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); 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Sat, 03 May 2025 16:24:55 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 543GOi4m029770; Sat, 3 May 2025 16:24:51 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 46dc7kb1g6-1; Sat, 03 May 2025 16:24:51 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 543GOpbm029873; Sat, 3 May 2025 16:24:51 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 543GOpQU029872; Sat, 03 May 2025 16:24:51 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id DC82A5015A2; Sat, 3 May 2025 21:54:50 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, bvanassche@acm.org, andersson@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat Subject: [PATCH V4 07/11] phy: qcom-qmp-ufs: Remove qmp_ufs_exit() and Inline qmp_ufs_com_exit() Date: Sat, 3 May 2025 21:54:36 +0530 Message-ID: <20250503162440.2954-8-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250503162440.2954-1-quic_nitirawa@quicinc.com> References: <20250503162440.2954-1-quic_nitirawa@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: UC1OCos2Ou00ejXFJLwIt_f-_a74fgPY X-Authority-Analysis: v=2.4 cv=cpWbk04i c=1 sm=1 tr=0 ts=68164357 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=ckjLh8WlKRlJn9_E0bwA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: UC1OCos2Ou00ejXFJLwIt_f-_a74fgPY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAzMDE1MCBTYWx0ZWRfX7vsxm0Mkyz0q ImUbIy6n0XxewtesPYy69V2ifZgYGhhi7PoH8BzP8DXskcaMKmgSlbNCqkTrr8wO4mLBw7ADFJb Ec3cylpbl8hC4szLn0jCaOXH+RTw/8h71jHC92Szvx1U3KRNcUGaJTye6pwR1wih8XzP/Y+VRYF mYQWi4Pa6QWQGcH1a5W3hN0jc3HxSpd1tKihfugJN5pwB0K30+2T2NNb1akh+DvkCThm5FxPNXq U7xLvsYUX6nCrO7Sngeur9q3QDPKreQVB1IoeRwjPploX5CIBfBSMPDk85eUJQUDuXuO4PoJ+Ij ojUeiwnzZqMn55odufBIUTfXgj4GA7a3Vs9kPazXdv9G3BAOWl81HbZHuo29XmtngUuUm1+r4ik 1TwJBgvj60MTYdnjpHKTh0uAWkKgkhKvnWRBB46+Hhbqkz6LbyDMtmsETnDsdzmJlkmFOw4q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-03_07,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 malwarescore=0 suspectscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=999 clxscore=1015 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505030150 qmp_ufs_exit() is a wrapper function. It only calls qmp_ufs_com_exit(). Remove it to simplify the ufs phy driver. Additonally partial Inline(dropping the reset assert) qmp_ufs_com_exit into qmp_ufs_power_off function to avoid unnecessary function call. Signed-off-by: Nitin Rawat --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 29 +++++-------------------- 1 file changed, 5 insertions(+), 24 deletions(-) -- 2.48.1 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index c501223fc5f9..2df61ec68dc7 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1757,20 +1757,6 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); } - -static int qmp_ufs_com_exit(struct qmp_ufs *qmp) -{ - const struct qmp_phy_cfg *cfg = qmp->cfg; - - reset_control_assert(qmp->ufs_reset); - - clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); - - regulator_bulk_disable(cfg->num_vregs, qmp->vregs); - - return 0; -} - static int qmp_ufs_power_on(struct phy *phy) { struct qmp_ufs *qmp = phy_get_drvdata(phy); @@ -1835,15 +1821,6 @@ static int qmp_ufs_phy_calibrate(struct phy *phy) return 0; } -static int qmp_ufs_exit(struct phy *phy) -{ - struct qmp_ufs *qmp = phy_get_drvdata(phy); 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Sat, 03 May 2025 16:24:56 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 543GOiY1029771; Sat, 3 May 2025 16:24:53 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 46dc7kb1gf-1; Sat, 03 May 2025 16:24:53 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 543GOlrk029826; Sat, 3 May 2025 16:24:53 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 543GOqm3029895; Sat, 03 May 2025 16:24:53 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id 421945015A2; Sat, 3 May 2025 21:54:52 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, bvanassche@acm.org, andersson@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat Subject: [PATCH V4 08/11] phy: qcom-qmp-ufs: refactor qmp_ufs_power_off Date: Sat, 3 May 2025 21:54:37 +0530 Message-ID: <20250503162440.2954-9-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250503162440.2954-1-quic_nitirawa@quicinc.com> References: <20250503162440.2954-1-quic_nitirawa@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAzMDE1MCBTYWx0ZWRfX/1ubJ3XfeLvs njX7aJZMsemI4exBnjJoZRp8stNg395wKyMVu3zCjDwDiWNIV5gKjfss7tDumgjr+wjOgc/UTYu jAxWECjKyFOZ+QWFALwKrkF7r4UzF6eaIkyQCpJNaD/vbuO3ZjaRz4+W3o+H/GmxvIcBPR3N1eB vQ6ez/eT9B7R2lFM9UFPqTBVCsuKWlz7uU+MDrtWXrBHHppGGyRyY16yem/QXHSIcSIJ2p3eiLR p5yeFpCuV/4uDUEIyXtGkEOfuPSKQuB8qorSv820J5M7ViTWanAbdwZB+H6StG4jLSwFhylxSJC CJqz70WE6Tb4CEOcsuE32nLLSrJBJzYuiV/XH0PdRNqUHR4qXyY66AvzfD+MC4Y7fdD9aNsApgZ mfTysJYCEjuhu1O/5SYMDiu7CPsyfKzYFTY2N/900wCPbKNFymEXa7re2AZW7V+q8jLtpuQC X-Proofpoint-ORIG-GUID: xPAD8_xlE_Al3unBT2IO6qe2OxetIM6B X-Authority-Analysis: v=2.4 cv=Qope3Uyd c=1 sm=1 tr=0 ts=68164358 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=0NjA6WJkZe3NLfXfqlsA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: xPAD8_xlE_Al3unBT2IO6qe2OxetIM6B X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-03_07,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 adultscore=0 clxscore=1015 malwarescore=0 bulkscore=0 suspectscore=0 impostorscore=0 phishscore=0 mlxlogscore=999 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505030150 In qmp_ufs_power_off, the PHY is already powered down by asserting QPHY_PCS_POWER_DOWN_CONTROL. Therefore, additional phy_reset and stopping SerDes are unnecessary. Also this approach does not align with the phy HW programming guide. Thus, refactor qmp_ufs_power_off to remove the phy_reset and stop SerDes calls to simplify the code and ensure alignment with the PHY HW programming guide. Signed-off-by: Nitin Rawat --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 7 ------- 1 file changed, 7 deletions(-) -- 2.48.1 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 2df61ec68dc7..1cbc255c7c74 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1826,13 +1826,6 @@ static int qmp_ufs_power_off(struct phy *phy) struct qmp_ufs *qmp = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qmp->cfg; - /* PHY reset */ - if (!cfg->no_pcs_sw_reset) - qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); - - /* stop SerDes */ - qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START); - /* Put PHY into POWER DOWN state: active low */ qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); From patchwork Sat May 3 16:24:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 887013 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A2061F1508; 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Sat, 03 May 2025 16:24:59 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 543GOjrm029804; Sat, 3 May 2025 16:24:56 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 46dc7kb1gt-1; Sat, 03 May 2025 16:24:56 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 543GOtDN029948; Sat, 3 May 2025 16:24:55 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 543GOt95029947; Sat, 03 May 2025 16:24:55 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id 129265015A2; Sat, 3 May 2025 21:54:55 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, bvanassche@acm.org, andersson@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat Subject: [PATCH V4 10/11] scsi: ufs: qcom : Introduce phy_power_on/off wrapper function Date: Sat, 3 May 2025 21:54:39 +0530 Message-ID: <20250503162440.2954-11-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250503162440.2954-1-quic_nitirawa@quicinc.com> References: <20250503162440.2954-1-quic_nitirawa@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: XESIZspFT_M1wiU7xEmhe8Xqd60VLH6H X-Authority-Analysis: v=2.4 cv=O7Y5vA9W c=1 sm=1 tr=0 ts=6816435b cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=fCbX77z8Gh-i-5kHVyEA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: XESIZspFT_M1wiU7xEmhe8Xqd60VLH6H X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAzMDE1MCBTYWx0ZWRfXxEkBtkd/FEWd 9Z2gi1P5g1CUO/s4o8rUEyA4pQbTHMDwFO9jEj025yqYnNav8hfks0FQ1yjjTLTkm5b0udE5BVa aFhh4l1XbHM7l6A8FMgiV7h1e7VNFO5AqzjcJJPhQRzc/2TKrcXZByAnDQ5E///5wtPKjH76PfJ M0kewx6tS+J7SRK1IjHZfLCkHj3RDD1uW/ilTshS6X0MMJqJKrp1n8wORFNGckWG2VYUyTUCZN8 Y6weFkNXaid2jbnHbY6gTsLw+yjth2q34mdi1gUHTkEbcuQrT16wSYjBdoeMxRKwVXm78Baf0GV 1LOh/hMTEXB9y2oeOmA4pYye3+BYnkMXyLKvdqlqExQ3cEpHVvziTs2DPn84lrBgF4TE/y7zTpk 5+LHUjTQ2vMGYeJcAbTVNDG5+cD3c357kRXXQPaHTb0niw5ZdgkBJji89JVZQd34ifxBPlDD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-03_07,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 bulkscore=0 impostorscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505030150 Introduce ufs_qcom_phy_power_on and ufs_qcom_phy_power_off wrapper functions with mutex protection to ensure safe usage of is_phy_pwr_on and prevent possible race conditions. Co-developed-by: Can Guo Signed-off-by: Can Guo Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 44 +++++++++++++++++++++++++++++++------ drivers/ufs/host/ufs-qcom.h | 4 ++++ 2 files changed, 41 insertions(+), 7 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index ff35cd15c72f..a7e9e06847f8 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -421,6 +421,38 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) return UFS_HS_G3; } +static int ufs_qcom_phy_power_on(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct phy *phy = host->generic_phy; + int ret = 0; + + guard(mutex)(&host->phy_mutex); + if (!host->is_phy_pwr_on) { + ret = phy_power_on(phy); + if (!ret) + host->is_phy_pwr_on = true; + } + + return ret; +} + +static int ufs_qcom_phy_power_off(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct phy *phy = host->generic_phy; + int ret = 0; + + guard(mutex)(&host->phy_mutex); + if (host->is_phy_pwr_on) { + ret = phy_power_off(phy); + if (!ret) + host->is_phy_pwr_on = false; + } + + return ret; +} + static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); @@ -449,7 +481,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) return ret; if (phy->power_count) { - phy_power_off(phy); + ufs_qcom_phy_power_off(hba); phy_exit(phy); } @@ -466,7 +498,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) goto out_disable_phy; /* power on phy - start serdes and phy's power and clocks */ - ret = phy_power_on(phy); + ret = ufs_qcom_phy_power_on(hba); if (ret) { dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", __func__, ret); @@ -1018,7 +1050,6 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, enum ufs_notify_change_status status) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - struct phy *phy = host->generic_phy; int err; /* @@ -1038,7 +1069,7 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, /* disable device ref_clk */ ufs_qcom_dev_ref_clk_ctrl(host, false); } - err = phy_power_off(phy); + err = ufs_qcom_phy_power_off(hba); if (err) { dev_err(hba->dev, "%s: phy power off failed, ret=%d\n", __func__, err); @@ -1048,7 +1079,7 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, break; case POST_CHANGE: if (on) { - err = phy_power_on(phy); + err = ufs_qcom_phy_power_on(hba); if (err) { dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", __func__, err); @@ -1236,10 +1267,9 @@ static int ufs_qcom_init(struct ufs_hba *hba) static void ufs_qcom_exit(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - struct phy *phy = host->generic_phy; ufs_qcom_disable_lane_clks(host); - phy_power_off(phy); + ufs_qcom_phy_power_off(hba); phy_exit(host->generic_phy); } diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index d0e6ec9128e7..3db29fbcd40b 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -252,6 +252,10 @@ struct ufs_qcom_host { u32 phy_gear; bool esi_enabled; + /* flag to check if phy is powered on */ + bool is_phy_pwr_on; + /* Protect the usage of is_phy_pwr_on against racing */ + struct mutex phy_mutex; }; struct ufs_qcom_drvdata { From patchwork Sat May 3 16:24:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 887012 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6331268683; Sat, 3 May 2025 16:25:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746289521; cv=none; b=um1oUPhAIkY1gpXoqBDQZ4sPTF3+O9do2Oiu5jjGCi1aCt6GrhF1G5PJbLtgkEgaAGSRSf8iWjPhbJztWt1ANdmxUONnIICVl4jtWGwhRvlyQKEnF1QFz9e/wJEDk41jgKosc85EtcqODuqG5bg/CfskyP10NCFjtSb/I2+urH8= ARC-Message-Signature: i=1; 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Sat, 3 May 2025 16:24:57 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 46dc7kb1h4-1; Sat, 03 May 2025 16:24:57 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 543GOhc5029761; Sat, 3 May 2025 16:24:57 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 543GOudt029961; Sat, 03 May 2025 16:24:57 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id 668155015A2; Sat, 3 May 2025 21:54:56 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, bvanassche@acm.org, andersson@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat Subject: [PATCH V4 11/11] scsi: ufs: qcom: Prevent calling phy_exit before phy_init Date: Sat, 3 May 2025 21:54:40 +0530 Message-ID: <20250503162440.2954-12-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250503162440.2954-1-quic_nitirawa@quicinc.com> References: <20250503162440.2954-1-quic_nitirawa@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: uqxELhWuceALrZBbTPSLVvCWouGReras X-Proofpoint-GUID: uqxELhWuceALrZBbTPSLVvCWouGReras X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAzMDE1MCBTYWx0ZWRfX8KdvWmMh7BZh gns7ZV1gvPfRdw40jgJKDcgDFRFrgeav/240nlSKOPJHhtT+rhlVBCOdlEOezs5XvbpThFv5K5n rodBf20q7x4sEg2NIalQ+4R4bH9ZXPZG1mziXBltbA7kTuGBWAnfWEFg9+Pxl+hPCcmgBRRVwix XiMWAfdYVaVwix3qorf8NODPwzR9L+gNg7zBKxwv0+CBddU5lY+P+7tk5D+rFjJHSxfBHrFyyeU vZR9qRIhgBI6jnY8BEMOWVeVklsJjBSx1UvKZFQASFiqizRyLV+b1p+Uyt3u/ws4kOkmC9mWq8+ Zc8ubLGAaJDjeXbd7W4n53QMR4ZOs0ls6zWGQxKSNc7qLeXczVXoMulp7fy3XMIgHPQx1cWqb7G 2WUkWK0MaobBO8S2qRb3sJRjgccgYUjz6vhx6Yvd97uWGvZt8iqifzoEBBnHG52j/ExdwrD5 X-Authority-Analysis: v=2.4 cv=AfqxH2XG c=1 sm=1 tr=0 ts=6816435c cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=6qkdr0EpClcQ5iOZAa0A:9 a=zZCYzV9kfG8A:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-03_07,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 phishscore=0 impostorscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505030150 Prevent calling phy_exit before phy_init to avoid abnormal power count and the following warning during boot up. [5.146763] phy phy-1d80000.phy.0: phy_power_on was called before phy_init Fixes: 7bac65687510 ("scsi: ufs: qcom: Power off the PHY if it was already powered on in ufs_qcom_power_up_sequence()") Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 1 - 1 file changed, 1 deletion(-) -- 2.48.1 diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index a7e9e06847f8..db51e1e7d836 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -482,7 +482,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) if (phy->power_count) { ufs_qcom_phy_power_off(hba); - phy_exit(phy); } /* phy initialization - calibrate the phy */