From patchwork Fri May 2 10:15:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 886683 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76A2021146A; Fri, 2 May 2025 10:15:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746180949; cv=none; b=FOGtyJk+OmKJ88A/EHXYqeTlXg+ahsTi+6/AhuYJ9j64VO/882q6t9fPcyHJrWYr11K/iuxMpGmyGC3B/aicV99d1Hc0IWSqBZ9k3XP1LRf/4w6+5znzdlMoGhXTSltt/9aKo08HQqxbjRK36zhZo20cGmax1/6Nwiy5e7pSsJE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746180949; c=relaxed/simple; bh=OEMRWSk4kiWPE3EhCFbIe0N0cuQqpnI5N1PC98kusOo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VBSn+VwKeDiZrGOu9y4Zi0fOHomHd60lzKm/SKoelpL2nqB3/ihR5Ia+LpdRXEsRouIXuHbCme2v4DSjcscGnqmL4jl2Fr/9/06NtroVJFnaLCCDgKiNOe1i/lcugCyFpFFLtZm1f86wuqcEzVGIuB2b/Kz7rGEx2jWsxJx2b1M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NhQSXXwg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NhQSXXwg" Received: by smtp.kernel.org (Postfix) with ESMTPS id ED60EC4CEED; Fri, 2 May 2025 10:15:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746180949; bh=OEMRWSk4kiWPE3EhCFbIe0N0cuQqpnI5N1PC98kusOo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=NhQSXXwgWP7TgnjKs0pD9ZOB4UyvSBCVdH0iSEE+rs4bXGzJ2VBuhiq6XSvxdX5Rx 7LhZgVTuk6HiqlO0H25TwVYd6PP1kLXufmL+Xwk1bYdXmAnOnMvcn3VR/bLHhVu/eE V11iJima33/7/ldCpEJqi79kuV2L6AzuOXXqxzVNFVi7uqG+BmZeTSlYsNVU6FgOz3 52puUzbiEhdBjAhk+2UK8uyvkNu47fn9sWTb+KOYNyNzbGzIadLmYePEYXSfUQaxuf dkV0pl+N5gkh3GOhnxEwhSe4ao3okJNiooa+c8Xr5IOm0+IvWyJvqMHGv5SxeNFSWz EYJrf8xhhh9DA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD246C3ABA3; Fri, 2 May 2025 10:15:48 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 02 May 2025 14:15:43 +0400 Subject: [PATCH 1/6] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250502-ipq5018-cmn-pll-v1-1-27902c1c4071@outlook.com> References: <20250502-ipq5018-cmn-pll-v1-0-27902c1c4071@outlook.com> In-Reply-To: <20250502-ipq5018-cmn-pll-v1-0-27902c1c4071@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746180945; l=2537; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=xMsnswH7lfsZOMdAFG5L88fjf8jqYYNAJSbGO9nECgc=; b=7+PZxKnRPFSXkwIqCDngsDZjv0Ccl/GljGOBpZt45o/525VNJJBP5j1WbKqTcVlOYbdtF4XIy cg4neOqVkaPABNsGuww3237zj0QlAtE2I7kTYca9XgcEr+QBd+kYvlK X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and ethernet (50Mhz) clocks. Unlike IPQ9574, the CMN PLL to the ethernet block needs to be enabled first in IPQ5018. Hence, add optional phandle to TCSR register space and offset to do so. Signed-off-by: George Moussalem --- .../devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml | 11 ++++++++--- include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h | 16 ++++++++++++++++ 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml index cb6e09f4247f4b25105b25f4ae746c0b3ef47616..25006d65d30e20ef8e1f43537bcf3dca65bae73d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml @@ -24,12 +24,10 @@ description: properties: compatible: enum: + - qcom,ipq5018-cmn-pll - qcom,ipq5424-cmn-pll - qcom,ipq9574-cmn-pll - reg: - maxItems: 1 - clocks: items: - description: The reference clock. The supported clock rates include @@ -50,6 +48,13 @@ properties: "#clock-cells": const: 1 + qcom,cmn-pll-eth-enable: + description: Register in TCSR to enable CMN PLL to ethernet + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - description: phandle of TCSR syscon + - description: offset of TCSR register to enable CMN PLL to ethernet + required: - compatible - reg diff --git a/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h new file mode 100644 index 0000000000000000000000000000000000000000..586d1c9b33b374331bef413f543c526212c18494 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H +#define _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H + +/* CMN PLL core clock. */ +#define IPQ5018_CMN_PLL_CLK 0 + +/* The output clocks from CMN PLL of IPQ5018. */ +#define IPQ5018_XO_24MHZ_CLK 1 +#define IPQ5018_SLEEP_32KHZ_CLK 2 +#define IPQ5018_ETH_50MHZ_CLK 3 +#endif From patchwork Fri May 2 10:15:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 886682 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76BE4231849; Fri, 2 May 2025 10:15:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746180949; cv=none; b=qYRf2CzyB5uuU0Qqgx1+V0VpZsmGIYt5InWEznYPGPDEpLwZUotaEhlHwVC5pb5l4zdR+aUj7obm/cA6eos6zbH1+AG2miLa40BZr7hdDpwTusRaTlUTnKyOnUrgCsGyqus9yrVYFunVrpbUvWaqUquiIazvg89LZn6pVgcv7Ak= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746180949; c=relaxed/simple; bh=+i6U5gzgaJQuykdrlR9696g2Ug/pI295l1VkB4dqmU8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PsS5CJXFXb/fQzMl59qzeYcN0FaO6vDiEM6QEUkR6hkK3euFHv2m9hwoogyFo+momfC8VSuqqd8ekWuizxjsjGU4U4goXJaVo2lB1l/wD59906SzVNBsIVv6pZBrmqCS8+kt/Jnw0kdz4AzzhcXgrp+4xrU4s8dZH5/Ahy3TNu8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rSJpHzBq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rSJpHzBq" Received: by smtp.kernel.org (Postfix) with ESMTPS id 13006C4CEEF; Fri, 2 May 2025 10:15:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746180949; bh=+i6U5gzgaJQuykdrlR9696g2Ug/pI295l1VkB4dqmU8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=rSJpHzBqVAGBEJkKavDLNgcVgbYPj4P/aY82vHe+99Rx+X8lY24bRVY5uvkORXUfd zpwS4+5AbBhBFQKkIE0ZyaqDPJ/ieqqIMhp62e24z2fwDXXFzymsQGQ6T6vJjnbOU/ TQXlaaEF9AsqcVAaNY1o3UGVhMEQX7JbN3HWGpCZPP7ig9zzWZxjGdFR+A4eRlCVtt WQAcN04F6S28V2a3MYUS7Yp4HgVTTkdT4GVSplWVk62QP78DbkxXCvqEB0IazcXMqx eJGETVQU0bIyL3VPBix4BNKk40N3VmJKvDF+O1ka/j+W8KBRMSjLPw39XN4LiBP0qW wAmeJYImcNXjA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 031ECC3ABAC; Fri, 2 May 2025 10:15:49 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 02 May 2025 14:15:45 +0400 Subject: [PATCH 3/6] clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250502-ipq5018-cmn-pll-v1-3-27902c1c4071@outlook.com> References: <20250502-ipq5018-cmn-pll-v1-0-27902c1c4071@outlook.com> In-Reply-To: <20250502-ipq5018-cmn-pll-v1-0-27902c1c4071@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746180945; l=5376; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=PEmE2g2mhIp+5KgVZEFjuRFR4mN6d1vKPr3n1ioKGP8=; b=xk+zmNRHrItlJ/CpcHVMMaOP1kSYV0bYRvjVOWbUkf+M1rcau8nVETBYhlAkWKdsURB2xLwH0 GTEWGj0s7myDrxdUB5zfDMoVjV1hG7b6KMfgWqs67TkWWb8FpAoKKDZ X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The CMN PLL in IPQ5018 SoC supplies fixed clocks to XO, sleep, and the ethernet block. The CMN PLL to the ethernet block must be enabled first by setting a specific register in the TCSR area set in the device tree. Signed-off-by: George Moussalem --- drivers/clk/qcom/ipq-cmn-pll.c | 72 +++++++++++++++++++++++++++++++++++------- 1 file changed, 61 insertions(+), 11 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index b34d6faf67b8dd74402fabdb8dfe5ea52edd52f4..8e1faea1f980fd53f62b340aa31b6cf1b14f7923 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include #include @@ -50,6 +51,7 @@ #include #include +#include #include #define CMN_PLL_REFCLK_SRC_SELECTION 0x28 @@ -72,6 +74,9 @@ #define CMN_PLL_DIVIDER_CTRL 0x794 #define CMN_PLL_DIVIDER_CTRL_FACTOR GENMASK(9, 0) +#define TCSR_CMN_PLL_ETH 0x4 +#define TCSR_CMN_PLL_ETH_ENABLE BIT(0) + /** * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information * @id: Clock specifier to be supplied @@ -92,6 +97,7 @@ struct cmn_pll_fixed_output_clk { struct clk_cmn_pll { struct regmap *regmap; struct clk_hw hw; + struct regmap *tcsr; }; #define CLK_PLL_OUTPUT(_id, _name, _rate) { \ @@ -110,16 +116,10 @@ static const struct regmap_config ipq_cmn_pll_regmap_config = { .fast_io = true, }; -static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { - CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), - CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), - CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), - CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), - CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), - CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), - CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), - CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), - CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), +static const struct cmn_pll_fixed_output_clk ipq5018_output_clks[] = { + CLK_PLL_OUTPUT(IPQ5018_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), + CLK_PLL_OUTPUT(IPQ5018_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), + CLK_PLL_OUTPUT(IPQ5018_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL), { /* Sentinel */ } }; @@ -136,6 +136,19 @@ static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = { { /* Sentinel */ } }; +static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { + CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), + CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), + CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), + CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), + CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), + CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), + { /* Sentinel */ } +}; + /* * CMN PLL has the single parent clock, which supports the several * possible parent clock rates, each parent clock rate is reflected @@ -380,11 +393,47 @@ static int ipq_cmn_pll_register_clks(struct platform_device *pdev) return ret; } +static inline int ipq_cmn_pll_eth_enable(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + unsigned int cmn_pll_offset; + struct regmap *tcsr; + int ret; + + tcsr = syscon_regmap_lookup_by_phandle_args(dev->of_node, "qcom,cmn-pll-eth-enable", + 1, &cmn_pll_offset); + if (IS_ERR(tcsr)) { + ret = PTR_ERR(tcsr); + /* + * continue if -ENODEV is returned as not all IPQ SoCs + * need to enable CMN PLL. If it's another error, return it. + */ + if (ret == -ENODEV) + tcsr = NULL; + else + return ret; + } + + if (tcsr) { + ret = regmap_update_bits(tcsr, cmn_pll_offset + TCSR_CMN_PLL_ETH, + TCSR_CMN_PLL_ETH_ENABLE, TCSR_CMN_PLL_ETH_ENABLE); + if (ret) + return ret; + } + + return 0; +} + static int ipq_cmn_pll_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; int ret; + ret = ipq_cmn_pll_eth_enable(pdev); + if (ret) + return dev_err_probe(dev, ret, + "Fail to enable CMN PLL to ethernet"); + ret = devm_pm_runtime_enable(dev); if (ret) return ret; @@ -439,8 +488,9 @@ static const struct dev_pm_ops ipq_cmn_pll_pm_ops = { }; static const struct of_device_id ipq_cmn_pll_clk_ids[] = { - { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks }, + { .compatible = "qcom,ipq5018-cmn-pll", .data = &ipq5018_output_clks }, { .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks }, + { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks }, { } }; MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids); From patchwork Fri May 2 10:15:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 886684 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76A8822D4F9; Fri, 2 May 2025 10:15:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746180949; cv=none; b=krCrfFApReanUoz4ESVH+Oy2r5TNxJmc4kiAIaif0UP16lNj8cPwDG6ZztnuPOfKSZi+aHSrW63LJTCv25ySuKDz/QxN/UZhVb1hLpMHYOuf9s0pM1rwdK4Dmf7wa9LvfUqJTdSWJmsTSL1luzouPbxSu7rEihXGNjhlv/tuJmE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746180949; c=relaxed/simple; bh=9c73iXDXvgnARot8nAst3Y4sWhj8Zc0sgUgQkOUXnus=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZRh9oUWFJwikTAL7yeEgT7evaopXo3wLAF/J61Wu0ce21KInM0IYtY5oOPs5bWs4Z5GcuDbl8yp6cITNLv09nwWGdqI8ilLt4NWW4tYJNyVi3bZJIMhdJT0zLkmQNoIqPx9Foyl0J7f2CLeAGpyRvh3KWt9gmUlTld3tXB5Lk1Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=s8lkdEeE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="s8lkdEeE" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1C6C4C4CEF7; Fri, 2 May 2025 10:15:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746180949; bh=9c73iXDXvgnARot8nAst3Y4sWhj8Zc0sgUgQkOUXnus=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=s8lkdEeEu/5hTjphAH51GVQNYiK8MaA6cmSt5/fj9vxPUCnS6uA6NCoDV12O/9XmT CqQwIw+Xp6p0zWqYm2FnYh9uUmXEa+N6m1uu5TQrHFsiRwPKBRtxL6aQJiMO8Bl1Nv gRuCAhHpqrJu2mtr615M038YQ9oYqwEx5XD5qISpsVvVmOmt0qvqka8XWdjHMITbOx 8nHnb6Gn4BTIlwKX4kCqWAhEdh8Ak2uztqmWx0YFmUurIb4hgvpnfbOOYPAI2nhpV0 g5st+PDB9mRgq+uJLye+UuVaxZ/0+78YC8lQVmBtlNmHC0YGJ8ojfudN2U3tIAHw8Q +vxFP3TReEx0Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F8F3C3ABB6; Fri, 2 May 2025 10:15:49 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 02 May 2025 14:15:46 +0400 Subject: [PATCH 4/6] dt-bindings: mfd: qcom,tcsr: Add compatible for IPQ5018 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250502-ipq5018-cmn-pll-v1-4-27902c1c4071@outlook.com> References: <20250502-ipq5018-cmn-pll-v1-0-27902c1c4071@outlook.com> In-Reply-To: <20250502-ipq5018-cmn-pll-v1-0-27902c1c4071@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746180945; l=819; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=rWOkA/E/Z9CidEDzLfL6fySdOSwBg0HFYVj2bD8wwdw=; b=lgtEHtO41HG6bV8PodAOUvv4/8xckPbBymX1w3Wj6XQeY35/cFoP15GLYqTsSna6obsLzbh9X 3fygYMoK3lWC99OHGLNYSUI2JedeVmSHU3BJzbdJ7L7JO4JMNLe3lAI X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Document the qcom,tcsr-ipq5018 compatible. Signed-off-by: George Moussalem --- Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml index 7e7225aadae3285f59ec303294cf1515772a629b..14ae3f00ef7e00e607bba93f49f03bb244253b0e 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -41,6 +41,7 @@ properties: - qcom,sm8450-tcsr - qcom,tcsr-apq8064 - qcom,tcsr-apq8084 + - qcom,tcsr-ipq5018 - qcom,tcsr-ipq5332 - qcom,tcsr-ipq5424 - qcom,tcsr-ipq6018 From patchwork Fri May 2 10:15:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 886681 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA6F823C4F5; Fri, 2 May 2025 10:15:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746180949; cv=none; b=JTebajrlKAOEilaWqTRPazg5w1wIf1srBqNPclEd/cl65vRy/I5hsH6DYS5dtIwZNOPBPYULLps8bc5ysCUqStbJ0aHT1DukAJk7a075QttCcO/dVTcIn3+jpyB8s4X774+3PhefcdqJsvpEeZi/Q4+gDvqQ2/PSoWzlf1o6u70= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746180949; c=relaxed/simple; bh=J5bRSUSSinWxsTQKxhKwV/BUAMuxf53BzmqIIG9qPGo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cOeQPvyk7hiPTxeu5D0c1O0ev+EmIii9rItU0AO9PtIlR6Z5M6QCHbBhyg+oBB1kc255VgWDnmA4eLgpDvihXD7qwCAETq7WTTJ1utgfnoWO2l6vLqYkk4d8iFP0UVxKVX/1NRMR9E/gWyGdfHPd1SXkRESLKaFBevyo0YIBvzU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Hpwl9D7p; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Hpwl9D7p" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2330FC4CEF9; Fri, 2 May 2025 10:15:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746180949; bh=J5bRSUSSinWxsTQKxhKwV/BUAMuxf53BzmqIIG9qPGo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Hpwl9D7pwiiaxefC0OhsVLYXFwgE0foS5aZMC/VT4LYEdE9nsxQtV/TBoK3lxvg15 AUOPswuUtW0zQFzAwqu4l/hn88kuhLrTufotC1NoQRm9kxyN+22fE7A8hR+CDuTi73 8Go9RKzqOz6IoKVzAJ6EIrVl56/FmS49LnqnUrc/qXcwZa8pNoJCJpSymwM0xIb84W di8UM+h1E7EsmK4nWcQhW0fjUw/l9an9JNqQ5GpLik0j1SblYKqxC+mK3Pj1P5wFCQ /KV/UDqT8LyE1/VSpzKSaRQB8xIGDETUF6kOgxmkgODefhlQ7uWJcQV8REtGAbtMvp J5mAXX9v5lqEQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B829C3ABA3; Fri, 2 May 2025 10:15:49 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 02 May 2025 14:15:47 +0400 Subject: [PATCH 5/6] arm64: dts: ipq5018: Add CMN PLL node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250502-ipq5018-cmn-pll-v1-5-27902c1c4071@outlook.com> References: <20250502-ipq5018-cmn-pll-v1-0-27902c1c4071@outlook.com> In-Reply-To: <20250502-ipq5018-cmn-pll-v1-0-27902c1c4071@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746180945; l=2861; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=GI/nnrynnAP1TcHu1Q2Qi498C3gSFhYoszdpVbk+97o=; b=iLRTIzMIHJDOiyCzc1cvE6X2r8oDkWhwj6GlOV84ZwFtIuxHXw264Wc9wZcdCkttKUOCJIZsG Hj72J9IBs0VDDr72Z8igaQcE4EIvg3pbTYjIMSiBeDfLGUY1mm04YDW X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Add CMN PLL node for enabling output clocks to the networking hardware blocks on IPQ5018 devices. The reference clock of CMN PLL is routed from XO to the CMN PLL through the internal WiFi block. .XO (96 MHZ)-->WiFi (multiplier/divider)--> 48 MHZ to CMN PLL. Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 39 +++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 8914f2ef0bc47fda243b19174f77ce73fc10757d..78368600ba44825b38f737a6d7837a80dc32efb6 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -2,12 +2,13 @@ /* * IPQ5018 SoC device tree source * - * Copyright (c) 2023 The Linux Foundation. All rights reserved. + * Copyright (c) 2023-2025 The Linux Foundation. All rights reserved. */ #include -#include +#include #include +#include #include / { @@ -16,6 +17,14 @@ / { #size-cells = <2>; clocks { + ref_96mhz_clk: ref-96mhz-clk { + compatible = "fixed-factor-clock"; + clocks = <&xo_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -25,6 +34,12 @@ xo_board_clk: xo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; + + xo_clk: xo-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; }; cpus { @@ -147,6 +162,21 @@ usbphy0: phy@5b000 { status = "disabled"; }; + cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq5018-cmn-pll"; + reg = <0 0x0009b000 0 0x800>; + clocks = <&ref_96mhz_clk>, + <&gcc GCC_CMN_BLK_AHB_CLK>, + <&gcc GCC_CMN_BLK_SYS_CLK>; + clock-names = "ref", + "ahb", + "sys"; + #clock-cells = <1>; + assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>; + assigned-clock-rates-u64 = /bits/ 64 <9600000000>; + qcom,cmn-pll-eth-enable = <&tcsr 0x105c0>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5018-tlmm"; reg = <0x01000000 0x300000>; @@ -187,6 +217,11 @@ tcsr_mutex: hwlock@1905000 { #hwlock-cells = <1>; }; + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-ipq5018", "syscon"; + reg = <0x01937000 0x21000>; + }; + sdhc_1: mmc@7804000 { compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; reg = <0x7804000 0x1000>;