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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.48.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:48:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 01/16] accel/tcg: Generalize fake_user_interrupt test Date: Wed, 30 Apr 2025 09:48:39 -0700 Message-ID: <20250430164854.2233995-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Test for the hook being present instead of ifdef TARGET_I386. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 279df5fae7..8ff4a34509 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -732,10 +732,10 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) * If user mode only, we simulate a fake exception which will be * handled outside the cpu execution loop. */ -#if defined(TARGET_I386) const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; - tcg_ops->fake_user_interrupt(cpu); -#endif /* TARGET_I386 */ + if (tcg_ops->fake_user_interrupt) { + tcg_ops->fake_user_interrupt(cpu); + } *ret = cpu->exception_index; cpu->exception_index = -1; return true; From patchwork Wed Apr 30 16:48:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 886062 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:38f:210b:807b with SMTP id g4csp956820wrq; Wed, 30 Apr 2025 09:49:28 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXMqCZxoUjiRHDSEhRMCeuy/mgfLORpZKlkIjKDyXlq/BbeNs2y9Ca7YyOeLdpS/hRoYaoHmg==@linaro.org X-Google-Smtp-Source: AGHT+IEs9mfP1Cw+5RSmPRzoW7LkZ4qd4kFY9tl0X1M8rvvabxKRxIn7TMJd2BRhCx7IRtrUN1Iq X-Received: by 2002:a05:620a:414a:b0:7c5:9553:d4e2 with SMTP id af79cd13be357-7cacd064abamr21672385a.24.1746031768377; Wed, 30 Apr 2025 09:49:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1746031768; cv=none; d=google.com; s=arc-20240605; b=a5jnO4HmYUZTzP0MhFDfzdcQu1msH3+yqwifHJ6JEFVwrRYYmTDmax8ENUAeJI3TB9 AEXO5+91BWzq7XaNzwpg2b0gxvc2d7ji63vrwO+i2SNeRDWfcet6JcHlcMmGGaQDcmNy RO3lI2MyYMpLjrWkMDe0vk/xsDQC2q1neZ72jAo/wU++9B98AEEwtJufTntrZXxG5ECN 26JMsqCtJclnFxgeiOnSuXnpZJLn3tKTg4YM4nz3OBvt205sW7+KKE+R6We2OOJz8HqR rfKLPOdFA4cAZoluGzeHl4S/sR+s3zfBjfSbo+IvM45J/WFGEJL5j69ofcvsD850j7xT R4XQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=m8QQZQVqZoC308ckvLV+kB4d6m4SiPb0nD+im6xT08U=; fh=6c3iePwzSVcIevU/n11cXtkmPbvvYSh1prLosaYzn/o=; b=VK/07SdpvS27FJeDWT5L3JNu8cu/3yZMXY91NNmbUpPvAN6uTng5wtsKszoN60bGi2 mgzxPAKNNmk14QWgJloLSaugogxRTf9UDfsEscbnVxMWWXt3PlZOY0qXTjfvSNW8QtE5 M/9lGGV4FuhOYhuz2uHIVmdZxx4XA8mLZcY6Bf9/l7ddHMAdGvd8kjGacVmDnU/xV8Bq CBh0LsEr0KBayoOwYDkGpFfRJYm8Q825zytbPsk7fVBp/aCerZLVRG+7gKYJgtnG0KH/ 4+psrZL/KDxT5+DtGPNLgjH9aVBtHnGKQSqwI+wReyKSGu28Uej7XKNuU20wgyriuSRt rcWA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="L5u/+81Y"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.48.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:48:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 02/16] accel/tcg: Unconditionally use CPU_DUMP_CCOP in log_cpu_exec Date: Wed, 30 Apr 2025 09:48:40 -0700 Message-ID: <20250430164854.2233995-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This flag is only tested by target/i386, so including this makes no functional change. This is similar to other places like cpu-target.c which use CPU_DUMP_CCOP unconditionally. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8ff4a34509..ff979a2c57 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -285,14 +285,11 @@ static void log_cpu_exec(vaddr pc, CPUState *cpu, if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { FILE *logfile = qemu_log_trylock(); if (logfile) { - int flags = 0; + int flags = CPU_DUMP_CCOP; if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) { flags |= CPU_DUMP_FPU; } -#if defined(TARGET_I386) - flags |= CPU_DUMP_CCOP; -#endif if (qemu_loglevel_mask(CPU_LOG_TB_VPU)) { flags |= CPU_DUMP_VPU; } From patchwork Wed Apr 30 16:48:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 886063 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:38f:210b:807b with SMTP id g4csp957008wrq; Wed, 30 Apr 2025 09:49:54 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX5DlGxnai4GyOLgBtLchg/tnDsg98XS+05Azd160cnxai51xRnfdT3CcnkQG21pe//F5cOrQ==@linaro.org X-Google-Smtp-Source: AGHT+IGgfQqnWWWQY9pVpzp21EFBo8/eubKu3S/htQ/cEjo8vXF34WxNfJupsamQDrcVs08FiiI3 X-Received: by 2002:ad4:5d61:0:b0:6e4:4274:aaf8 with SMTP id 6a1803df08f44-6f4fe055990mr55668036d6.17.1746031793888; Wed, 30 Apr 2025 09:49:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1746031793; cv=none; d=google.com; s=arc-20240605; b=SAf6pQwog5C8tCP8EFJMkFHZNjF8O0DWbk8AuHVrjuOvn3l9Cwgly/3hVYFPYBrV5O 1c3q8vtNDJhNlAARbZjT5HSYPgyBlEaCDHPIBOpGfw2D3dZcMoQveux5XehyPZQHsOP1 YmYnG0wUuoBH/P8WhEKwfE17OY842aJtkKAqskKQM8DJ570l9zJeQglBXseej6jyhjQX lYqmn0yBwPGb7gIkzlJYbW354v1AzyzojYey9JIVCtes2SozUVEfCD6o3DsNiuIH/QEm lWmpm8zsXoGSwaJXudL3lDVAd8uFxmxRg0GuPMDm5Sfa/p/SSc10xVfQs/05aUa47ooj YAPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=JFC0lIwrLvv96xyWA8HMukwFYVh25GBIzBMcz0FbVPQ=; fh=6c3iePwzSVcIevU/n11cXtkmPbvvYSh1prLosaYzn/o=; b=ZvVEjvwr/20spahA9Uy/pxufHq4Qm8zVaBIr95TRKdMNAeo9PWsiqgxILubR3qwSjw dwMzxLyLQ+IH4+XqKipaVuYgzDQd6/n9ceD1ETqwXq4dUHWH9i29H2N5ANK7Y+Zn50/D d7bhqnU/4emDERy2lp9Y2IIshpA7ZowCW5IdEjw4applRHdct0kbSX1YGJxUgcvg7IJf tjS82pawbCw6HPHuLAdZrKfhPnu0a0oDY4ARBEfsVAbk9IF89ypxadANKqEYzX9ar4V1 O+w4q4bX0aWwliVw+2QQXeFT028kk+1PJxP7ZRSnX9P0S7gv1di0nMSYxP7+MXb8fb+4 T8Yw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qPBg558V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.48.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:48:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 03/16] accel/tcg: Introduce TCGCPUOps.cpu_exec_reset Date: Wed, 30 Apr 2025 09:48:41 -0700 Message-ID: <20250430164854.2233995-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Initialize all instances with cpu_reset(), so that there is no functional change. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 2 ++ accel/tcg/cpu-exec.c | 3 ++- target/alpha/cpu.c | 1 + target/arm/cpu.c | 1 + target/arm/tcg/cpu-v7m.c | 1 + target/avr/cpu.c | 1 + target/hppa/cpu.c | 1 + target/i386/tcg/tcg-cpu.c | 1 + target/loongarch/cpu.c | 1 + target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/ppc/cpu_init.c | 1 + target/riscv/tcg/tcg-cpu.c | 1 + target/rx/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sh4/cpu.c | 1 + target/sparc/cpu.c | 1 + target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + 21 files changed, 23 insertions(+), 1 deletion(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 60b5e97205..3ff72b8d9d 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -155,6 +155,8 @@ struct TCGCPUOps { void (*do_interrupt)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** @cpu_exec_reset: Callback for reset in cpu_exec. */ + void (*cpu_exec_reset)(CPUState *cpu); /** * @cpu_exec_halt: Callback for handling halt in cpu_exec. * diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ff979a2c57..010f38edaa 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -834,7 +834,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, #else else if (interrupt_request & CPU_INTERRUPT_RESET) { replay_interrupt(); - cpu_reset(cpu); + cpu->cc->tcg_ops->cpu_exec_reset(cpu); bql_unlock(); return true; } @@ -1070,6 +1070,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) #ifndef CONFIG_USER_ONLY assert(tcg_ops->cpu_exec_halt); assert(tcg_ops->cpu_exec_interrupt); + assert(tcg_ops->cpu_exec_reset); #endif /* !CONFIG_USER_ONLY */ assert(tcg_ops->translate_code); assert(tcg_ops->mmu_index); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 68414af8d3..d4e66aa432 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -251,6 +251,7 @@ static const TCGCPUOps alpha_tcg_ops = { .tlb_fill = alpha_cpu_tlb_fill, .cpu_exec_interrupt = alpha_cpu_exec_interrupt, .cpu_exec_halt = alpha_cpu_has_work, + .cpu_exec_reset = cpu_reset, .do_interrupt = alpha_cpu_do_interrupt, .do_transaction_failed = alpha_cpu_do_transaction_failed, .do_unaligned_access = alpha_cpu_do_unaligned_access, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7b801eb3aa..3dde70b04a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2705,6 +2705,7 @@ static const TCGCPUOps arm_tcg_ops = { .tlb_fill_align = arm_cpu_tlb_fill_align, .cpu_exec_interrupt = arm_cpu_exec_interrupt, .cpu_exec_halt = arm_cpu_exec_halt, + .cpu_exec_reset = cpu_reset, .do_interrupt = arm_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, .do_unaligned_access = arm_cpu_do_unaligned_access, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index b34b657857..5c8c374885 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -250,6 +250,7 @@ static const TCGCPUOps arm_v7m_tcg_ops = { .tlb_fill_align = arm_cpu_tlb_fill_align, .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, .cpu_exec_halt = arm_cpu_exec_halt, + .cpu_exec_reset = cpu_reset, .do_interrupt = arm_v7m_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, .do_unaligned_access = arm_cpu_do_unaligned_access, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 69fface7e9..50b835e1ae 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -232,6 +232,7 @@ static const TCGCPUOps avr_tcg_ops = { .mmu_index = avr_cpu_mmu_index, .cpu_exec_interrupt = avr_cpu_exec_interrupt, .cpu_exec_halt = avr_cpu_has_work, + .cpu_exec_reset = cpu_reset, .tlb_fill = avr_cpu_tlb_fill, .do_interrupt = avr_cpu_do_interrupt, }; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index b083693b57..60b618a22b 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -271,6 +271,7 @@ static const TCGCPUOps hppa_tcg_ops = { .tlb_fill_align = hppa_cpu_tlb_fill_align, .cpu_exec_interrupt = hppa_cpu_exec_interrupt, .cpu_exec_halt = hppa_cpu_has_work, + .cpu_exec_reset = cpu_reset, .do_interrupt = hppa_cpu_do_interrupt, .do_unaligned_access = hppa_cpu_do_unaligned_access, .do_transaction_failed = hppa_cpu_do_transaction_failed, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 192812656c..5d1c758ae3 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -147,6 +147,7 @@ const TCGCPUOps x86_tcg_ops = { .do_interrupt = x86_cpu_do_interrupt, .cpu_exec_halt = x86_cpu_exec_halt, .cpu_exec_interrupt = x86_cpu_exec_interrupt, + .cpu_exec_reset = cpu_reset, .do_unaligned_access = x86_cpu_do_unaligned_access, .debug_excp_handler = breakpoint_handler, .debug_check_breakpoint = x86_debug_check_breakpoint, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index c083ad4fd9..c64cba72dd 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -877,6 +877,7 @@ static const TCGCPUOps loongarch_tcg_ops = { .tlb_fill = loongarch_cpu_tlb_fill, .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, .cpu_exec_halt = loongarch_cpu_has_work, + .cpu_exec_reset = cpu_reset, .do_interrupt = loongarch_cpu_do_interrupt, .do_transaction_failed = loongarch_cpu_do_transaction_failed, #endif diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 6f33b86c7d..f446c6c8f7 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -602,6 +602,7 @@ static const TCGCPUOps m68k_tcg_ops = { .tlb_fill = m68k_cpu_tlb_fill, .cpu_exec_interrupt = m68k_cpu_exec_interrupt, .cpu_exec_halt = m68k_cpu_has_work, + .cpu_exec_reset = cpu_reset, .do_interrupt = m68k_cpu_do_interrupt, .do_transaction_failed = m68k_cpu_transaction_failed, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 2720e5c1d2..f305ed04f6 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -440,6 +440,7 @@ static const TCGCPUOps mb_tcg_ops = { .tlb_fill = mb_cpu_tlb_fill, .cpu_exec_interrupt = mb_cpu_exec_interrupt, .cpu_exec_halt = mb_cpu_has_work, + .cpu_exec_reset = cpu_reset, .do_interrupt = mb_cpu_do_interrupt, .do_transaction_failed = mb_cpu_transaction_failed, .do_unaligned_access = mb_cpu_do_unaligned_access, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 96fe4da255..09ed330027 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -563,6 +563,7 @@ static const TCGCPUOps mips_tcg_ops = { .tlb_fill = mips_cpu_tlb_fill, .cpu_exec_interrupt = mips_cpu_exec_interrupt, .cpu_exec_halt = mips_cpu_has_work, + .cpu_exec_reset = cpu_reset, .do_interrupt = mips_cpu_do_interrupt, .do_transaction_failed = mips_cpu_do_transaction_failed, .do_unaligned_access = mips_cpu_do_unaligned_access, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 8c8165d666..94776e0ad8 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -255,6 +255,7 @@ static const TCGCPUOps openrisc_tcg_ops = { .tlb_fill = openrisc_cpu_tlb_fill, .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, .cpu_exec_halt = openrisc_cpu_has_work, + .cpu_exec_reset = cpu_reset, .do_interrupt = openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index b0973b6df9..3a01731402 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7492,6 +7492,7 @@ static const TCGCPUOps ppc_tcg_ops = { .tlb_fill = ppc_cpu_tlb_fill, .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .cpu_exec_halt = ppc_cpu_has_work, + .cpu_exec_reset = cpu_reset, .do_interrupt = ppc_cpu_do_interrupt, .cpu_exec_enter = ppc_cpu_exec_enter, .cpu_exec_exit = ppc_cpu_exec_exit, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 2f757c2a5e..50782e0f0e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -153,6 +153,7 @@ const TCGCPUOps riscv_tcg_ops = { .tlb_fill = riscv_cpu_tlb_fill, .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .cpu_exec_halt = riscv_cpu_has_work, + .cpu_exec_reset = cpu_reset, .do_interrupt = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, .do_unaligned_access = riscv_cpu_do_unaligned_access, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index a51b543028..de2e6a22ff 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -217,6 +217,7 @@ static const TCGCPUOps rx_tcg_ops = { .cpu_exec_interrupt = rx_cpu_exec_interrupt, .cpu_exec_halt = rx_cpu_has_work, + .cpu_exec_reset = cpu_reset, .do_interrupt = rx_cpu_do_interrupt, }; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 99ff58affc..71338aae77 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -365,6 +365,7 @@ static const TCGCPUOps s390_tcg_ops = { .tlb_fill = s390_cpu_tlb_fill, .cpu_exec_interrupt = s390_cpu_exec_interrupt, .cpu_exec_halt = s390_cpu_has_work, + .cpu_exec_reset = cpu_reset, .do_interrupt = s390_cpu_do_interrupt, .debug_excp_handler = s390x_cpu_debug_excp_handler, .do_unaligned_access = s390x_cpu_do_unaligned_access, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 1885e7d5b2..681237c511 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -275,6 +275,7 @@ static const TCGCPUOps superh_tcg_ops = { .tlb_fill = superh_cpu_tlb_fill, .cpu_exec_interrupt = superh_cpu_exec_interrupt, .cpu_exec_halt = superh_cpu_has_work, + .cpu_exec_reset = cpu_reset, .do_interrupt = superh_cpu_do_interrupt, .do_unaligned_access = superh_cpu_do_unaligned_access, .io_recompile_replay_branch = superh_io_recompile_replay_branch, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 690e74f109..bbdea8556a 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1034,6 +1034,7 @@ static const TCGCPUOps sparc_tcg_ops = { .tlb_fill = sparc_cpu_tlb_fill, .cpu_exec_interrupt = sparc_cpu_exec_interrupt, .cpu_exec_halt = sparc_cpu_has_work, + .cpu_exec_reset = cpu_reset, .do_interrupt = sparc_cpu_do_interrupt, .do_transaction_failed = sparc_cpu_do_transaction_failed, .do_unaligned_access = sparc_cpu_do_unaligned_access, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 9f19e903bc..0fcac697f6 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -182,6 +182,7 @@ static const TCGCPUOps tricore_tcg_ops = { .tlb_fill = tricore_cpu_tlb_fill, .cpu_exec_interrupt = tricore_cpu_exec_interrupt, .cpu_exec_halt = tricore_cpu_has_work, + .cpu_exec_reset = cpu_reset, }; static void tricore_cpu_class_init(ObjectClass *c, const void *data) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 27d6e40195..9dcb883208 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -246,6 +246,7 @@ static const TCGCPUOps xtensa_tcg_ops = { .tlb_fill = xtensa_cpu_tlb_fill, .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, .cpu_exec_halt = xtensa_cpu_has_work, + .cpu_exec_reset = cpu_reset, .do_interrupt = xtensa_cpu_do_interrupt, .do_transaction_failed = xtensa_cpu_do_transaction_failed, .do_unaligned_access = xtensa_cpu_do_unaligned_access, From patchwork Wed Apr 30 16:48:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 886069 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:38f:210b:807b with SMTP id g4csp957782wrq; Wed, 30 Apr 2025 09:51:43 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWENgshGVjOtSFCeXRZwU+Ybfqt5Rt9K12n3SUUnv00pPuq/B/SstxpOCOoypqRfSbU/EpdQg==@linaro.org X-Google-Smtp-Source: AGHT+IFD5lYI8hybyY4WAAkVdxK9rLrWjqao8zf3NR4IZxCxeo9INjeSMBq23ruc1SICH8rpVdrE X-Received: by 2002:a05:622a:559a:b0:476:977c:2eb0 with SMTP id d75a77b69052e-489c416ca79mr72966121cf.30.1746031903313; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.48.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:48:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 04/16] target/i386: Split out x86_cpu_exec_reset Date: Wed, 30 Apr 2025 09:48:42 -0700 Message-ID: <20250430164854.2233995-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Note that target/i386/cpu.h defines CPU_INTERRUPT_INIT as CPU_INTERRUPT_RESET. Therefore we can handle the new TCGCPUOps.cpu_exec_reset hook. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 39 ++++++++++++++------------------------- target/i386/tcg/tcg-cpu.c | 11 ++++++++++- 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 010f38edaa..c21c5d202d 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -819,33 +819,22 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, cpu->exception_index = EXCP_HLT; bql_unlock(); return true; - } -#if defined(TARGET_I386) - else if (interrupt_request & CPU_INTERRUPT_INIT) { - X86CPU *x86_cpu = X86_CPU(cpu); - CPUArchState *env = &x86_cpu->env; - replay_interrupt(); - cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0, 0); - do_cpu_init(x86_cpu); - cpu->exception_index = EXCP_HALTED; - bql_unlock(); - return true; - } -#else - else if (interrupt_request & CPU_INTERRUPT_RESET) { - replay_interrupt(); - cpu->cc->tcg_ops->cpu_exec_reset(cpu); - bql_unlock(); - return true; - } -#endif /* !TARGET_I386 */ - /* The target hook has 3 exit conditions: - False when the interrupt isn't processed, - True when it is, and we should restart on a new TB, - and via longjmp via cpu_loop_exit. */ - else { + } else { const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; + if (interrupt_request & CPU_INTERRUPT_RESET) { + replay_interrupt(); + tcg_ops->cpu_exec_reset(cpu); + bql_unlock(); + return true; + } + + /* + * The target hook has 3 exit conditions: + * False when the interrupt isn't processed, + * True when it is, and we should restart on a new TB, + * and via longjmp via cpu_loop_exit. + */ if (tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { if (!tcg_ops->need_replay_interrupt || tcg_ops->need_replay_interrupt(interrupt_request)) { diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 5d1c758ae3..f3f0380e70 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -120,6 +120,15 @@ static bool x86_debug_check_breakpoint(CPUState *cs) /* RF disables all architectural breakpoints. */ return !(env->eflags & RF_MASK); } + +static void x86_cpu_exec_reset(CPUState *cs) +{ + CPUArchState *env = cpu_env(cs); + + cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0, 0); + do_cpu_init(env_archcpu(env)); + cs->exception_index = EXCP_HALTED; +} #endif #include "accel/tcg/cpu-ops.h" @@ -147,7 +156,7 @@ const TCGCPUOps x86_tcg_ops = { .do_interrupt = x86_cpu_do_interrupt, .cpu_exec_halt = x86_cpu_exec_halt, .cpu_exec_interrupt = x86_cpu_exec_interrupt, - .cpu_exec_reset = cpu_reset, + .cpu_exec_reset = x86_cpu_exec_reset, .do_unaligned_access = x86_cpu_do_unaligned_access, .debug_excp_handler = breakpoint_handler, .debug_check_breakpoint = x86_debug_check_breakpoint, From patchwork Wed Apr 30 16:48:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 886071 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:38f:210b:807b with SMTP id g4csp957783wrq; Wed, 30 Apr 2025 09:51:43 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVanChTFD0EsJqK6Lgvc10sB+3GqyMBFUJ2yRm4RuzTifZ5yCpWEbcoyKVCUngE1v5QE/TSYg==@linaro.org X-Google-Smtp-Source: AGHT+IG5ZovpQBjs9ceJP9KUPJ2AW7ZCCGQ2OTBqhlFSFKZMA4D3mJCj6o/nce8wkJP5hLcCOADj X-Received: by 2002:a05:620a:424f:b0:7c5:4eee:5405 with SMTP id af79cd13be357-7cac76be6f3mr460063885a.35.1746031903330; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.48.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:48:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 05/16] accel/tcg: Hoist cpu_get_tb_cpu_state decl to accl/tcg/cpu-ops.h Date: Wed, 30 Apr 2025 09:48:43 -0700 Message-ID: <20250430164854.2233995-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For some targets, simply remove the local definition. For other targets, move the inline definition out of line. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 3 ++ target/alpha/cpu.h | 11 ------ target/arm/cpu.h | 3 -- target/avr/cpu.h | 18 ---------- target/hexagon/cpu.h | 15 -------- target/hppa/cpu.h | 3 -- target/i386/cpu.h | 14 -------- target/loongarch/cpu.h | 12 ------- target/m68k/cpu.h | 16 --------- target/microblaze/cpu.h | 8 ----- target/mips/cpu.h | 9 ----- target/openrisc/cpu.h | 10 ------ target/ppc/cpu.h | 13 ------- target/riscv/cpu.h | 3 -- target/rx/cpu.h | 9 ----- target/s390x/cpu.h | 9 ----- target/sh4/cpu.h | 15 -------- target/sparc/cpu.h | 3 -- target/tricore/cpu.h | 12 ------- target/xtensa/cpu.h | 68 ----------------------------------- target/alpha/cpu.c | 14 ++++++-- target/arm/helper.c | 1 + target/avr/cpu.c | 21 +++++++++-- target/hexagon/cpu.c | 18 ++++++++-- target/hppa/cpu.c | 3 +- target/i386/tcg/tcg-cpu.c | 17 +++++++-- target/loongarch/cpu.c | 15 ++++++-- target/m68k/cpu.c | 19 ++++++++-- target/microblaze/cpu.c | 11 ++++-- target/mips/cpu.c | 9 +++++ target/openrisc/cpu.c | 13 +++++-- target/ppc/helper_regs.c | 16 ++++----- target/rx/cpu.c | 12 +++++-- target/s390x/cpu.c | 1 + target/sh4/cpu.c | 18 ++++++++-- target/tricore/cpu.c | 15 ++++++-- target/xtensa/cpu.c | 71 +++++++++++++++++++++++++++++++++++-- 37 files changed, 243 insertions(+), 285 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 3ff72b8d9d..f5e5746976 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -18,6 +18,9 @@ #include "exec/vaddr.h" #include "tcg/tcg-mo.h" +void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags); + struct TCGCPUOps { /** * mttcg_supported: multi-threaded TCG is supported diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 849f673489..45944e46b5 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -464,17 +464,6 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, MemTxResult response, uintptr_t retaddr); #endif -static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - *pc = env->pc; - *cs_base = 0; - *pflags = env->flags & ENV_FLAG_TB_MASK; -#ifdef CONFIG_USER_ONLY - *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#endif -} - #ifdef CONFIG_USER_ONLY /* Copied from linux ieee_swcr_to_fpcr. */ static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fdcf8cd1ae..be4449ca06 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3119,9 +3119,6 @@ static inline bool bswap_code(bool sctlr_b) #endif } -void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); - enum { QEMU_PSCI_CONDUIT_DISABLED = 0, QEMU_PSCI_CONDUIT_SMC = 1, diff --git a/target/avr/cpu.h b/target/avr/cpu.h index d6666175a9..518e243d81 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -205,24 +205,6 @@ enum { TB_FLAGS_SKIP = 2, }; -static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - uint32_t flags = 0; - - *pc = env->pc_w * 2; - *cs_base = 0; - - if (env->fullacc) { - flags |= TB_FLAGS_FULL_ACCESS; - } - if (env->skip) { - flags |= TB_FLAGS_SKIP; - } - - *pflags = flags; -} - static inline int cpu_interrupts_enabled(CPUAVRState *env) { return env->sregI != 0; diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index c065fa8ddc..43a854f517 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -137,21 +137,6 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, uint32_t exception, uintptr_t pc); -static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - uint32_t hex_flags = 0; - *pc = env->gpr[HEX_REG_PC]; - *cs_base = 0; - if (*pc == env->gpr[HEX_REG_SA0]) { - hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); - } - *flags = hex_flags; - if (*pc & PCALIGN_MASK) { - hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); - } -} - typedef HexagonCPU ArchCPU; void hexagon_translate_init(void); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index acc9937240..11d59d11ca 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -351,9 +351,6 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); #define CS_BASE_DIFFPAGE (1 << 12) #define CS_BASE_DIFFSPACE (1 << 13) -void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags); - target_ulong cpu_hppa_get_psw(CPUHPPAState *env); void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); void update_gva_offset_mask(CPUHPPAState *env); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 3182ba413b..4f8ed8868e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2599,20 +2599,6 @@ static inline bool is_mmu_index_32(int mmu_index) #include "hw/i386/apic.h" #endif -static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *flags = env->hflags | - (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); - if (env->hflags & HF_CS64_MASK) { - *cs_base = 0; - *pc = env->eip; - } else { - *cs_base = env->segs[R_CS].base; - *pc = (uint32_t)(*cs_base + env->eip); - } -} - void do_cpu_init(X86CPU *cpu); #define MCE_INJECT_BROADCAST 1 diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 70ff56e60c..262bf87f7b 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -492,18 +492,6 @@ static inline void set_pc(CPULoongArchState *env, uint64_t value) #define HW_FLAGS_VA32 0x20 #define HW_FLAGS_EUEN_ASXE 0x40 -static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->pc; - *cs_base = 0; - *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); - *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; - *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE; - *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE; - *flags |= is_va32(env) * HW_FLAGS_VA32; -} - #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU void loongarch_cpu_post_init(Object *obj); diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 39d0b9d6d7..d9db6a486a 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -605,22 +605,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, #define TB_FLAGS_TRACE 16 #define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE) -static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->pc; - *cs_base = 0; - *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; - if (env->sr & SR_S) { - *flags |= TB_FLAGS_MSR_S; - *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; - *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; - } - if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) { - *flags |= TB_FLAGS_TRACE; - } -} - void dump_mmu(CPUM68KState *env); #endif diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d511f22a55..6ad8643f2e 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -419,14 +419,6 @@ static inline bool mb_cpu_is_big_endian(CPUState *cs) return !cpu->cfg.endi; } -static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->pc; - *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); - *cs_base = (*flags & IMM_FLAG ? env->imm : 0); -} - #if !defined(CONFIG_USER_ONLY) bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/target/mips/cpu.h b/target/mips/cpu.h index d16f9a7220..5cd4c6c818 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1366,15 +1366,6 @@ void cpu_mips_clock_init(MIPSCPU *cpu); /* helper.c */ target_ulong exception_resume_pc(CPUMIPSState *env); -static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->active_tc.PC; - *cs_base = 0; - *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | - MIPS_HFLAG_HWRENA_ULR); -} - /** * mips_cpu_create_with_clock: * @typename: a MIPS CPU type. diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 569819bfb0..f4bcf00b07 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -349,16 +349,6 @@ static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val) env->shadow_gpr[0][i] = val; } -static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->pc; - *cs_base = 0; - *flags = (env->dflag ? TB_FLAGS_DFLAG : 0) - | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) - | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); -} - static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) { return (env->sr diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 13115a89ff..6b90543811 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2751,19 +2751,6 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xer); */ #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B)) -#ifdef CONFIG_DEBUG_TCG -void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); -#else -static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->nip; - *cs_base = 0; - *flags = env->hflags; -} -#endif - G_NORETURN void raise_exception_err_ra(CPUPPCState *env, uint32_t exception, uint32_t error_code, uintptr_t raddr); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 167909c89b..c66ac3bc27 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -802,9 +802,6 @@ static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew, return vlen >> (vsew + 3 - lmul); } -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags); - bool riscv_cpu_is_32bit(RISCVCPU *cpu); bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 5c19c83219..ba5761b647 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -153,15 +153,6 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); #define RX_CPU_IRQ 0 #define RX_CPU_FIR 1 -static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->pc; - *cs_base = 0; - *flags = FIELD_DP32(0, PSW, PM, env->psw_pm); - *flags = FIELD_DP32(*flags, PSW, U, env->psw_u); -} - static inline uint32_t rx_cpu_pack_psw(CPURXState *env) { uint32_t psw = 0; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 530d97ccf1..aa931cb674 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -411,15 +411,6 @@ static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch) #endif } -#ifdef CONFIG_TCG - -#include "tcg/tcg_s390x.h" - -void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); - -#endif /* CONFIG_TCG */ - /* PER bits from control register 9 */ #define PER_CR9_EVENT_BRANCH 0x80000000 #define PER_CR9_EVENT_IFETCH 0x40000000 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 906f99ddf0..c41ab70dd7 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -380,19 +380,4 @@ static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr) env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); } -static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->pc; - /* For a gUSA region, notice the end of the region. */ - *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; - *flags = env->flags - | (env->fpscr & TB_FLAG_FPSCR_MASK) - | (env->sr & TB_FLAG_SR_MASK) - | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ -#ifdef CONFIG_USER_ONLY - *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#endif -} - #endif /* SH4_CPU_H */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 37fd1e066e..31cb3d97eb 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -741,9 +741,6 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_FSR_QNE (1 << 8) #define TB_FLAG_ASI_SHIFT 24 -void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags); - static inline bool tb_fpu_enabled(int tb_flags) { #if defined(CONFIG_USER_ONLY) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index c76e65f818..82085fbc32 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -258,18 +258,6 @@ void tricore_tcg_init(void); void tricore_translate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc); -static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - uint32_t new_flags = 0; - *pc = env->PC; - *cs_base = 0; - - new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV, - extract32(env->PSW, 10, 2)); - *flags = new_flags; -} - #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU /* helpers.c */ diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index c03ed71c94..74122ebe15 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -733,74 +733,6 @@ static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 -static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->pc; - *cs_base = 0; - *flags = 0; - *flags |= xtensa_get_ring(env); - if (env->sregs[PS] & PS_EXCM) { - *flags |= XTENSA_TBFLAG_EXCM; - } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { - target_ulong lend_dist = - env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); - - /* - * 0 in the csbase_lend field means that there may not be a loopback - * for any instruction that starts inside this page. Any other value - * means that an instruction that ends at this offset from the page - * start may loop back and will need loopback code to be generated. - * - * lend_dist is 0 when LEND points to the start of the page, but - * no instruction that starts inside this page may end at offset 0, - * so it's still correct. - * - * When an instruction ends at a page boundary it may only start in - * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE - * for the TB that contains this instruction. - */ - if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) { - target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG]; - - *cs_base = lend_dist; - if (lbeg_off < 256) { - *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; - } - } - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && - (env->sregs[LITBASE] & 1)) { - *flags |= XTENSA_TBFLAG_LITBASE; - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { - if (xtensa_get_cintlevel(env) < env->config->debug_level) { - *flags |= XTENSA_TBFLAG_DEBUG; - } - if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { - *flags |= XTENSA_TBFLAG_ICOUNT; - } - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { - *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) && - (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) { - uint32_t windowstart = xtensa_replicate_windowstart(env) >> - (env->sregs[WINDOW_BASE] + 1); - uint32_t w = ctz32(windowstart | 0x8); - - *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; - *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT, - PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; - } else { - *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT; - } - if (env->yield_needed) { - *flags |= XTENSA_TBFLAG_YIELD; - } -} - XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index d4e66aa432..134806e755 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -25,6 +25,7 @@ #include "cpu.h" #include "exec/translation-block.h" #include "exec/target_page.h" +#include "accel/tcg/cpu-ops.h" #include "fpu/softfloat.h" @@ -40,6 +41,17 @@ static vaddr alpha_cpu_get_pc(CPUState *cs) return env->pc; } +void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + *pc = env->pc; + *cs_base = 0; + *pflags = env->flags & ENV_FLAG_TB_MASK; +#ifdef CONFIG_USER_ONLY + *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif +} + static void alpha_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -231,8 +243,6 @@ static const struct SysemuCPUOps alpha_sysemu_ops = { }; #endif -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps alpha_tcg_ops = { /* Alpha processors have a weak memory model */ .guest_default_memory_order = 0, diff --git a/target/arm/helper.c b/target/arm/helper.c index 8de4eb2c1f..98adeb7086 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -30,6 +30,7 @@ #include "qemu/guest-random.h" #ifdef CONFIG_TCG #include "accel/tcg/probe.h" +#include "accel/tcg/cpu-ops.h" #include "semihosting/common-semi.h" #endif #include "cpregs.h" diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 50b835e1ae..d9fecb272e 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -27,6 +27,7 @@ #include "disas/dis-asm.h" #include "tcg/debug-assert.h" #include "hw/qdev-properties.h" +#include "accel/tcg/cpu-ops.h" static void avr_cpu_set_pc(CPUState *cs, vaddr value) { @@ -53,6 +54,24 @@ static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } +void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags = 0; + + *pc = env->pc_w * 2; + *cs_base = 0; + + if (env->fullacc) { + flags |= TB_FLAGS_FULL_ACCESS; + } + if (env->skip) { + flags |= TB_FLAGS_SKIP; + } + + *pflags = flags; +} + static void avr_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -220,8 +239,6 @@ static const struct SysemuCPUOps avr_sysemu_ops = { .get_phys_page_debug = avr_cpu_get_phys_page_debug, }; -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps avr_tcg_ops = { .guest_default_memory_order = 0, .mttcg_supported = false, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index c1bfa80252..2272f1222b 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -25,6 +25,7 @@ #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" #include "exec/gdbstub.h" +#include "accel/tcg/cpu-ops.h" static void hexagon_v66_cpu_init(Object *obj) { } static void hexagon_v67_cpu_init(Object *obj) { } @@ -254,6 +255,21 @@ static vaddr hexagon_cpu_get_pc(CPUState *cs) return cpu_env(cs)->gpr[HEX_REG_PC]; } +void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + uint32_t hex_flags = 0; + *pc = env->gpr[HEX_REG_PC]; + *cs_base = 0; + if (*pc == env->gpr[HEX_REG_SA0]) { + hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); + } + *flags = hex_flags; + if (*pc & PCALIGN_MASK) { + hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); + } +} + static void hexagon_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -321,8 +337,6 @@ static void hexagon_cpu_init(Object *obj) { } -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps hexagon_tcg_ops = { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 60b618a22b..4cdaf98ab1 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -29,6 +29,7 @@ #include "fpu/softfloat.h" #include "tcg/tcg.h" #include "hw/hppa/hppa_hardware.h" +#include "accel/tcg/cpu-ops.h" static void hppa_cpu_set_pc(CPUState *cs, vaddr value) { @@ -249,8 +250,6 @@ static const struct SysemuCPUOps hppa_sysemu_ops = { }; #endif -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps hppa_tcg_ops = { /* PA-RISC 1.x processors have a strong memory model. */ /* diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index f3f0380e70..bb6f82befb 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -24,6 +24,7 @@ #include "accel/accel-cpu-target.h" #include "exec/translation-block.h" #include "exec/target_page.h" +#include "accel/tcg/cpu-ops.h" #include "tcg-cpu.h" /* Frob eflags into and out of the CPU temporary format. */ @@ -47,6 +48,20 @@ static void x86_cpu_exec_exit(CPUState *cs) env->eflags = cpu_compute_eflags(env); } +void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *flags = env->hflags | + (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); + if (env->hflags & HF_CS64_MASK) { + *cs_base = 0; + *pc = env->eip; + } else { + *cs_base = env->segs[R_CS].base; + *pc = (uint32_t)(*cs_base + env->eip); + } +} + static void x86_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -131,8 +146,6 @@ static void x86_cpu_exec_reset(CPUState *cs) } #endif -#include "accel/tcg/cpu-ops.h" - const TCGCPUOps x86_tcg_ops = { .mttcg_supported = true, .precise_smc = true, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index c64cba72dd..be770b7e19 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -29,6 +29,7 @@ #endif #ifdef CONFIG_TCG #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" #endif #include "tcg/tcg_loongarch.h" @@ -335,6 +336,18 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } #endif +void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->pc; + *cs_base = 0; + *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); + *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; + *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE; + *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE; + *flags |= is_va32(env) * HW_FLAGS_VA32; +} + static void loongarch_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -861,8 +874,6 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) } #ifdef CONFIG_TCG -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps loongarch_tcg_ops = { .guest_default_memory_order = 0, .mttcg_supported = true, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index f446c6c8f7..2b4ec40509 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "migration/vmstate.h" #include "fpu/softfloat.h" +#include "accel/tcg/cpu-ops.h" static void m68k_cpu_set_pc(CPUState *cs, vaddr value) { @@ -38,6 +39,22 @@ static vaddr m68k_cpu_get_pc(CPUState *cs) return cpu->env.pc; } +void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->pc; + *cs_base = 0; + *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; + if (env->sr & SR_S) { + *flags |= TB_FLAGS_MSR_S; + *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; + *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; + } + if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) { + *flags |= TB_FLAGS_TRACE; + } +} + static void m68k_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) @@ -586,8 +603,6 @@ static const struct SysemuCPUOps m68k_sysemu_ops = { }; #endif /* !CONFIG_USER_ONLY */ -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps m68k_tcg_ops = { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index f305ed04f6..105ede0b1e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -31,6 +31,7 @@ #include "exec/gdbstub.h" #include "exec/translation-block.h" #include "fpu/softfloat-helpers.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" static const struct { @@ -94,6 +95,14 @@ static vaddr mb_cpu_get_pc(CPUState *cs) return cpu->env.pc; } +void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->pc; + *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); + *cs_base = (*flags & IMM_FLAG ? env->imm : 0); +} + static void mb_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -423,8 +432,6 @@ static const struct SysemuCPUOps mb_sysemu_ops = { }; #endif -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps mb_tcg_ops = { /* MicroBlaze is always in-order. */ .guest_default_memory_order = TCG_MO_ALL, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 09ed330027..ab00adf86b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -549,6 +549,15 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) return mips_env_mmu_index(cpu_env(cs)); } +void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->active_tc.PC; + *cs_base = 0; + *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | + MIPS_HFLAG_HWRENA_ULR); +} + static const TCGCPUOps mips_tcg_ops = { .mttcg_supported = TARGET_LONG_BITS == 32, .guest_default_memory_order = 0, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 94776e0ad8..d798127d67 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "exec/translation-block.h" #include "fpu/softfloat-helpers.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) @@ -40,6 +41,16 @@ static vaddr openrisc_cpu_get_pc(CPUState *cs) return cpu->env.pc; } +void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->pc; + *cs_base = 0; + *flags = (env->dflag ? TB_FLAGS_DFLAG : 0) + | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) + | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); +} + static void openrisc_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -239,8 +250,6 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { }; #endif -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps openrisc_tcg_ops = { .guest_default_memory_order = 0, .mttcg_supported = true, diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index f211bc9830..8d248bcbb9 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -27,6 +27,7 @@ #include "power8-pmu.h" #include "cpu-models.h" #include "spr_common.h" +#include "accel/tcg/cpu-ops.h" /* Swap temporary saved registers with GPRs */ void hreg_swap_gpr_tgpr(CPUPPCState *env) @@ -255,26 +256,25 @@ void hreg_update_pmu_hflags(CPUPPCState *env) env->hflags |= hreg_compute_pmu_hflags_value(env); } -#ifdef CONFIG_DEBUG_TCG void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { uint32_t hflags_current = env->hflags; - uint32_t hflags_rebuilt; - *pc = env->nip; - *cs_base = 0; - *flags = hflags_current; - - hflags_rebuilt = hreg_compute_hflags_value(env); +#ifdef CONFIG_DEBUG_TCG + uint32_t hflags_rebuilt = hreg_compute_hflags_value(env); if (unlikely(hflags_current != hflags_rebuilt)) { cpu_abort(env_cpu(env), "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n", hflags_current, hflags_rebuilt); } -} #endif + *pc = env->nip; + *cs_base = 0; + *flags = hflags_current; +} + void cpu_interrupt_exittb(CPUState *cs) { /* diff --git a/target/rx/cpu.c b/target/rx/cpu.c index de2e6a22ff..e8b47be675 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -28,6 +28,7 @@ #include "hw/loader.h" #include "fpu/softfloat.h" #include "tcg/debug-assert.h" +#include "accel/tcg/cpu-ops.h" static void rx_cpu_set_pc(CPUState *cs, vaddr value) { @@ -43,6 +44,15 @@ static vaddr rx_cpu_get_pc(CPUState *cs) return cpu->env.pc; } +void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->pc; + *cs_base = 0; + *flags = FIELD_DP32(0, PSW, PM, env->psw_pm); + *flags = FIELD_DP32(*flags, PSW, U, env->psw_u); +} + static void rx_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -201,8 +211,6 @@ static const struct SysemuCPUOps rx_sysemu_ops = { .get_phys_page_debug = rx_cpu_get_phys_page_debug, }; -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps rx_tcg_ops = { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 71338aae77..435b2034ff 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -302,6 +302,7 @@ static const Property s390x_cpu_properties[] = { #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" +#include "tcg/tcg_s390x.h" static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch) { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 681237c511..5fb18bf55e 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -26,6 +26,7 @@ #include "migration/vmstate.h" #include "exec/translation-block.h" #include "fpu/softfloat-helpers.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" static void superh_cpu_set_pc(CPUState *cs, vaddr value) @@ -42,6 +43,21 @@ static vaddr superh_cpu_get_pc(CPUState *cs) return cpu->env.pc; } +void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->pc; + /* For a gUSA region, notice the end of the region. */ + *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; + *flags = env->flags + | (env->fpscr & TB_FLAG_FPSCR_MASK) + | (env->sr & TB_FLAG_SR_MASK) + | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ +#ifdef CONFIG_USER_ONLY + *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif +} + static void superh_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -258,8 +274,6 @@ static const struct SysemuCPUOps sh4_sysemu_ops = { }; #endif -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps superh_tcg_ops = { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 0fcac697f6..81b3bb6362 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -23,6 +23,7 @@ #include "exec/translation-block.h" #include "qemu/error-report.h" #include "tcg/debug-assert.h" +#include "accel/tcg/cpu-ops.h" static inline void set_feature(CPUTriCoreState *env, int feature) { @@ -44,6 +45,18 @@ static vaddr tricore_cpu_get_pc(CPUState *cs) return cpu_env(cs)->PC; } +void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + uint32_t new_flags = 0; + *pc = env->PC; + *cs_base = 0; + + new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV, + extract32(env->PSW, 10, 2)); + *flags = new_flags; +} + static void tricore_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -168,8 +181,6 @@ static const struct SysemuCPUOps tricore_sysemu_ops = { .get_phys_page_debug = tricore_cpu_get_phys_page_debug, }; -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps tricore_tcg_ops = { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 9dcb883208..c78ef9421c 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -35,6 +35,7 @@ #include "qemu/module.h" #include "migration/vmstate.h" #include "hw/qdev-clock.h" +#include "accel/tcg/cpu-ops.h" #ifndef CONFIG_USER_ONLY #include "system/memory.h" #endif @@ -54,6 +55,74 @@ static vaddr xtensa_cpu_get_pc(CPUState *cs) return cpu->env.pc; } +void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->pc; + *cs_base = 0; + *flags = 0; + *flags |= xtensa_get_ring(env); + if (env->sregs[PS] & PS_EXCM) { + *flags |= XTENSA_TBFLAG_EXCM; + } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { + target_ulong lend_dist = + env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); + + /* + * 0 in the csbase_lend field means that there may not be a loopback + * for any instruction that starts inside this page. Any other value + * means that an instruction that ends at this offset from the page + * start may loop back and will need loopback code to be generated. + * + * lend_dist is 0 when LEND points to the start of the page, but + * no instruction that starts inside this page may end at offset 0, + * so it's still correct. + * + * When an instruction ends at a page boundary it may only start in + * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE + * for the TB that contains this instruction. + */ + if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) { + target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG]; + + *cs_base = lend_dist; + if (lbeg_off < 256) { + *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; + } + } + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && + (env->sregs[LITBASE] & 1)) { + *flags |= XTENSA_TBFLAG_LITBASE; + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { + if (xtensa_get_cintlevel(env) < env->config->debug_level) { + *flags |= XTENSA_TBFLAG_DEBUG; + } + if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { + *flags |= XTENSA_TBFLAG_ICOUNT; + } + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { + *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) && + (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) { + uint32_t windowstart = xtensa_replicate_windowstart(env) >> + (env->sregs[WINDOW_BASE] + 1); + uint32_t w = ctz32(windowstart | 0x8); + + *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; + *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT, + PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; + } else { + *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT; + } + if (env->yield_needed) { + *flags |= XTENSA_TBFLAG_YIELD; + } +} + static void xtensa_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) @@ -229,8 +298,6 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = { }; #endif -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps xtensa_tcg_ops = { /* Xtensa processors have a weak memory model */ .guest_default_memory_order = 0, From patchwork Wed Apr 30 16:48:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 886067 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:38f:210b:807b with SMTP id g4csp957154wrq; Wed, 30 Apr 2025 09:50:12 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVIGkwkTNjWFf//IcdmEJWqkmYtWw/sB7SFNwVPQVvzQVTu3jZBWoFxVIYyp5d6Fgl+/K0yNg==@linaro.org X-Google-Smtp-Source: AGHT+IEHYdmih8Y92k+SZUIEcmW23tvM+COsp3tbFiTNnRqos38tYlQMXiWfRQOdz2fHTPJzGUPm X-Received: by 2002:a05:6102:5090:b0:4c5:1c02:5b46 with SMTP id ada2fe7eead31-4dad3995502mr3091729137.25.1746031812656; Wed, 30 Apr 2025 09:50:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1746031812; cv=none; d=google.com; s=arc-20240605; b=iQ+LgPWBQTPSDQtbHHmI8XYp9mo5dws/bW/VAas3u2AZhpQW51jidXzAuJsAWIApSv nqHaPwS2VaT7Z722UVKEr4QgX+fPUhfrFqwj+0JIpUqxEZqhSHeE/5v7S1XugPIk9ZX6 a3dxNBMbYmFACZI6VVqhdjVWQXkfzJbozPYtzgh3brANmna6SeftUheovxVEiAeRlHIr usngGjJvsE5PVwH7QlctJfkOGVs+YEDpJzvGXciEW+roBf00sWvDMijpf13yoCnJiwQN sF1nOXYr1J4M6yxnv5G9kxgmgxbIw5JcJjJijzjA/DbmlPOl6cYwsn3mlJhn0VsBpgVF Wr2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=JSX6D5vgzNk6RAgZyLyRqAirOJHp5W5gvXuRkK9XdPE=; fh=6c3iePwzSVcIevU/n11cXtkmPbvvYSh1prLosaYzn/o=; b=j8IHxRxS/zudxtmRc32Dya4hVb74YdXEu2vl/TopMxpn9NkU3j999fYiV2KRPXptEZ gWO9LJ3INwDdceYB6IhTva1RY1FpQvQVjdFJlexLRbmSfFHMdzlzE8yJZcmp1RD0w2Se QazBrojvGpJjdPlnLXcJjbXk3RQa8tD2JnRBQjAueVZM0VZrv0MRU77iOWwMkwI+14zP ux4sUduaZwJO3j5Ofd3TewyIK0/gI0Xtg410rJxYzgC8uXfHqO2eogtuqwWPCFf+9Abi rNCWtXl01KdXl+vZf6YiTHxkinzk1vukYojxDcYWkOL3bCq0u/kQpqzFV0zMu8uDncyr wxKg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EHPl3b09; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.48.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:48:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 06/16] target/arm: Move cpu_get_tb_cpu_state to hflags.c Date: Wed, 30 Apr 2025 09:48:44 -0700 Message-ID: <20250430164854.2233995-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is a tcg-specific function, so move it to a tcg file. Also move mve_no_pred, a static function only used within cpu_get_tb_cpu_state. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/arm/helper.c | 110 ---------------------------------------- target/arm/tcg/hflags.c | 110 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+), 110 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 98adeb7086..360e6ac0f5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -30,7 +30,6 @@ #include "qemu/guest-random.h" #ifdef CONFIG_TCG #include "accel/tcg/probe.h" -#include "accel/tcg/cpu-ops.h" #include "semihosting/common-semi.h" #endif #include "cpregs.h" @@ -11424,115 +11423,6 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) return arm_mmu_idx_el(env, arm_current_el(env)); } -static bool mve_no_pred(CPUARMState *env) -{ - /* - * Return true if there is definitely no predication of MVE - * instructions by VPR or LTPSIZE. (Returning false even if there - * isn't any predication is OK; generated code will just be - * a little worse.) - * If the CPU does not implement MVE then this TB flag is always 0. - * - * NOTE: if you change this logic, the "recalculate s->mve_no_pred" - * logic in gen_update_fp_context() needs to be updated to match. - * - * We do not include the effect of the ECI bits here -- they are - * tracked in other TB flags. This simplifies the logic for - * "when did we emit code that changes the MVE_NO_PRED TB flag - * and thus need to end the TB?". - */ - if (cpu_isar_feature(aa32_mve, env_archcpu(env))) { - return false; - } - if (env->v7m.vpr) { - return false; - } - if (env->v7m.ltpsize < 4) { - return false; - } - return true; -} - -void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - CPUARMTBFlags flags; - - assert_hflags_rebuild_correctly(env); - flags = env->hflags; - - if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { - *pc = env->pc; - if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { - DP_TBFLAG_A64(flags, BTYPE, env->btype); - } - } else { - *pc = env->regs[15]; - - if (arm_feature(env, ARM_FEATURE_M)) { - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && - FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) - != env->v7m.secure) { - DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); - } - - if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && - (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || - (env->v7m.secure && - !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { - /* - * ASPEN is set, but FPCA/SFPA indicate that there is no - * active FP context; we must create a new FP context before - * executing any FP insn. - */ - DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); - } - - bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; - if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { - DP_TBFLAG_M32(flags, LSPACT, 1); - } - - if (mve_no_pred(env)) { - DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); - } - } else { - /* - * Note that XSCALE_CPAR shares bits with VECSTRIDE. - * Note that VECLEN+VECSTRIDE are RES0 for M-profile. - */ - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); - } else { - DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); - DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); - } - if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { - DP_TBFLAG_A32(flags, VFPEN, 1); - } - } - - DP_TBFLAG_AM32(flags, THUMB, env->thumb); - DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); - } - - /* - * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine - * states defined in the ARM ARM for software singlestep: - * SS_ACTIVE PSTATE.SS State - * 0 x Inactive (the TB flag for SS is always 0) - * 1 0 Active-pending - * 1 1 Active-not-pending - * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. - */ - if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { - DP_TBFLAG_ANY(flags, PSTATE__SS, 1); - } - - *pflags = flags.flags; - *cs_base = flags.flags2; -} - #ifdef TARGET_AARCH64 /* * The manual says that when SVE is enabled and VQ is widened the diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index e51d9f7b15..e530f65ed7 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -10,6 +10,7 @@ #include "internals.h" #include "cpu-features.h" #include "exec/helper-proto.h" +#include "accel/tcg/cpu-ops.h" #include "cpregs.h" static inline bool fgt_svc(CPUARMState *env, int el) @@ -513,3 +514,112 @@ void assert_hflags_rebuild_correctly(CPUARMState *env) } #endif } + +static bool mve_no_pred(CPUARMState *env) +{ + /* + * Return true if there is definitely no predication of MVE + * instructions by VPR or LTPSIZE. (Returning false even if there + * isn't any predication is OK; generated code will just be + * a little worse.) + * If the CPU does not implement MVE then this TB flag is always 0. + * + * NOTE: if you change this logic, the "recalculate s->mve_no_pred" + * logic in gen_update_fp_context() needs to be updated to match. + * + * We do not include the effect of the ECI bits here -- they are + * tracked in other TB flags. This simplifies the logic for + * "when did we emit code that changes the MVE_NO_PRED TB flag + * and thus need to end the TB?". + */ + if (cpu_isar_feature(aa32_mve, env_archcpu(env))) { + return false; + } + if (env->v7m.vpr) { + return false; + } + if (env->v7m.ltpsize < 4) { + return false; + } + return true; +} + +void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + CPUARMTBFlags flags; + + assert_hflags_rebuild_correctly(env); + flags = env->hflags; + + if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { + *pc = env->pc; + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { + DP_TBFLAG_A64(flags, BTYPE, env->btype); + } + } else { + *pc = env->regs[15]; + + if (arm_feature(env, ARM_FEATURE_M)) { + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && + FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) + != env->v7m.secure) { + DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); + } + + if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && + (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || + (env->v7m.secure && + !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { + /* + * ASPEN is set, but FPCA/SFPA indicate that there is no + * active FP context; we must create a new FP context before + * executing any FP insn. + */ + DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); + } + + bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; + if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { + DP_TBFLAG_M32(flags, LSPACT, 1); + } + + if (mve_no_pred(env)) { + DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); + } + } else { + /* + * Note that XSCALE_CPAR shares bits with VECSTRIDE. + * Note that VECLEN+VECSTRIDE are RES0 for M-profile. + */ + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); + } else { + DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); + DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); + } + if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { + DP_TBFLAG_A32(flags, VFPEN, 1); + } + } + + DP_TBFLAG_AM32(flags, THUMB, env->thumb); + DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); + } + + /* + * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine + * states defined in the ARM ARM for software singlestep: + * SS_ACTIVE PSTATE.SS State + * 0 x Inactive (the TB flag for SS is always 0) + * 1 0 Active-pending + * 1 1 Active-not-pending + * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. + */ + if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { + DP_TBFLAG_ANY(flags, PSTATE__SS, 1); + } + + *pflags = flags.flags; + *cs_base = flags.flags2; +} From patchwork Wed Apr 30 16:48:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 886065 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:38f:210b:807b with SMTP id g4csp957111wrq; Wed, 30 Apr 2025 09:50:08 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX9zkohpc8ntqtMooPdcDwpvNFineqzActlakyMPRgYIkfk03y6g/z8Rqesk3PXambXLplsIw==@linaro.org X-Google-Smtp-Source: AGHT+IEJVyE78sWwh4h/7UErtPUd/YIv7QRW6La5/KzuhZIxWVhePlsgrnbfe/AprRVA2/s3pkou X-Received: by 2002:ac8:6f0a:0:b0:47c:67b5:73da with SMTP id d75a77b69052e-48ad879b665mr2608331cf.13.1746031808211; Wed, 30 Apr 2025 09:50:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1746031808; cv=none; d=google.com; s=arc-20240605; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 07/16] target/arm: Unexport assert_hflags_rebuild_correctly Date: Wed, 30 Apr 2025 09:48:45 -0700 Message-ID: <20250430164854.2233995-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This function is no longer used outside of hflags.c. We can remove the stub as well. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/arm/internals.h | 2 -- target/arm/tcg-stubs.c | 4 ---- target/arm/tcg/hflags.c | 2 +- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 4d3d84ffeb..382a4d1015 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1906,8 +1906,6 @@ static inline bool arm_fgt_active(CPUARMState *env, int el) (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN)); } -void assert_hflags_rebuild_correctly(CPUARMState *env); - /* * Although the ARM implementation of hardware assisted debugging * allows for different breakpoints per-core, the current GDB diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c index 93a15cad61..5e5166c049 100644 --- a/target/arm/tcg-stubs.c +++ b/target/arm/tcg-stubs.c @@ -21,10 +21,6 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, { g_assert_not_reached(); } -/* Temporarily while cpu_get_tb_cpu_state() is still in common code */ -void assert_hflags_rebuild_correctly(CPUARMState *env) -{ -} /* TLBI insns are only used by TCG, so we don't need to do anything for KVM */ void define_tlb_insn_regs(ARMCPU *cpu) diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index e530f65ed7..5315264c28 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -499,7 +499,7 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); } -void assert_hflags_rebuild_correctly(CPUARMState *env) +static void assert_hflags_rebuild_correctly(CPUARMState *env) { #ifdef CONFIG_DEBUG_TCG CPUARMTBFlags c = env->hflags; From patchwork Wed Apr 30 16:48:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 886070 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:38f:210b:807b with SMTP id g4csp957791wrq; Wed, 30 Apr 2025 09:51:44 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVbtwjJS5SV/ijL7Xw9lw9v8IxvtGLy6vDOVoCCIxj36P9OXUK1HVZalUwis2OwcyldNohGCw==@linaro.org X-Google-Smtp-Source: AGHT+IGmd2bubIg/dz6OswIOAcLxZ0Q8N61NpXk9O/GjOALHvbdTxrACxwedNTVyiVD9hI7HSN/5 X-Received: by 2002:ac8:6f10:0:b0:472:6aa:d6be with SMTP id d75a77b69052e-489e4a8ccbbmr48882451cf.17.1746031904333; Wed, 30 Apr 2025 09:51:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1746031904; cv=none; d=google.com; s=arc-20240605; b=GfzoDTVjrr54yXXWxQ6hE5azTeTqspCEmNpoR+gNPJ87n2XTmZvh4hqZKQ2EBaEKqM VvpqVduIYbfM/CSdJfSagQPX6J+qYq3evQAEzWhDmRpRf8V3ztV+X9IXd4NxY23YjQCp JaSE3BnD2HYBYtFi87ES/ZT7tHB/I2xUmHSaWU+B0EjpEhwogdVaWuTAE0Gp8dJzQd4p OpXyhsZDulnzFxoCqsyK4yY0g/gW5FyDVP9oiruczR/we/uXhWUGdN4TMK8OMFru1OK3 oFS9QUJ94TzYGHlISjb2igYC932GwM15mYYsRk/hVvxpirRsbc+5ZdAgQSz5YzHTfkLn MGHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SpjRSP299/Pwnlg0y40yyEXNMYiNnhME3gCevLegoTY=; fh=6c3iePwzSVcIevU/n11cXtkmPbvvYSh1prLosaYzn/o=; b=eOyh+ZpfZYwYwcZgIj2YB95RMMTtW3/t+xdrDd9YqRlQjpwqOc5FwvlZcCalIIMova rUZjrjwnI/WHePDvlR7OrnfuhBCB5YM3ZaaLPXwoO1JUliC2mwVURsbxPBes+xB5UQDI suHto5od9G8Umkl7tGszTzU4nGlbfrWR2CxByiFTx/faMXqOAH9N3F0IIfFTD61dDOGb xRdQ5n42+Yv/Ei5xpEB861L9zpS0LCABcO/M4UH5SvWeRN9rvFGPM6YkJPjaTXCaZnzC zPt6gU1g3canpdlbO17wrnDhrFj4+wQ4ZEMap44fN7sZx+QLCLylDxZRlCLWYVhBRSPp WJYg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WkdPK8LA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 08/16] target/riscv: Move cpu_get_tb_cpu_state to tcg-cpu.c Date: Wed, 30 Apr 2025 09:48:46 -0700 Message-ID: <20250430164854.2233995-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This function is only relevant to tcg. Move it to a tcg-specific file. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 97 ------------------------------------- target/riscv/tcg/tcg-cpu.c | 98 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+), 97 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f2e90a9889..d5039f69a9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -135,103 +135,6 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt) #endif } -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - RISCVCPU *cpu = env_archcpu(env); - RISCVExtStatus fs, vs; - uint32_t flags = 0; - bool pm_signext = riscv_cpu_virt_mem_enabled(env); - - *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; - *cs_base = 0; - - if (cpu->cfg.ext_zve32x) { - /* - * If env->vl equals to VLMAX, we can use generic vector operation - * expanders (GVEC) to accerlate the vector operations. - * However, as LMUL could be a fractional number. The maximum - * vector size can be operated might be less than 8 bytes, - * which is not supported by GVEC. So we set vl_eq_vlmax flag to true - * only when maxsz >= 8 bytes. - */ - - /* lmul encoded as in DisasContext::lmul */ - int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3); - uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW); - uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); - uint32_t maxsz = vlmax << vsew; - bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && - (maxsz >= 8); - flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); - flags = FIELD_DP32(flags, TB_FLAGS, SEW, vsew); - flags = FIELD_DP32(flags, TB_FLAGS, LMUL, - FIELD_EX64(env->vtype, VTYPE, VLMUL)); - flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); - flags = FIELD_DP32(flags, TB_FLAGS, VTA, - FIELD_EX64(env->vtype, VTYPE, VTA)); - flags = FIELD_DP32(flags, TB_FLAGS, VMA, - FIELD_EX64(env->vtype, VTYPE, VMA)); - flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0); - } else { - flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); - } - - if (cpu_get_fcfien(env)) { - /* - * For Forward CFI, only the expectation of a lpad at - * the start of the block is tracked via env->elp. env->elp - * is turned on during jalr translation. - */ - flags = FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp); - flags = FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1); - } - - if (cpu_get_bcfien(env)) { - flags = FIELD_DP32(flags, TB_FLAGS, BCFI_ENABLED, 1); - } - -#ifdef CONFIG_USER_ONLY - fs = EXT_STATUS_DIRTY; - vs = EXT_STATUS_DIRTY; -#else - flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); - - flags |= riscv_env_mmu_index(env, 0); - fs = get_field(env->mstatus, MSTATUS_FS); - vs = get_field(env->mstatus, MSTATUS_VS); - - if (env->virt_enabled) { - flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); - /* - * Merge DISABLED and !DIRTY states using MIN. - * We will set both fields when dirtying. - */ - fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); - vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); - } - - /* With Zfinx, floating point is enabled/disabled by Smstateen. */ - if (!riscv_has_ext(env, RVF)) { - fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE) - ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; - } - - if (cpu->cfg.debug && !icount_enabled()) { - flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); - } -#endif - - flags = FIELD_DP32(flags, TB_FLAGS, FS, fs); - flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); - flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); - flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); - flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); - flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); - - *pflags = flags; -} - RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) { #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 50782e0f0e..e67de7dfe2 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -36,6 +36,7 @@ #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #include "system/tcg.h" +#include "exec/icount.h" #endif /* Hash that stores user set extensions */ @@ -97,6 +98,103 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) return riscv_env_mmu_index(cpu_env(cs), ifetch); } +void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + RISCVCPU *cpu = env_archcpu(env); + RISCVExtStatus fs, vs; + uint32_t flags = 0; + bool pm_signext = riscv_cpu_virt_mem_enabled(env); + + *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; + *cs_base = 0; + + if (cpu->cfg.ext_zve32x) { + /* + * If env->vl equals to VLMAX, we can use generic vector operation + * expanders (GVEC) to accerlate the vector operations. + * However, as LMUL could be a fractional number. The maximum + * vector size can be operated might be less than 8 bytes, + * which is not supported by GVEC. So we set vl_eq_vlmax flag to true + * only when maxsz >= 8 bytes. + */ + + /* lmul encoded as in DisasContext::lmul */ + int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3); + uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); + uint32_t maxsz = vlmax << vsew; + bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && + (maxsz >= 8); + flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); + flags = FIELD_DP32(flags, TB_FLAGS, SEW, vsew); + flags = FIELD_DP32(flags, TB_FLAGS, LMUL, + FIELD_EX64(env->vtype, VTYPE, VLMUL)); + flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); + flags = FIELD_DP32(flags, TB_FLAGS, VTA, + FIELD_EX64(env->vtype, VTYPE, VTA)); + flags = FIELD_DP32(flags, TB_FLAGS, VMA, + FIELD_EX64(env->vtype, VTYPE, VMA)); + flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0); + } else { + flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); + } + + if (cpu_get_fcfien(env)) { + /* + * For Forward CFI, only the expectation of a lpad at + * the start of the block is tracked via env->elp. env->elp + * is turned on during jalr translation. + */ + flags = FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp); + flags = FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1); + } + + if (cpu_get_bcfien(env)) { + flags = FIELD_DP32(flags, TB_FLAGS, BCFI_ENABLED, 1); + } + +#ifdef CONFIG_USER_ONLY + fs = EXT_STATUS_DIRTY; + vs = EXT_STATUS_DIRTY; +#else + flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); + + flags |= riscv_env_mmu_index(env, 0); + fs = get_field(env->mstatus, MSTATUS_FS); + vs = get_field(env->mstatus, MSTATUS_VS); + + if (env->virt_enabled) { + flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); + /* + * Merge DISABLED and !DIRTY states using MIN. + * We will set both fields when dirtying. + */ + fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); + vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); + } + + /* With Zfinx, floating point is enabled/disabled by Smstateen. */ + if (!riscv_has_ext(env, RVF)) { + fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE) + ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; + } + + if (cpu->cfg.debug && !icount_enabled()) { + flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); + } +#endif + + flags = FIELD_DP32(flags, TB_FLAGS, FS, fs); + flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); + flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); + flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); + flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); + flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); + + *pflags = flags; +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { From patchwork Wed Apr 30 16:48:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 886066 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:38f:210b:807b with SMTP id g4csp957107wrq; Wed, 30 Apr 2025 09:50:07 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVl6EZGxWhBQosVmOGLJ/y+7Esi4cNep0s77FJfBHT67pNklGzgMX+rwMEIY6PjTOjDDj8a6w==@linaro.org X-Google-Smtp-Source: AGHT+IG3+TIxEjRUyU5EZiStelbipLrcpBYJ7HYMZZU1DPBfvPZ7rR/21zlIc3lqCaSytcrXMhyt X-Received: by 2002:a05:620a:294c:b0:7c7:a5cd:5bd3 with SMTP id af79cd13be357-7cac7616c94mr509077285a.28.1746031807528; Wed, 30 Apr 2025 09:50:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1746031807; cv=none; d=google.com; s=arc-20240605; b=Qdvf3HuvSSnd3HEcK78EvWW5C3u9L156swlqIknnlzqdSd6dkaIEIhGAhgfpHbMbRQ t2saXH3Tq0XwW2VB4tMD8H/acIqqfnXlF++EBHMfDiecfcHAeN3vvxTQq1yKDRqYP4F9 imwsfc4z26IScuKvjN2s2Lb7aRhOrrJyIqLO3iBxiNURmeFG3wVp51F3Je0+P6PXUoza hk7IlHpDpGMBW3SPtadUfEuylxViQOv8H0djxwPpSR9zk9dn/AVE3ZbF6W1tMj560rsU YERv0OhfplEcL/QRJguGi7S2DcWihC/esnuKdk5bjR/2Tg702clCRRYaPw1Pq06CnWmw G92A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZrgNHkmVFQwH5odIUzOQLc+ZFJWjL7PB2mBMvbUpVdg=; fh=6c3iePwzSVcIevU/n11cXtkmPbvvYSh1prLosaYzn/o=; b=TKeiPdHtqIJFQAnTwMCQ/gfcY9n36rVyrgHElP6OpGy+YKWMtjaiSqe8Kx/hq01gEs UKU0jjINcVO5ZmcmnzryT2h3h5xyIWQh7R78ETohqNsWxlz+bJ6O0NejbyJh0icE7tZQ vmyXHiH6vbf39A5ZMgw/zx3ceaaBWBXT9wnQ2Pzh7USYrJe5KSFspHsc4Mi1v9Q0rsJi SSV5fNcx0cR1KvjStrPYKhJi3H9I/6iODyOZVxgMFni+kraxYcZRzd0MNfLNRI14uDn/ NmCKWSIAoZM+UMMk15X7df4iBpueyrCYGqy7ZOtVTdt4z1SPjYvp79eQQ6CnpdQGqxew gojQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VgJXJLnZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 09/16] accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_state Date: Wed, 30 Apr 2025 09:48:47 -0700 Message-ID: <20250430164854.2233995-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Combine 3 different pointer returns into one structure return. Include a cflags field in TCGTBCPUState, not filled in by cpu_get_tb_cpu_state, but used by all callers. This fills a hole in the structure and is useful in some subroutines. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/accel/tcg/cpu-ops.h | 4 +-- include/accel/tcg/tb-cpu-state.h | 18 ++++++++++ accel/tcg/cpu-exec.c | 56 +++++++++++++------------------- accel/tcg/translate-all.c | 8 ++--- target/alpha/cpu.c | 13 ++++---- target/arm/tcg/hflags.c | 17 ++++++---- target/avr/cpu.c | 9 ++--- target/hexagon/cpu.c | 15 +++++---- target/hppa/cpu.c | 10 +++--- target/i386/tcg/tcg-cpu.c | 19 +++++++---- target/loongarch/cpu.c | 20 +++++++----- target/m68k/cpu.c | 21 +++++++----- target/microblaze/cpu.c | 13 +++++--- target/mips/cpu.c | 14 ++++---- target/openrisc/cpu.c | 16 +++++---- target/ppc/helper_regs.c | 8 ++--- target/riscv/tcg/tcg-cpu.c | 12 +++---- target/rx/cpu.c | 14 ++++---- target/s390x/cpu.c | 14 ++++---- target/sh4/cpu.c | 22 +++++++++---- target/sparc/cpu.c | 17 ++++++---- target/tricore/cpu.c | 14 ++++---- target/xtensa/cpu.c | 40 +++++++++++++---------- 23 files changed, 218 insertions(+), 176 deletions(-) create mode 100644 include/accel/tcg/tb-cpu-state.h diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index f5e5746976..43a39c2e13 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -16,10 +16,10 @@ #include "exec/memop.h" #include "exec/mmu-access-type.h" #include "exec/vaddr.h" +#include "accel/tcg/tb-cpu-state.h" #include "tcg/tcg-mo.h" -void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs); struct TCGCPUOps { /** diff --git a/include/accel/tcg/tb-cpu-state.h b/include/accel/tcg/tb-cpu-state.h new file mode 100644 index 0000000000..8f912900ca --- /dev/null +++ b/include/accel/tcg/tb-cpu-state.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: LGPL-2.1-or-later */ +/* + * Definition of TCGTBCPUState. + */ + +#ifndef EXEC_TB_CPU_STATE_H +#define EXEC_TB_CPU_STATE_H + +#include "exec/vaddr.h" + +typedef struct TCGTBCPUState { + vaddr pc; + uint32_t flags; + uint32_t cflags; + uint64_t cs_base; +} TCGTBCPUState; + +#endif diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c21c5d202d..f7e7e7949d 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -385,9 +385,6 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) { CPUState *cpu = env_cpu(env); TranslationBlock *tb; - vaddr pc; - uint64_t cs_base; - uint32_t flags, cflags; /* * By definition we've just finished a TB, so I/O is OK. @@ -397,20 +394,21 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) * The next TB, if we chain to it, will clear the flag again. */ cpu->neg.can_do_io = true; - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - cflags = curr_cflags(cpu); - if (check_for_breakpoints(cpu, pc, &cflags)) { + TCGTBCPUState s = cpu_get_tb_cpu_state(cpu); + s.cflags = curr_cflags(cpu); + + if (check_for_breakpoints(cpu, s.pc, &s.cflags)) { cpu_loop_exit(cpu); } - tb = tb_lookup(cpu, pc, cs_base, flags, cflags); + tb = tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); if (tb == NULL) { return tcg_code_gen_epilogue; } if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) { - log_cpu_exec(pc, cpu, tb); + log_cpu_exec(s.pc, cpu, tb); } return tb->tc.ptr; @@ -560,11 +558,7 @@ static void cpu_exec_longjmp_cleanup(CPUState *cpu) void cpu_exec_step_atomic(CPUState *cpu) { - CPUArchState *env = cpu_env(cpu); TranslationBlock *tb; - vaddr pc; - uint64_t cs_base; - uint32_t flags, cflags; int tb_exit; if (sigsetjmp(cpu->jmp_env, 0) == 0) { @@ -573,13 +567,13 @@ void cpu_exec_step_atomic(CPUState *cpu) g_assert(!cpu->running); cpu->running = true; - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + TCGTBCPUState s = cpu_get_tb_cpu_state(cpu); + s.cflags = curr_cflags(cpu); - cflags = curr_cflags(cpu); /* Execute in a serial context. */ - cflags &= ~CF_PARALLEL; + s.cflags &= ~CF_PARALLEL; /* After 1 insn, return and release the exclusive lock. */ - cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1; + s.cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1; /* * No need to check_for_breakpoints here. * We only arrive in cpu_exec_step_atomic after beginning execution @@ -587,16 +581,16 @@ void cpu_exec_step_atomic(CPUState *cpu) * Any breakpoint for this insn will have been recognized earlier. */ - tb = tb_lookup(cpu, pc, cs_base, flags, cflags); + tb = tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); if (tb == NULL) { mmap_lock(); - tb = tb_gen_code(cpu, pc, cs_base, flags, cflags); + tb = tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags); mmap_unlock(); } cpu_exec_enter(cpu); /* execute the generated code */ - trace_exec_tb(tb, pc); + trace_exec_tb(tb, s.pc); cpu_tb_exec(cpu, tb, &tb_exit); cpu_exec_exit(cpu); } else { @@ -941,11 +935,8 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) while (!cpu_handle_interrupt(cpu, &last_tb)) { TranslationBlock *tb; - vaddr pc; - uint64_t cs_base; - uint32_t flags, cflags; - - cpu_get_tb_cpu_state(cpu_env(cpu), &pc, &cs_base, &flags); + TCGTBCPUState s = cpu_get_tb_cpu_state(cpu); + s.cflags = cpu->cflags_next_tb; /* * When requested, use an exact setting for cflags for the next @@ -954,33 +945,32 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) * have CF_INVALID set, -1 is a convenient invalid value that * does not require tcg headers for cpu_common_reset. */ - cflags = cpu->cflags_next_tb; - if (cflags == -1) { - cflags = curr_cflags(cpu); + if (s.cflags == -1) { + s.cflags = curr_cflags(cpu); } else { cpu->cflags_next_tb = -1; } - if (check_for_breakpoints(cpu, pc, &cflags)) { + if (check_for_breakpoints(cpu, s.pc, &s.cflags)) { break; } - tb = tb_lookup(cpu, pc, cs_base, flags, cflags); + tb = tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); if (tb == NULL) { CPUJumpCache *jc; uint32_t h; mmap_lock(); - tb = tb_gen_code(cpu, pc, cs_base, flags, cflags); + tb = tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags); mmap_unlock(); /* * We add the TB in the virtual pc hash table * for the fast lookup */ - h = tb_jmp_cache_hash_func(pc); + h = tb_jmp_cache_hash_func(s.pc); jc = cpu->tb_jmp_cache; - jc->array[h].pc = pc; + jc->array[h].pc = s.pc; qatomic_set(&jc->array[h].tb, tb); } @@ -1000,7 +990,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) tb_add_jump(last_tb, tb_exit, tb); } - cpu_loop_exec_tb(cpu, tb, pc, &last_tb, &tb_exit); + cpu_loop_exec_tb(cpu, tb, s.pc, &last_tb, &tb_exit); /* Try to align the host and virtual clocks if the guest is in advance */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 31c7f9927f..f2766cedfc 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -590,13 +590,9 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr) /* The exception probably happened in a helper. The CPU state should have been saved before calling it. Fetch the PC from there. */ CPUArchState *env = cpu_env(cpu); - vaddr pc; - uint64_t cs_base; - tb_page_addr_t addr; - uint32_t flags; + TCGTBCPUState s = cpu_get_tb_cpu_state(cpu); + tb_page_addr_t addr = get_page_addr_code(env, s.pc); - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - addr = get_page_addr_code(env, pc); if (addr != -1) { tb_invalidate_phys_range(cpu, addr, addr); } diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 134806e755..90e3a2e748 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -41,15 +41,16 @@ static vaddr alpha_cpu_get_pc(CPUState *cs) return env->pc; } -void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc = env->pc; - *cs_base = 0; - *pflags = env->flags & ENV_FLAG_TB_MASK; + CPUAlphaState *env = cpu_env(cs); + uint32_t flags = env->flags & ENV_FLAG_TB_MASK; + #ifdef CONFIG_USER_ONLY - *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; + flags |= TB_FLAG_UNALIGN * !cs->prctl_unalign_sigbus; #endif + + return (TCGTBCPUState){ .pc = env->pc, .flags = flags }; } static void alpha_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 5315264c28..b49381924b 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -10,6 +10,7 @@ #include "internals.h" #include "cpu-features.h" #include "exec/helper-proto.h" +#include "exec/translation-block.h" #include "accel/tcg/cpu-ops.h" #include "cpregs.h" @@ -544,21 +545,22 @@ static bool mve_no_pred(CPUARMState *env) return true; } -void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUARMState *env = cpu_env(cs); CPUARMTBFlags flags; + vaddr pc; assert_hflags_rebuild_correctly(env); flags = env->hflags; if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { - *pc = env->pc; + pc = env->pc; if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { DP_TBFLAG_A64(flags, BTYPE, env->btype); } } else { - *pc = env->regs[15]; + pc = env->regs[15]; if (arm_feature(env, ARM_FEATURE_M)) { if (arm_feature(env, ARM_FEATURE_M_SECURITY) && @@ -620,6 +622,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, DP_TBFLAG_ANY(flags, PSTATE__SS, 1); } - *pflags = flags.flags; - *cs_base = flags.flags2; + return (TCGTBCPUState){ + .pc = pc, + .flags = flags.flags, + .cs_base = flags.flags2, + }; } diff --git a/target/avr/cpu.c b/target/avr/cpu.c index d9fecb272e..683195b61d 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -54,14 +54,11 @@ static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } -void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUAVRState *env = cpu_env(cs); uint32_t flags = 0; - *pc = env->pc_w * 2; - *cs_base = 0; - if (env->fullacc) { flags |= TB_FLAGS_FULL_ACCESS; } @@ -69,7 +66,7 @@ void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, flags |= TB_FLAGS_SKIP; } - *pflags = flags; + return (TCGTBCPUState){ .pc = env->pc_w * 2, .flags = flags }; } static void avr_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 2272f1222b..a7f76dd089 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -255,19 +255,20 @@ static vaddr hexagon_cpu_get_pc(CPUState *cs) return cpu_env(cs)->gpr[HEX_REG_PC]; } -void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUHexagonState *env = cpu_env(cs); + vaddr pc = env->gpr[HEX_REG_PC]; uint32_t hex_flags = 0; - *pc = env->gpr[HEX_REG_PC]; - *cs_base = 0; - if (*pc == env->gpr[HEX_REG_SA0]) { + + if (pc == env->gpr[HEX_REG_SA0]) { hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); } - *flags = hex_flags; - if (*pc & PCALIGN_MASK) { + if (pc & PCALIGN_MASK) { hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); } + + return (TCGTBCPUState){ .pc = pc, .flags = hex_flags }; } static void hexagon_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 4cdaf98ab1..40cbc191bb 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -51,11 +51,12 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) env->iaoq_f & -4); } -void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *pcsbase, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUHPPAState *env = cpu_env(cs); uint32_t flags = 0; uint64_t cs_base = 0; + vaddr pc; /* * TB lookup assumes that PC contains the complete virtual address. @@ -63,7 +64,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, * incomplete virtual address. This also means that we must separate * out current cpu privilege from the low bits of IAOQ_F. */ - *pc = hppa_cpu_get_pc(env_cpu(env)); + pc = hppa_cpu_get_pc(env_cpu(env)); flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; /* @@ -99,8 +100,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, } #endif - *pcsbase = cs_base; - *pflags = flags; + return (TCGTBCPUState){ .pc = pc, .flags = flags, .cs_base = cs_base }; } static void hppa_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index bb6f82befb..3004fb3023 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -48,18 +48,23 @@ static void x86_cpu_exec_exit(CPUState *cs) env->eflags = cpu_compute_eflags(env); } -void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *flags = env->hflags | + CPUX86State *env = cpu_env(cs); + uint32_t flags, cs_base; + vaddr pc; + + flags = env->hflags | (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); if (env->hflags & HF_CS64_MASK) { - *cs_base = 0; - *pc = env->eip; + cs_base = 0; + pc = env->eip; } else { - *cs_base = env->segs[R_CS].base; - *pc = (uint32_t)(*cs_base + env->eip); + cs_base = env->segs[R_CS].base; + pc = (uint32_t)(cs_base + env->eip); } + + return (TCGTBCPUState){ .pc = pc, .flags = flags, .cs_base = cs_base }; } static void x86_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index be770b7e19..446cf43914 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -336,16 +336,18 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } #endif -void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc = env->pc; - *cs_base = 0; - *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); - *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; - *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE; - *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE; - *flags |= is_va32(env) * HW_FLAGS_VA32; + CPULoongArchState *env = cpu_env(cs); + uint32_t flags; + + flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); + flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; + flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE; + flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE; + flags |= is_va32(env) * HW_FLAGS_VA32; + + return (TCGTBCPUState){ .pc = env->pc, .flags = flags }; } static void loongarch_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 2b4ec40509..b75ed6e887 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "migration/vmstate.h" #include "fpu/softfloat.h" +#include "exec/translation-block.h" #include "accel/tcg/cpu-ops.h" static void m68k_cpu_set_pc(CPUState *cs, vaddr value) @@ -39,20 +40,22 @@ static vaddr m68k_cpu_get_pc(CPUState *cs) return cpu->env.pc; } -void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc = env->pc; - *cs_base = 0; - *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; + CPUM68KState *env = cpu_env(cs); + uint32_t flags; + + flags = (env->macsr >> 4) & TB_FLAGS_MACSR; if (env->sr & SR_S) { - *flags |= TB_FLAGS_MSR_S; - *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; - *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; + flags |= TB_FLAGS_MSR_S; + flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; + flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; } if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) { - *flags |= TB_FLAGS_TRACE; + flags |= TB_FLAGS_TRACE; } + + return (TCGTBCPUState){ .pc = env->pc, .flags = flags }; } static void m68k_restore_state_to_opc(CPUState *cs, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 105ede0b1e..72a0d0583c 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -95,12 +95,15 @@ static vaddr mb_cpu_get_pc(CPUState *cs) return cpu->env.pc; } -void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc = env->pc; - *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); - *cs_base = (*flags & IMM_FLAG ? env->imm : 0); + CPUMBState *env = cpu_env(cs); + + return (TCGTBCPUState){ + .pc = env->pc, + .flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK), + .cs_base = (env->iflags & IMM_FLAG ? env->imm : 0), + }; } static void mb_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index ab00adf86b..b0f7612a64 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -549,13 +549,15 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) return mips_env_mmu_index(cpu_env(cs)); } -void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc = env->active_tc.PC; - *cs_base = 0; - *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | - MIPS_HFLAG_HWRENA_ULR); + CPUMIPSState *env = cpu_env(cs); + + return (TCGTBCPUState){ + .pc = env->active_tc.PC, + .flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | + MIPS_HFLAG_HWRENA_ULR), + }; } static const TCGCPUOps mips_tcg_ops = { diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index d798127d67..aba4639bbb 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -41,14 +41,16 @@ static vaddr openrisc_cpu_get_pc(CPUState *cs) return cpu->env.pc; } -void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc = env->pc; - *cs_base = 0; - *flags = (env->dflag ? TB_FLAGS_DFLAG : 0) - | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) - | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); + CPUOpenRISCState *env = cpu_env(cs); + + return (TCGTBCPUState){ + .pc = env->pc, + .flags = ((env->dflag ? TB_FLAGS_DFLAG : 0) + | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) + | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE))), + }; } static void openrisc_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 8d248bcbb9..ccaf2b0343 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -256,9 +256,9 @@ void hreg_update_pmu_hflags(CPUPPCState *env) env->hflags |= hreg_compute_pmu_hflags_value(env); } -void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUPPCState *env = cpu_env(cs); uint32_t hflags_current = env->hflags; #ifdef CONFIG_DEBUG_TCG @@ -270,9 +270,7 @@ void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, } #endif - *pc = env->nip; - *cs_base = 0; - *flags = hflags_current; + return (TCGTBCPUState){ .pc = env->nip, .flags = hflags_current }; } void cpu_interrupt_exittb(CPUState *cs) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e67de7dfe2..927153377e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -98,17 +98,14 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) return riscv_env_mmu_index(cpu_env(cs), ifetch); } -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPURISCVState *env = cpu_env(cs); RISCVCPU *cpu = env_archcpu(env); RISCVExtStatus fs, vs; uint32_t flags = 0; bool pm_signext = riscv_cpu_virt_mem_enabled(env); - *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; - *cs_base = 0; - if (cpu->cfg.ext_zve32x) { /* * If env->vl equals to VLMAX, we can use generic vector operation @@ -192,7 +189,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); - *pflags = flags; + return (TCGTBCPUState){ + .pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc, + .flags = flags + }; } static void riscv_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index e8b47be675..be778c9f65 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -44,13 +44,15 @@ static vaddr rx_cpu_get_pc(CPUState *cs) return cpu->env.pc; } -void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc = env->pc; - *cs_base = 0; - *flags = FIELD_DP32(0, PSW, PM, env->psw_pm); - *flags = FIELD_DP32(*flags, PSW, U, env->psw_u); + CPURXState *env = cpu_env(cs); + uint32_t flags = 0; + + flags = FIELD_DP32(flags, PSW, PM, env->psw_pm); + flags = FIELD_DP32(flags, PSW, U, env->psw_u); + + return (TCGTBCPUState){ .pc = env->pc, .flags = flags }; } static void rx_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 435b2034ff..279289f265 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -309,9 +309,9 @@ static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch) return s390x_env_mmu_index(cpu_env(cs), ifetch); } -void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUS390XState *env = cpu_env(cs); uint32_t flags; if (env->psw.addr & 1) { @@ -323,9 +323,6 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); } - *pc = env->psw.addr; - *cs_base = env->ex_value; - flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; if (env->psw.mask & PSW_MASK_PER) { flags |= env->cregs[9] & (FLAG_MASK_PER_BRANCH | @@ -342,7 +339,12 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, if (env->cregs[0] & CR0_VECTOR) { flags |= FLAG_MASK_VECTOR; } - *pflags = flags; + + return (TCGTBCPUState){ + .pc = env->psw.addr, + .flags = flags, + .cs_base = env->ex_value, + }; } static const TCGCPUOps s390_tcg_ops = { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 5fb18bf55e..cbd43b55e5 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -43,19 +43,27 @@ static vaddr superh_cpu_get_pc(CPUState *cs) return cpu->env.pc; } -void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc = env->pc; - /* For a gUSA region, notice the end of the region. */ - *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; - *flags = env->flags + CPUSH4State *env = cpu_env(cs); + uint32_t flags; + + flags = env->flags | (env->fpscr & TB_FLAG_FPSCR_MASK) | (env->sr & TB_FLAG_SR_MASK) | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ #ifdef CONFIG_USER_ONLY - *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; + flags |= TB_FLAG_UNALIGN * !cs->prctl_unalign_sigbus; #endif + + return (TCGTBCPUState){ + .pc = env->pc, + .flags = flags, +#ifdef CONFIG_USER_ONLY + /* For a gUSA region, notice the end of the region. */ + .cs_base = flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0, +#endif + }; } static void superh_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index bbdea8556a..6166b81f71 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -716,13 +716,11 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, cpu->env.npc = tb->cs_base; } -void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - uint32_t flags; - *pc = env->pc; - *cs_base = env->npc; - flags = cpu_mmu_index(env_cpu(env), false); + CPUSPARCState *env = cpu_env(cs); + uint32_t flags = cpu_mmu_index(cs, false); + #ifndef CONFIG_USER_ONLY if (cpu_supervisor_mode(env)) { flags |= TB_FLAG_SUPER; @@ -751,7 +749,12 @@ void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, } #endif /* !CONFIG_USER_ONLY */ #endif /* TARGET_SPARC64 */ - *pflags = flags; + + return (TCGTBCPUState){ + .pc = env->pc, + .flags = flags, + .cs_base = env->npc, + }; } static void sparc_restore_state_to_opc(CPUState *cs, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 81b3bb6362..1151a812b6 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -45,16 +45,14 @@ static vaddr tricore_cpu_get_pc(CPUState *cs) return cpu_env(cs)->PC; } -void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - uint32_t new_flags = 0; - *pc = env->PC; - *cs_base = 0; + CPUTriCoreState *env = cpu_env(cs); - new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV, - extract32(env->PSW, 10, 2)); - *flags = new_flags; + return (TCGTBCPUState){ + .pc = env->PC, + .flags = FIELD_DP32(0, TB_FLAGS, PRIV, extract32(env->PSW, 10, 2)), + }; } static void tricore_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c78ef9421c..431b7ebd7b 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -55,15 +55,15 @@ static vaddr xtensa_cpu_get_pc(CPUState *cs) return cpu->env.pc; } -void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc = env->pc; - *cs_base = 0; - *flags = 0; - *flags |= xtensa_get_ring(env); + CPUXtensaState *env = cpu_env(cs); + uint32_t flags = 0; + target_ulong cs_base = 0; + + flags |= xtensa_get_ring(env); if (env->sregs[PS] & PS_EXCM) { - *flags |= XTENSA_TBFLAG_EXCM; + flags |= XTENSA_TBFLAG_EXCM; } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { target_ulong lend_dist = env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); @@ -85,26 +85,26 @@ void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) { target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG]; - *cs_base = lend_dist; + cs_base = lend_dist; if (lbeg_off < 256) { - *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; + cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; } } } if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && (env->sregs[LITBASE] & 1)) { - *flags |= XTENSA_TBFLAG_LITBASE; + flags |= XTENSA_TBFLAG_LITBASE; } if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { if (xtensa_get_cintlevel(env) < env->config->debug_level) { - *flags |= XTENSA_TBFLAG_DEBUG; + flags |= XTENSA_TBFLAG_DEBUG; } if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { - *flags |= XTENSA_TBFLAG_ICOUNT; + flags |= XTENSA_TBFLAG_ICOUNT; } } if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { - *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; + flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; } if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) && (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) { @@ -112,15 +112,21 @@ void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, (env->sregs[WINDOW_BASE] + 1); uint32_t w = ctz32(windowstart | 0x8); - *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; - *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT, + flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; + flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT, PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; } else { - *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT; + flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT; } if (env->yield_needed) { - *flags |= XTENSA_TBFLAG_YIELD; + flags |= XTENSA_TBFLAG_YIELD; } + + return (TCGTBCPUState){ + .pc = env->pc, + .flags = flags, + .cs_base = cs_base, + }; } static void xtensa_restore_state_to_opc(CPUState *cs, From patchwork Wed Apr 30 16:48:48 2025 Content-Type: text/plain; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 10/16] accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps Date: Wed, 30 Apr 2025 09:48:48 -0700 Message-ID: <20250430164854.2233995-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move the global function name to a hook on TCGCPUOps. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 8 ++++++-- target/arm/internals.h | 2 ++ target/ppc/internal.h | 3 +++ accel/tcg/cpu-exec.c | 7 ++++--- accel/tcg/translate-all.c | 2 +- target/alpha/cpu.c | 3 ++- target/arm/cpu.c | 1 + target/arm/tcg/cpu-v7m.c | 1 + target/arm/tcg/hflags.c | 2 +- target/avr/cpu.c | 3 ++- target/hexagon/cpu.c | 3 ++- target/hppa/cpu.c | 3 ++- target/i386/tcg/tcg-cpu.c | 3 ++- target/loongarch/cpu.c | 3 ++- target/m68k/cpu.c | 3 ++- target/microblaze/cpu.c | 3 ++- target/mips/cpu.c | 3 ++- target/openrisc/cpu.c | 3 ++- target/ppc/cpu_init.c | 2 +- target/ppc/helper_regs.c | 3 ++- target/riscv/tcg/tcg-cpu.c | 3 ++- target/rx/cpu.c | 3 ++- target/s390x/cpu.c | 3 ++- target/sh4/cpu.c | 3 ++- target/sparc/cpu.c | 3 ++- target/tricore/cpu.c | 3 ++- target/xtensa/cpu.c | 3 ++- 27 files changed, 56 insertions(+), 26 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 43a39c2e13..23cd6af0b2 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -19,8 +19,6 @@ #include "accel/tcg/tb-cpu-state.h" #include "tcg/tcg-mo.h" -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs); - struct TCGCPUOps { /** * mttcg_supported: multi-threaded TCG is supported @@ -63,6 +61,12 @@ struct TCGCPUOps { */ void (*translate_code)(CPUState *cpu, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc); + /** + * @get_tb_cpu_state: Extract CPU state for a TCG #TranslationBlock + * + * Fill in all data required to select or compile a TranslationBlock. + */ + TCGTBCPUState (*get_tb_cpu_state)(CPUState *cs); /** * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock * diff --git a/target/arm/internals.h b/target/arm/internals.h index 382a4d1015..660d3a88e0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -28,6 +28,7 @@ #include "exec/hwaddr.h" #include "exec/vaddr.h" #include "exec/breakpoint.h" +#include "accel/tcg/tb-cpu-state.h" #include "hw/registerfields.h" #include "tcg/tcg-gvec-desc.h" #include "system/memory.h" @@ -372,6 +373,7 @@ void arm_restore_state_to_opc(CPUState *cs, const uint64_t *data); #ifdef CONFIG_TCG +TCGTBCPUState arm_get_tb_cpu_state(CPUState *cs); void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); /* Our implementation of TCGCPUOps::cpu_exec_halt */ diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 9012d3809c..7723350227 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -21,6 +21,7 @@ #include "exec/breakpoint.h" #include "hw/registerfields.h" #include "exec/page-protection.h" +#include "accel/tcg/tb-cpu-state.h" /* PM instructions */ typedef enum { @@ -308,4 +309,6 @@ static inline int ger_pack_masks(int pmsk, int ymsk, int xmsk) return msk; } +TCGTBCPUState ppc_get_tb_cpu_state(CPUState *cs); + #endif /* PPC_INTERNAL_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f7e7e7949d..4a405d7b56 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -395,7 +395,7 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) */ cpu->neg.can_do_io = true; - TCGTBCPUState s = cpu_get_tb_cpu_state(cpu); + TCGTBCPUState s = cpu->cc->tcg_ops->get_tb_cpu_state(cpu); s.cflags = curr_cflags(cpu); if (check_for_breakpoints(cpu, s.pc, &s.cflags)) { @@ -567,7 +567,7 @@ void cpu_exec_step_atomic(CPUState *cpu) g_assert(!cpu->running); cpu->running = true; - TCGTBCPUState s = cpu_get_tb_cpu_state(cpu); + TCGTBCPUState s = cpu->cc->tcg_ops->get_tb_cpu_state(cpu); s.cflags = curr_cflags(cpu); /* Execute in a serial context. */ @@ -935,7 +935,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) while (!cpu_handle_interrupt(cpu, &last_tb)) { TranslationBlock *tb; - TCGTBCPUState s = cpu_get_tb_cpu_state(cpu); + TCGTBCPUState s = cpu->cc->tcg_ops->get_tb_cpu_state(cpu); s.cflags = cpu->cflags_next_tb; /* @@ -1052,6 +1052,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) assert(tcg_ops->cpu_exec_reset); #endif /* !CONFIG_USER_ONLY */ assert(tcg_ops->translate_code); + assert(tcg_ops->get_tb_cpu_state); assert(tcg_ops->mmu_index); tcg_ops->initialize(); tcg_target_initialized = true; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index f2766cedfc..97aadee52c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -590,7 +590,7 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr) /* The exception probably happened in a helper. The CPU state should have been saved before calling it. Fetch the PC from there. */ CPUArchState *env = cpu_env(cpu); - TCGTBCPUState s = cpu_get_tb_cpu_state(cpu); + TCGTBCPUState s = cpu->cc->tcg_ops->get_tb_cpu_state(cpu); tb_page_addr_t addr = get_page_addr_code(env, s.pc); if (addr != -1) { diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 90e3a2e748..890b84c032 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -41,7 +41,7 @@ static vaddr alpha_cpu_get_pc(CPUState *cs) return env->pc; } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState alpha_get_tb_cpu_state(CPUState *cs) { CPUAlphaState *env = cpu_env(cs); uint32_t flags = env->flags & ENV_FLAG_TB_MASK; @@ -251,6 +251,7 @@ static const TCGCPUOps alpha_tcg_ops = { .initialize = alpha_translate_init, .translate_code = alpha_translate_code, + .get_tb_cpu_state = alpha_get_tb_cpu_state, .synchronize_from_tb = alpha_cpu_synchronize_from_tb, .restore_state_to_opc = alpha_restore_state_to_opc, .mmu_index = alpha_cpu_mmu_index, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3dde70b04a..2020aec54a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2693,6 +2693,7 @@ static const TCGCPUOps arm_tcg_ops = { .initialize = arm_translate_init, .translate_code = arm_translate_code, + .get_tb_cpu_state = arm_get_tb_cpu_state, .synchronize_from_tb = arm_cpu_synchronize_from_tb, .debug_excp_handler = arm_debug_excp_handler, .restore_state_to_opc = arm_restore_state_to_opc, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 5c8c374885..95b23d9b55 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -238,6 +238,7 @@ static const TCGCPUOps arm_v7m_tcg_ops = { .initialize = arm_translate_init, .translate_code = arm_translate_code, + .get_tb_cpu_state = arm_get_tb_cpu_state, .synchronize_from_tb = arm_cpu_synchronize_from_tb, .debug_excp_handler = arm_debug_excp_handler, .restore_state_to_opc = arm_restore_state_to_opc, diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index b49381924b..fd407a7b28 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -545,7 +545,7 @@ static bool mve_no_pred(CPUARMState *env) return true; } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +TCGTBCPUState arm_get_tb_cpu_state(CPUState *cs) { CPUARMState *env = cpu_env(cs); CPUARMTBFlags flags; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 683195b61d..250241541b 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -54,7 +54,7 @@ static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState avr_get_tb_cpu_state(CPUState *cs) { CPUAVRState *env = cpu_env(cs); uint32_t flags = 0; @@ -241,6 +241,7 @@ static const TCGCPUOps avr_tcg_ops = { .mttcg_supported = false, .initialize = avr_cpu_tcg_init, .translate_code = avr_cpu_translate_code, + .get_tb_cpu_state = avr_get_tb_cpu_state, .synchronize_from_tb = avr_cpu_synchronize_from_tb, .restore_state_to_opc = avr_restore_state_to_opc, .mmu_index = avr_cpu_mmu_index, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index a7f76dd089..a5a04173ab 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -255,7 +255,7 @@ static vaddr hexagon_cpu_get_pc(CPUState *cs) return cpu_env(cs)->gpr[HEX_REG_PC]; } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState *cs) { CPUHexagonState *env = cpu_env(cs); vaddr pc = env->gpr[HEX_REG_PC]; @@ -344,6 +344,7 @@ static const TCGCPUOps hexagon_tcg_ops = { .mttcg_supported = false, .initialize = hexagon_translate_init, .translate_code = hexagon_translate_code, + .get_tb_cpu_state = hexagon_get_tb_cpu_state, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, .restore_state_to_opc = hexagon_restore_state_to_opc, .mmu_index = hexagon_cpu_mmu_index, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 40cbc191bb..6465181543 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -51,7 +51,7 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) env->iaoq_f & -4); } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState hppa_get_tb_cpu_state(CPUState *cs) { CPUHPPAState *env = cpu_env(cs); uint32_t flags = 0; @@ -262,6 +262,7 @@ static const TCGCPUOps hppa_tcg_ops = { .initialize = hppa_translate_init, .translate_code = hppa_translate_code, + .get_tb_cpu_state = hppa_get_tb_cpu_state, .synchronize_from_tb = hppa_cpu_synchronize_from_tb, .restore_state_to_opc = hppa_restore_state_to_opc, .mmu_index = hppa_cpu_mmu_index, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 3004fb3023..179dfdf064 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -48,7 +48,7 @@ static void x86_cpu_exec_exit(CPUState *cs) env->eflags = cpu_compute_eflags(env); } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState x86_get_tb_cpu_state(CPUState *cs) { CPUX86State *env = cpu_env(cs); uint32_t flags, cs_base; @@ -160,6 +160,7 @@ const TCGCPUOps x86_tcg_ops = { .guest_default_memory_order = TCG_MO_ALL & ~TCG_MO_ST_LD, .initialize = tcg_x86_init, .translate_code = x86_translate_code, + .get_tb_cpu_state = x86_get_tb_cpu_state, .synchronize_from_tb = x86_cpu_synchronize_from_tb, .restore_state_to_opc = x86_restore_state_to_opc, .mmu_index = x86_cpu_mmu_index, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 446cf43914..f7535d1be7 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -336,7 +336,7 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } #endif -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState loongarch_get_tb_cpu_state(CPUState *cs) { CPULoongArchState *env = cpu_env(cs); uint32_t flags; @@ -882,6 +882,7 @@ static const TCGCPUOps loongarch_tcg_ops = { .initialize = loongarch_translate_init, .translate_code = loongarch_translate_code, + .get_tb_cpu_state = loongarch_get_tb_cpu_state, .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, .restore_state_to_opc = loongarch_restore_state_to_opc, .mmu_index = loongarch_cpu_mmu_index, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index b75ed6e887..c5196a612e 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -40,7 +40,7 @@ static vaddr m68k_cpu_get_pc(CPUState *cs) return cpu->env.pc; } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState m68k_get_tb_cpu_state(CPUState *cs) { CPUM68KState *env = cpu_env(cs); uint32_t flags; @@ -613,6 +613,7 @@ static const TCGCPUOps m68k_tcg_ops = { .initialize = m68k_tcg_init, .translate_code = m68k_translate_code, + .get_tb_cpu_state = m68k_get_tb_cpu_state, .restore_state_to_opc = m68k_restore_state_to_opc, .mmu_index = m68k_cpu_mmu_index, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 72a0d0583c..d069e40e70 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -95,7 +95,7 @@ static vaddr mb_cpu_get_pc(CPUState *cs) return cpu->env.pc; } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState mb_get_tb_cpu_state(CPUState *cs) { CPUMBState *env = cpu_env(cs); @@ -442,6 +442,7 @@ static const TCGCPUOps mb_tcg_ops = { .initialize = mb_tcg_init, .translate_code = mb_translate_code, + .get_tb_cpu_state = mb_get_tb_cpu_state, .synchronize_from_tb = mb_cpu_synchronize_from_tb, .restore_state_to_opc = mb_restore_state_to_opc, .mmu_index = mb_cpu_mmu_index, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index b0f7612a64..4cbfb9435a 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -549,7 +549,7 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) return mips_env_mmu_index(cpu_env(cs)); } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState mips_get_tb_cpu_state(CPUState *cs) { CPUMIPSState *env = cpu_env(cs); @@ -566,6 +566,7 @@ static const TCGCPUOps mips_tcg_ops = { .initialize = mips_tcg_init, .translate_code = mips_translate_code, + .get_tb_cpu_state = mips_get_tb_cpu_state, .synchronize_from_tb = mips_cpu_synchronize_from_tb, .restore_state_to_opc = mips_restore_state_to_opc, .mmu_index = mips_cpu_mmu_index, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index aba4639bbb..054ad33360 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -41,7 +41,7 @@ static vaddr openrisc_cpu_get_pc(CPUState *cs) return cpu->env.pc; } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState openrisc_get_tb_cpu_state(CPUState *cs) { CPUOpenRISCState *env = cpu_env(cs); @@ -258,6 +258,7 @@ static const TCGCPUOps openrisc_tcg_ops = { .initialize = openrisc_translate_init, .translate_code = openrisc_translate_code, + .get_tb_cpu_state = openrisc_get_tb_cpu_state, .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, .restore_state_to_opc = openrisc_restore_state_to_opc, .mmu_index = openrisc_cpu_mmu_index, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 3a01731402..cf88a18244 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -45,7 +45,6 @@ #include "internal.h" #include "spr_common.h" #include "power8-pmu.h" - #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #include "hw/intc/intc.h" @@ -7483,6 +7482,7 @@ static const TCGCPUOps ppc_tcg_ops = { .guest_default_memory_order = 0, .initialize = ppc_translate_init, .translate_code = ppc_translate_code, + .get_tb_cpu_state = ppc_get_tb_cpu_state, .restore_state_to_opc = ppc_restore_state_to_opc, .mmu_index = ppc_cpu_mmu_index, diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index ccaf2b0343..7e5726871e 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -28,6 +28,7 @@ #include "cpu-models.h" #include "spr_common.h" #include "accel/tcg/cpu-ops.h" +#include "internal.h" /* Swap temporary saved registers with GPRs */ void hreg_swap_gpr_tgpr(CPUPPCState *env) @@ -256,7 +257,7 @@ void hreg_update_pmu_hflags(CPUPPCState *env) env->hflags |= hreg_compute_pmu_hflags_value(env); } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +TCGTBCPUState ppc_get_tb_cpu_state(CPUState *cs) { CPUPPCState *env = cpu_env(cs); uint32_t hflags_current = env->hflags; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 927153377e..55e00972b7 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -98,7 +98,7 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) return riscv_env_mmu_index(cpu_env(cs), ifetch); } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs) { CPURISCVState *env = cpu_env(cs); RISCVCPU *cpu = env_archcpu(env); @@ -243,6 +243,7 @@ const TCGCPUOps riscv_tcg_ops = { .initialize = riscv_translate_init, .translate_code = riscv_translate_code, + .get_tb_cpu_state = riscv_get_tb_cpu_state, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, .restore_state_to_opc = riscv_restore_state_to_opc, .mmu_index = riscv_cpu_mmu_index, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index be778c9f65..36eba75545 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -44,7 +44,7 @@ static vaddr rx_cpu_get_pc(CPUState *cs) return cpu->env.pc; } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState rx_get_tb_cpu_state(CPUState *cs) { CPURXState *env = cpu_env(cs); uint32_t flags = 0; @@ -220,6 +220,7 @@ static const TCGCPUOps rx_tcg_ops = { .initialize = rx_translate_init, .translate_code = rx_translate_code, + .get_tb_cpu_state = rx_get_tb_cpu_state, .synchronize_from_tb = rx_cpu_synchronize_from_tb, .restore_state_to_opc = rx_restore_state_to_opc, .mmu_index = rx_cpu_mmu_index, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 279289f265..9c1158ebcc 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -309,7 +309,7 @@ static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch) return s390x_env_mmu_index(cpu_env(cs), ifetch); } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState s390x_get_tb_cpu_state(CPUState *cs) { CPUS390XState *env = cpu_env(cs); uint32_t flags; @@ -358,6 +358,7 @@ static const TCGCPUOps s390_tcg_ops = { .initialize = s390x_translate_init, .translate_code = s390x_translate_code, + .get_tb_cpu_state = s390x_get_tb_cpu_state, .restore_state_to_opc = s390x_restore_state_to_opc, .mmu_index = s390x_cpu_mmu_index, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index cbd43b55e5..b35f18e250 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -43,7 +43,7 @@ static vaddr superh_cpu_get_pc(CPUState *cs) return cpu->env.pc; } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState superh_get_tb_cpu_state(CPUState *cs) { CPUSH4State *env = cpu_env(cs); uint32_t flags; @@ -289,6 +289,7 @@ static const TCGCPUOps superh_tcg_ops = { .initialize = sh4_translate_init, .translate_code = sh4_translate_code, + .get_tb_cpu_state = superh_get_tb_cpu_state, .synchronize_from_tb = superh_cpu_synchronize_from_tb, .restore_state_to_opc = superh_restore_state_to_opc, .mmu_index = sh4_cpu_mmu_index, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 6166b81f71..2a3e408923 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -716,7 +716,7 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, cpu->env.npc = tb->cs_base; } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState sparc_get_tb_cpu_state(CPUState *cs) { CPUSPARCState *env = cpu_env(cs); uint32_t flags = cpu_mmu_index(cs, false); @@ -1029,6 +1029,7 @@ static const TCGCPUOps sparc_tcg_ops = { .initialize = sparc_tcg_init, .translate_code = sparc_translate_code, + .get_tb_cpu_state = sparc_get_tb_cpu_state, .synchronize_from_tb = sparc_cpu_synchronize_from_tb, .restore_state_to_opc = sparc_restore_state_to_opc, .mmu_index = sparc_cpu_mmu_index, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 1151a812b6..e56f90fde9 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -45,7 +45,7 @@ static vaddr tricore_cpu_get_pc(CPUState *cs) return cpu_env(cs)->PC; } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState tricore_get_tb_cpu_state(CPUState *cs) { CPUTriCoreState *env = cpu_env(cs); @@ -185,6 +185,7 @@ static const TCGCPUOps tricore_tcg_ops = { .mttcg_supported = false, .initialize = tricore_tcg_init, .translate_code = tricore_translate_code, + .get_tb_cpu_state = tricore_get_tb_cpu_state, .synchronize_from_tb = tricore_cpu_synchronize_from_tb, .restore_state_to_opc = tricore_restore_state_to_opc, .mmu_index = tricore_cpu_mmu_index, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 431b7ebd7b..91b71b6caa 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -55,7 +55,7 @@ static vaddr xtensa_cpu_get_pc(CPUState *cs) return cpu->env.pc; } -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState xtensa_get_tb_cpu_state(CPUState *cs) { CPUXtensaState *env = cpu_env(cs); uint32_t flags = 0; @@ -312,6 +312,7 @@ static const TCGCPUOps xtensa_tcg_ops = { .initialize = xtensa_translate_init, .translate_code = xtensa_translate_code, .debug_excp_handler = xtensa_breakpoint_handler, + .get_tb_cpu_state = xtensa_get_tb_cpu_state, .restore_state_to_opc = xtensa_restore_state_to_opc, .mmu_index = xtensa_cpu_mmu_index, From patchwork Wed Apr 30 16:48:49 2025 Content-Type: text/plain; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 11/16] accel/tcg: Pass TCGTBCPUState to tb_lookup Date: Wed, 30 Apr 2025 09:48:49 -0700 Message-ID: <20250430164854.2233995-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/cpu-exec.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 4a405d7b56..808983e461 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -232,35 +232,33 @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu, vaddr pc, * * Returns: an existing translation block or NULL. */ -static inline TranslationBlock *tb_lookup(CPUState *cpu, vaddr pc, - uint64_t cs_base, uint32_t flags, - uint32_t cflags) +static inline TranslationBlock *tb_lookup(CPUState *cpu, TCGTBCPUState s) { TranslationBlock *tb; CPUJumpCache *jc; uint32_t hash; /* we should never be trying to look up an INVALID tb */ - tcg_debug_assert(!(cflags & CF_INVALID)); + tcg_debug_assert(!(s.cflags & CF_INVALID)); - hash = tb_jmp_cache_hash_func(pc); + hash = tb_jmp_cache_hash_func(s.pc); jc = cpu->tb_jmp_cache; tb = qatomic_read(&jc->array[hash].tb); if (likely(tb && - jc->array[hash].pc == pc && - tb->cs_base == cs_base && - tb->flags == flags && - tb_cflags(tb) == cflags)) { + jc->array[hash].pc == s.pc && + tb->cs_base == s.cs_base && + tb->flags == s.flags && + tb_cflags(tb) == s.cflags)) { goto hit; } - tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags); + tb = tb_htable_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); if (tb == NULL) { return NULL; } - jc->array[hash].pc = pc; + jc->array[hash].pc = s.pc; qatomic_set(&jc->array[hash].tb, tb); hit: @@ -268,7 +266,7 @@ hit: * As long as tb is not NULL, the contents are consistent. Therefore, * the virtual PC has to match for non-CF_PCREL translations. */ - assert((tb_cflags(tb) & CF_PCREL) || tb->pc == pc); + assert((tb_cflags(tb) & CF_PCREL) || tb->pc == s.pc); return tb; } @@ -402,7 +400,7 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) cpu_loop_exit(cpu); } - tb = tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb = tb_lookup(cpu, s); if (tb == NULL) { return tcg_code_gen_epilogue; } @@ -581,7 +579,7 @@ void cpu_exec_step_atomic(CPUState *cpu) * Any breakpoint for this insn will have been recognized earlier. */ - tb = tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb = tb_lookup(cpu, s); if (tb == NULL) { mmap_lock(); tb = tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags); @@ -955,7 +953,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) break; } - tb = tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb = tb_lookup(cpu, s); if (tb == NULL) { CPUJumpCache *jc; uint32_t h; From patchwork Wed Apr 30 16:48:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 886076 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:38f:210b:807b with SMTP id g4csp958042wrq; Wed, 30 Apr 2025 09:52:17 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWH7TqRGTDmRzy0nb+7KRRIbA9hMOp3xHvD9+PVvzqua7cX4bA9xM1ivzar7BkSUtIyiL5nvA==@linaro.org X-Google-Smtp-Source: AGHT+IFInNoaWRmBrhe43O3yjWWnXwT4A9UCp+gaKCcZWULus59qdszod71mAzhwpZytYRZWz+es X-Received: by 2002:a05:622a:5e17:b0:476:aa7a:2f78 with SMTP id d75a77b69052e-489c550cc45mr71669531cf.49.1746031937608; Wed, 30 Apr 2025 09:52:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1746031937; cv=none; d=google.com; s=arc-20240605; b=CE1Lwu//jC6P62Kqwrzn8gDGpd55uXnxqWM2bljBBbGyejV4CGJK2hJukJyrko0VQv F+m66XWpRkV1bOr25DIzMO207Uq88jI7dm3euZQi7/MIpaywFv5TEK+DG5Wnzteu+uir sSHAVHxa9TpIxlpECMl4aPnM/gX1ff4T2ykMHDD3FAIwC2z+OOMCOqlam9vIn19LGQZl BzjN8QSz1XS1B3e6FC40dBDluZV/1IGYkgSCItNffCSdHATIIAC3Fn5ezw6jyRh+8Y1X n+YxQhjDqQmT1Zn8/yXTQNqQivX8Aym7UrACs9hNt6GGjh0dMe5ImIdWcemKUenAMW22 jI9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+erat6AyDf4aFwvHPMIYlKBGQpGrVV5ItGv/2Xtf4+w=; fh=6c3iePwzSVcIevU/n11cXtkmPbvvYSh1prLosaYzn/o=; b=JZ9bPPLdOanCKMdJmzwyhpcAJTItX8R4kfvKmpf6GFJORPhAFODhnKBqoXxms+VavY Raxr3j3eVjrd6ui40Yn/v+IccO3OO5XXOaRCzt+yBSfs//i2PYjegF4KqclLtDxEMQXN SXjKxwZ2gtJckA8rld9SeoIC6nGLJoWGNuYjt0HiGc4QjE53XPy+4h6U4MDeLJJUyWCY FyMBhq2O4R25EDRj+aF3OSOFsL7M9EYoS2q3rdnpXTIHtVg1AUz/rrKXuE1PiI7DueZT oAsKSNjact4AgBC78IIONUsazO89a7vjgxcixH0sqhPeTCYSv0b8+M6aCpamrz5BrSZt 5mfQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZKpfl0KD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 12/16] accel/tcg: Pass TCGTBCPUState to tb_htable_lookup Date: Wed, 30 Apr 2025 09:48:50 -0700 Message-ID: <20250430164854.2233995-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/cpu-exec.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 808983e461..8e6899950e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -195,26 +195,24 @@ static bool tb_lookup_cmp(const void *p, const void *d) return false; } -static TranslationBlock *tb_htable_lookup(CPUState *cpu, vaddr pc, - uint64_t cs_base, uint32_t flags, - uint32_t cflags) +static TranslationBlock *tb_htable_lookup(CPUState *cpu, TCGTBCPUState s) { tb_page_addr_t phys_pc; struct tb_desc desc; uint32_t h; desc.env = cpu_env(cpu); - desc.cs_base = cs_base; - desc.flags = flags; - desc.cflags = cflags; - desc.pc = pc; - phys_pc = get_page_addr_code(desc.env, pc); + desc.cs_base = s.cs_base; + desc.flags = s.flags; + desc.cflags = s.cflags; + desc.pc = s.pc; + phys_pc = get_page_addr_code(desc.env, s.pc); if (phys_pc == -1) { return NULL; } desc.page_addr0 = phys_pc; - h = tb_hash_func(phys_pc, (cflags & CF_PCREL ? 0 : pc), - flags, cs_base, cflags); + h = tb_hash_func(phys_pc, (s.cflags & CF_PCREL ? 0 : s.pc), + s.flags, s.cs_base, s.cflags); return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); } @@ -253,7 +251,7 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, TCGTBCPUState s) goto hit; } - tb = tb_htable_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb = tb_htable_lookup(cpu, s); if (tb == NULL) { return NULL; } From patchwork Wed Apr 30 16:48:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 886064 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:38f:210b:807b with SMTP id g4csp957061wrq; Wed, 30 Apr 2025 09:50:01 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWuorud7DEsc+LauUYF5pZMWxB5aluf27dARzNbJgIFWzn+rRUPdFtGteaAH9lWxAzPjSsAxw==@linaro.org X-Google-Smtp-Source: AGHT+IFgny0SiIT29148/ZS9bTr1ttdpuaKVRaa1RguUpxw0i3/VcsTtLOM10kALO6DkvhiG5BbJ X-Received: by 2002:a05:6214:2584:b0:6e8:fb92:dffa with SMTP id 6a1803df08f44-6f4fe081236mr49090256d6.25.1746031801702; Wed, 30 Apr 2025 09:50:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1746031801; cv=none; d=google.com; s=arc-20240605; b=Me6bz4F4y/w464jXmyvetT9s2z5caaF9eS+A96Nwx5Hcamy0OFIhJPE8DHifWLOZ0L Qstb20QRMUiQH4UphWJZN+FdnTdsgGNjXeyuAt0U+EmiVc6E0ylErKHoyGZotYv61h2j cS7FqXbMcXnO+rBHc9pHe8xPy8XNcri3QVj+CD/fd7NgMQjapQaf/TTV7wytTffq+ta5 UMMnTJORhJksv7cGw31h81MFWAFQn6W/SR17ukaaORz9NcSTiweDrEJBkATLeFG/WOpU Xy8YfTd4ai70rqe3mGa7RGabRKlwDr91f+2/0JkoncpdXWk+86mYOUnsJqWBgI4ecjoP O7Sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3OA/Cegqwe9p0yD6ikSN7G53T07JOQms4URcLJNl+RA=; fh=6c3iePwzSVcIevU/n11cXtkmPbvvYSh1prLosaYzn/o=; b=izHlUQ/dIxqVcZt7JHRoqyhYU7W3mz2P6sYFKmI/vNn1JzhtleVgKB1Tl/aI3I6lNY 2Op1XUlfpk6+qL6OZt5vNakCxAu3kd0p4IH9Gt9VaEodX0xZXDKZlJOZm0t9hJu0B61o /f6NaZA1ZXxVNOhDlnsj5Zl7HTrl0zD7DqIqUKKijHkNbCH6OmvWVtPRNslI0VfN4MuZ TZ15E30OCNRs3hVChcscyptTPVdNn64FJygoi65ykXvnvHLetQNgYOs3IOmeAndoKl92 zm6M+vZlTVq5kTg76s/08ajheRm8EHKx/Yi5oZsQ4wcAFeejnyJc6Hp2v+c8hthtls3j 7YEA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sbq1nLre; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 13/16] accel/tcg: Use TCGTBCPUState in struct tb_desc Date: Wed, 30 Apr 2025 09:48:51 -0700 Message-ID: <20250430164854.2233995-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/cpu-exec.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8e6899950e..4ad84c2db8 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -150,12 +150,9 @@ static void init_delay_params(SyncClocks *sc, const CPUState *cpu) #endif /* CONFIG USER ONLY */ struct tb_desc { - vaddr pc; - uint64_t cs_base; + TCGTBCPUState s; CPUArchState *env; tb_page_addr_t page_addr0; - uint32_t flags; - uint32_t cflags; }; static bool tb_lookup_cmp(const void *p, const void *d) @@ -163,11 +160,11 @@ static bool tb_lookup_cmp(const void *p, const void *d) const TranslationBlock *tb = p; const struct tb_desc *desc = d; - if ((tb_cflags(tb) & CF_PCREL || tb->pc == desc->pc) && + if ((tb_cflags(tb) & CF_PCREL || tb->pc == desc->s.pc) && tb_page_addr0(tb) == desc->page_addr0 && - tb->cs_base == desc->cs_base && - tb->flags == desc->flags && - tb_cflags(tb) == desc->cflags) { + tb->cs_base == desc->s.cs_base && + tb->flags == desc->s.flags && + tb_cflags(tb) == desc->s.cflags) { /* check next page if needed */ tb_page_addr_t tb_phys_page1 = tb_page_addr1(tb); if (tb_phys_page1 == -1) { @@ -185,7 +182,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) * is different for the new TB. Therefore any exception raised * here by the faulting lookup is not premature. */ - virt_page1 = TARGET_PAGE_ALIGN(desc->pc); + virt_page1 = TARGET_PAGE_ALIGN(desc->s.pc); phys_page1 = get_page_addr_code(desc->env, virt_page1); if (tb_phys_page1 == phys_page1) { return true; @@ -201,11 +198,8 @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu, TCGTBCPUState s) struct tb_desc desc; uint32_t h; + desc.s = s; desc.env = cpu_env(cpu); - desc.cs_base = s.cs_base; - desc.flags = s.flags; - desc.cflags = s.cflags; - desc.pc = s.pc; phys_pc = get_page_addr_code(desc.env, s.pc); if (phys_pc == -1) { return NULL; From patchwork Wed Apr 30 16:48:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 886068 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:38f:210b:807b with SMTP id g4csp957293wrq; Wed, 30 Apr 2025 09:50:37 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVf4f76V7oGJhLaPAlxgBKxKP53f6syrrF9vFG1vHINRYhAFd52LXGbvt/L5dvq1ye4aF9Kpw==@linaro.org X-Google-Smtp-Source: AGHT+IGSqJz5/LDwyUB0uovB4+LEur12BQ2Hvxaj0jyWhoyUqv83lKKNIqLf0360OZ4sNf6ZfaTN X-Received: by 2002:a05:6102:c15:b0:4c3:6393:8448 with SMTP id ada2fe7eead31-4dad48c5957mr2723418137.1.1746031837323; Wed, 30 Apr 2025 09:50:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1746031837; cv=none; d=google.com; s=arc-20240605; b=VxpTs64WiebclA7F8NHbLbuubydSpUK407EFd39Sab++hV6LQut1dL7T+2Z76u7RBv iVhsoejWi856ZFXLk3FdvKq3xzJn/t0NO9M0vq8S7eb0TRlx6/EwCuFjk/jXVrq6DbbS yb7B0rqxrg6IZIsWfP/ZZjNKyrFsprQPEI+gcXraPhp/eInACvNNZqFPIYuMJbdXo5Yh P5c8BrQFpdyHLCAUOuwRSdHVZ+5PAR0q+tsnc7ZuVm4crMe+PpEGBw0TjpR8+3xgjNvQ WwlweXZ/tccGU58cMMvdAxTyIYFj1yfo61SHUl6Xw89IM17RPItx6nCzD+STVefshbOz YYqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TNItTYCqljpWXCYmXErceMTzMhdQ1ZlNvx1ZSBZc8tk=; fh=6c3iePwzSVcIevU/n11cXtkmPbvvYSh1prLosaYzn/o=; b=Rv2DzoxPGpXjrkD/BEmxFotdkTq0nh72w7MkyQckHLgS9zh+FotosyEoEHxFinvzdu WiDkEuZc8HMpQB9Unw5QSfGe0wirn6zGQNUB6O/asOichsr6FmYPN77HwWcRlTkR0i1v mu4eE3HI8uAEiu0cbgA9C495rppJ/jEjqYguZg0gL1BULayxty1MjJTjr0Tq2rntLfXo yaHWhm3+woVy2Uj2rPcej3/7/b621p0rY/vS4JW+mirFP/sMK5P2EclD0WgIKhQpMeg5 lUWxhyuBumKRy3XN/96EbKIRCiKMI57mKJjU2h7Kxo2M1RyVYbG5WnBLd+gqzdwM6aux rUcQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g41GqAog; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 14/16] accel/tcg: Pass TCGTBCPUState to tb_gen_code Date: Wed, 30 Apr 2025 09:48:52 -0700 Message-ID: <20250430164854.2233995-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/internal-common.h | 5 ++--- accel/tcg/cpu-exec.c | 4 ++-- accel/tcg/translate-all.c | 28 +++++++++++++--------------- 3 files changed, 17 insertions(+), 20 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 98c702422f..1dbc45dd95 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -12,6 +12,7 @@ #include "exec/cpu-common.h" #include "exec/translation-block.h" #include "exec/mmap-lock.h" +#include "accel/tcg/tb-cpu-state.h" extern int64_t max_delay; extern int64_t max_advance; @@ -46,9 +47,7 @@ static inline bool cpu_plugin_mem_cbs_enabled(const CPUState *cpu) #endif } -TranslationBlock *tb_gen_code(CPUState *cpu, vaddr pc, - uint64_t cs_base, uint32_t flags, - int cflags); +TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s); void page_init(void); void tb_htable_init(void); void tb_reset_jump(TranslationBlock *tb, int n); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 4ad84c2db8..a7436d2873 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -574,7 +574,7 @@ void cpu_exec_step_atomic(CPUState *cpu) tb = tb_lookup(cpu, s); if (tb == NULL) { mmap_lock(); - tb = tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb = tb_gen_code(cpu, s); mmap_unlock(); } @@ -951,7 +951,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) uint32_t h; mmap_lock(); - tb = tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb = tb_gen_code(cpu, s); mmap_unlock(); /* diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 97aadee52c..7b0bd50904 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -290,9 +290,7 @@ static int setjmp_gen_code(CPUArchState *env, TranslationBlock *tb, } /* Called with mmap_lock held for user mode emulation. */ -TranslationBlock *tb_gen_code(CPUState *cpu, - vaddr pc, uint64_t cs_base, - uint32_t flags, int cflags) +TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s) { CPUArchState *env = cpu_env(cpu); TranslationBlock *tb, *existing_tb; @@ -305,14 +303,14 @@ TranslationBlock *tb_gen_code(CPUState *cpu, assert_memory_lock(); qemu_thread_jit_write(); - phys_pc = get_page_addr_code_hostp(env, pc, &host_pc); + phys_pc = get_page_addr_code_hostp(env, s.pc, &host_pc); if (phys_pc == -1) { /* Generate a one-shot TB with 1 insn in it */ - cflags = (cflags & ~CF_COUNT_MASK) | 1; + s.cflags = (s.cflags & ~CF_COUNT_MASK) | 1; } - max_insns = cflags & CF_COUNT_MASK; + max_insns = s.cflags & CF_COUNT_MASK; if (max_insns == 0) { max_insns = TCG_MAX_INSNS; } @@ -332,12 +330,12 @@ TranslationBlock *tb_gen_code(CPUState *cpu, gen_code_buf = tcg_ctx->code_gen_ptr; tb->tc.ptr = tcg_splitwx_to_rx(gen_code_buf); - if (!(cflags & CF_PCREL)) { - tb->pc = pc; + if (!(s.cflags & CF_PCREL)) { + tb->pc = s.pc; } - tb->cs_base = cs_base; - tb->flags = flags; - tb->cflags = cflags; + tb->cs_base = s.cs_base; + tb->flags = s.flags; + tb->cflags = s.cflags; tb_set_page_addr0(tb, phys_pc); tb_set_page_addr1(tb, -1); if (phys_pc != -1) { @@ -355,9 +353,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->guest_mo = cpu->cc->tcg_ops->guest_default_memory_order; restart_translate: - trace_translate_block(tb, pc, tb->tc.ptr); + trace_translate_block(tb, s.pc, tb->tc.ptr); - gen_code_size = setjmp_gen_code(env, tb, pc, host_pc, &max_insns, &ti); + gen_code_size = setjmp_gen_code(env, tb, s.pc, host_pc, &max_insns, &ti); if (unlikely(gen_code_size < 0)) { switch (gen_code_size) { case -1: @@ -434,10 +432,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu, * For CF_PCREL, attribute all executions of the generated code * to its first mapping. */ - perf_report_code(pc, tb, tcg_splitwx_to_rx(gen_code_buf)); + perf_report_code(s.pc, tb, tcg_splitwx_to_rx(gen_code_buf)); if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) && - qemu_log_in_addr_range(pc)) { + qemu_log_in_addr_range(s.pc)) { FILE *logfile = qemu_log_trylock(); if (logfile) { int code_size, data_size; From patchwork Wed Apr 30 16:48:53 2025 Content-Type: text/plain; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 15/16] accel/tcg: Split out accel/tcg/helper-retaddr.h Date: Wed, 30 Apr 2025 09:48:53 -0700 Message-ID: <20250430164854.2233995-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move set_helper_retaddr and clear_helper_retaddr to a new header file. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ldst.h | 34 ----------------------- include/accel/tcg/helper-retaddr.h | 43 ++++++++++++++++++++++++++++++ accel/tcg/cpu-exec.c | 1 + accel/tcg/user-exec.c | 1 + target/arm/tcg/helper-a64.c | 1 + target/arm/tcg/sme_helper.c | 1 + target/arm/tcg/sve_helper.c | 1 + target/ppc/mem_helper.c | 1 + target/s390x/tcg/mem_helper.c | 1 + 9 files changed, 50 insertions(+), 34 deletions(-) create mode 100644 include/accel/tcg/helper-retaddr.h diff --git a/include/accel/tcg/cpu-ldst.h b/include/accel/tcg/cpu-ldst.h index f97a730703..44a62b54da 100644 --- a/include/accel/tcg/cpu-ldst.h +++ b/include/accel/tcg/cpu-ldst.h @@ -526,38 +526,4 @@ void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, MMUAccessType access_type, int mmu_idx); #endif -/* - * For user-only, helpers that use guest to host address translation - * must protect the actual host memory access by recording 'retaddr' - * for the signal handler. This is required for a race condition in - * which another thread unmaps the page between a probe and the - * actual access. - */ -#ifdef CONFIG_USER_ONLY -extern __thread uintptr_t helper_retaddr; - -static inline void set_helper_retaddr(uintptr_t ra) -{ - helper_retaddr = ra; - /* - * Ensure that this write is visible to the SIGSEGV handler that - * may be invoked due to a subsequent invalid memory operation. - */ - signal_barrier(); -} - -static inline void clear_helper_retaddr(void) -{ - /* - * Ensure that previous memory operations have succeeded before - * removing the data visible to the signal handler. - */ - signal_barrier(); - helper_retaddr = 0; -} -#else -#define set_helper_retaddr(ra) do { } while (0) -#define clear_helper_retaddr() do { } while (0) -#endif - #endif /* ACCEL_TCG_CPU_LDST_H */ diff --git a/include/accel/tcg/helper-retaddr.h b/include/accel/tcg/helper-retaddr.h new file mode 100644 index 0000000000..037fda2b83 --- /dev/null +++ b/include/accel/tcg/helper-retaddr.h @@ -0,0 +1,43 @@ +/* + * Get user helper pc for memory unwinding. + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ACCEL_TCG_HELPER_RETADDR_H +#define ACCEL_TCG_HELPER_RETADDR_H + +/* + * For user-only, helpers that use guest to host address translation + * must protect the actual host memory access by recording 'retaddr' + * for the signal handler. This is required for a race condition in + * which another thread unmaps the page between a probe and the + * actual access. + */ +#ifdef CONFIG_USER_ONLY +extern __thread uintptr_t helper_retaddr; + +static inline void set_helper_retaddr(uintptr_t ra) +{ + helper_retaddr = ra; + /* + * Ensure that this write is visible to the SIGSEGV handler that + * may be invoked due to a subsequent invalid memory operation. + */ + signal_barrier(); +} + +static inline void clear_helper_retaddr(void) +{ + /* + * Ensure that previous memory operations have succeeded before + * removing the data visible to the signal handler. + */ + signal_barrier(); + helper_retaddr = 0; +} +#else +#define set_helper_retaddr(ra) do { } while (0) +#define clear_helper_retaddr() do { } while (0) +#endif + +#endif /* ACCEL_TCG_HELPER_RETADDR_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index a7436d2873..a8fbda31ba 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -24,6 +24,7 @@ #include "hw/core/cpu.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/helper-retaddr.h" #include "trace.h" #include "disas/disas.h" #include "exec/cpu-common.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 70feee8df9..68e01fc584 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -26,6 +26,7 @@ #include "qemu/bitops.h" #include "qemu/rcu.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "accel/tcg/probe.h" #include "user/cpu_loop.h" #include "qemu/main-loop.h" diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 9cffda07cd..4f618ae390 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -30,6 +30,7 @@ #include "qemu/crc32c.h" #include "exec/cpu-common.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "accel/tcg/probe.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 3226895cae..de0c6e54d4 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -23,6 +23,7 @@ #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "qemu/int128.h" #include "fpu/softfloat.h" #include "vec_internal.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 9f20ecb51d..a2c363a4e1 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -30,6 +30,7 @@ #include "vec_internal.h" #include "sve_ldst_internal.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "accel/tcg/cpu-ops.h" #include "accel/tcg/probe.h" #ifdef CONFIG_USER_ONLY diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index aa1af44d22..6ab71a6fcb 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "helper_regs.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "accel/tcg/probe.h" #include "internal.h" #include "qemu/atomic128.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 857005b120..a03609a140 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -32,6 +32,7 @@ #include "exec/target_page.h" #include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/helper-retaddr.h" #include "qemu/int128.h" #include "qemu/atomic128.h" From patchwork Wed Apr 30 16:48:54 2025 Content-Type: text/plain; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 16/16] accel/tcg: Compile cpu-exec.c twice Date: Wed, 30 Apr 2025 09:48:54 -0700 Message-ID: <20250430164854.2233995-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 2 -- accel/tcg/meson.build | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index a8fbda31ba..cc5f362305 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -22,7 +22,6 @@ #include "qapi/error.h" #include "qapi/type-helpers.h" #include "hw/core/cpu.h" -#include "accel/tcg/cpu-ldst.h" #include "accel/tcg/cpu-ops.h" #include "accel/tcg/helper-retaddr.h" #include "trace.h" @@ -37,7 +36,6 @@ #include "qemu/rcu.h" #include "exec/log.h" #include "qemu/main-loop.h" -#include "cpu.h" #include "exec/icount.h" #include "exec/replay-core.h" #include "system/tcg.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 3f7b127130..0bb089299b 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -5,6 +5,7 @@ endif tcg_ss = ss.source_set() tcg_ss.add(files( + 'cpu-exec.c', 'cpu-exec-common.c', 'tcg-runtime.c', 'tcg-runtime-gvec.c', @@ -21,7 +22,6 @@ libsystem_ss.add_all(tcg_ss) tcg_specific_ss = ss.source_set() tcg_specific_ss.add(files( 'tcg-all.c', - 'cpu-exec.c', 'translate-all.c', )) tcg_specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'))